JPS63275197A - Manufacture of multilayered printed substrate - Google Patents
Manufacture of multilayered printed substrateInfo
- Publication number
- JPS63275197A JPS63275197A JP62111523A JP11152387A JPS63275197A JP S63275197 A JPS63275197 A JP S63275197A JP 62111523 A JP62111523 A JP 62111523A JP 11152387 A JP11152387 A JP 11152387A JP S63275197 A JPS63275197 A JP S63275197A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- intermediate layer
- formation
- layer
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000010030 laminating Methods 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- 239000002253 acid Substances 0.000 abstract description 2
- 238000005260 corrosion Methods 0.000 abstract 2
- 230000007797 corrosion Effects 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 2
- 238000003475 lamination Methods 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000003513 alkali Substances 0.000 description 4
- 239000002585 base Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910000365 copper sulfate Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- USFZMSVCRYTOJT-UHFFFAOYSA-N Ammonium acetate Chemical compound N.CC(O)=O USFZMSVCRYTOJT-UHFFFAOYSA-N 0.000 description 2
- 239000005695 Ammonium acetate Substances 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229940043376 ammonium acetate Drugs 0.000 description 2
- 235000019257 ammonium acetate Nutrition 0.000 description 2
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910000366 copper(II) sulfate Inorganic materials 0.000 description 2
- OPQARKPSCNTWTJ-UHFFFAOYSA-L copper(ii) acetate Chemical compound [Cu+2].CC([O-])=O.CC([O-])=O OPQARKPSCNTWTJ-UHFFFAOYSA-L 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 244000269722 Thea sinensis Species 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
中間層基板上に回路パターンと該回路パターンの所定の
個所に抵抗体を形成し、次いで前記抵抗体を内蔵した中
間層基板を積層して多層プリント基板に形成する製造方
法であって、中間層基板を積層するに際し、その前工程
で行う積層前処理酸化工程において硫酸等の酸液で抵抗
体が侵されてその抵抗値が変化することを防止するため
、前記積層前処理工程を抵抗体形成工程の前で行うよう
にしている。[Detailed Description of the Invention] [Summary] A circuit pattern and a resistor are formed on a predetermined location of the circuit pattern on an intermediate layer substrate, and then the intermediate layer substrate containing the resistor is laminated to form a multilayer printed circuit board. A manufacturing method for forming an intermediate layer substrate, in order to prevent the resistor from being attacked by an acid solution such as sulfuric acid and changing its resistance value in the pre-lamination oxidation step performed in the pre-layering process when laminating the intermediate layer substrate. , the lamination pretreatment process is performed before the resistor formation process.
（産業上の利用分野）
本発明は中間層基板に抵抗体を内蔵した多層プリント基
板の製造方法に係り、特に製造工程中に抵抗体の抵抗値
変化を防止するとともに、高品質の多層プリント基板が
得られるようにした多層プリント基板の製造方法に関す
るものである。(Industrial Application Field) The present invention relates to a method for manufacturing a multilayer printed circuit board in which a resistor is built into an intermediate layer board, and in particular, to prevent changes in the resistance value of the resistor during the manufacturing process, and to produce a high quality multilayer printed circuit board. The present invention relates to a method for manufacturing a multilayer printed circuit board that allows for the production of multilayer printed circuit boards.
多層プリント基板の実装密度を高くするために中間層基
板に抵抗体を設けて電気回路を構成している。かかる抵
抗体を内蔵した中間層基板においては、その製造工程に
おいて規定値の抵抗体を得ることは勿論、抵抗値の変化
を防止することが必要となる。In order to increase the packaging density of a multilayer printed circuit board, a resistor is provided on the intermediate layer board to form an electric circuit. In an intermediate layer substrate incorporating such a resistor, it is necessary not only to obtain a resistor having a specified value in the manufacturing process, but also to prevent changes in the resistance value.
第３図は従来の多層プリント基板製造工程のブロック図
、第４図ｆａｔ〜ｆｈｌは従来の製造工程における中間
層基板の側断面図を示している。FIG. 3 is a block diagram of a conventional multilayer printed circuit board manufacturing process, and FIGS. 4, fat to fhl, are side sectional views of an intermediate layer board in the conventional manufacturing process.
第３図において、従来の多層プリント基板の製造は、基
材（ガラス・エポキシ板）上に回路パターン（以後パタ
ーンと記す）を形成するパターン形成工程１と、パター
ン形成工程１で形成されたパターンに抵抗体を形成する
抵抗体形成工程２と、抵抗体形成工程２後の中間層基板
の積層前処理を行う積層前処理工程３と、中間層基板を
積層して多層プリント基板を形成する積層工程４とより
構成されている。In Figure 3, the conventional manufacturing of a multilayer printed circuit board consists of a pattern forming process 1 in which a circuit pattern (hereinafter referred to as a pattern) is formed on a base material (glass epoxy board), and a pattern formed in pattern forming process 1. a resistor formation step 2 in which a resistor is formed in the resistor formation step 2; a lamination pretreatment step 3 in which the intermediate layer substrate is pre-laminated after the resistor formation step 2; and a lamination step 3 in which the intermediate layer substrates are laminated to form a multilayer printed circuit board. It consists of step 4.
中間層基板の製造方法をパターン形成工程１を示す第４
図ｆａｌ〜（ｄｌと、抵抗体形成工程２を示す第４図ｔ
ｅ１． （ｆｌとを参照して詳しく説明する。Fourth illustrating pattern forming step 1 of the method for manufacturing an intermediate layer substrate
Figures fal~(dl and Figure 4t showing the resistor formation step 2)
e1. (This will be explained in detail with reference to fl.
第４図ｆａ）は、ガラス・エポキシの基材５上に抵抗体
となるニッケル（Ｎｉ）合金６および銅（Ｃｕ）箔７を
メッキする。図（ｂｌは、銅箔７上にパターン形成のた
めのレジスト８を塗布し、焼付け、現像を行う。図（Ｃ
１は、アルカリエツチングを行なって銅箔７のみをエツ
チングし、パターン１２を形成する。In FIG. 4fa), a nickel (Ni) alloy 6 and a copper (Cu) foil 7, which will become a resistor, are plated on a glass epoxy base material 5. Figure (bl) shows that a resist 8 for pattern formation is applied onto the copper foil 7, then baked and developed. Figure (C)
In step 1, alkali etching is performed to etch only the copper foil 7 to form a pattern 12.
図（ｄｌは、エツチング液に硫酸銅（ＣｕＳＯ４）と硫
酸（Ｈ２ＳＯ４）の混合液を用い、Ｎｉ合金６をパター
ン毎にエツチングを行う。In the figure (dl), Ni alloy 6 is etched pattern by pattern using a mixed solution of copper sulfate (CuSO4) and sulfuric acid (H2SO4) as an etching solution.
次に、＋８１図に示すように、レジスト８を図ｆｄｌの
銅箔Ａを分割するように塗布し、アルカリエツチングし
て（ｆｌ図に示すようにＡ１とＡ２パターンを形成する
。このパターンＡ１とＡ２の形成によってＡＩとＡ２の
パターン間にＮｉ合金の抵抗体９が形成される。Next, as shown in Figure +81, resist 8 is applied so as to divide the copper foil A in Figure fdl, and alkali etching is performed (to form patterns A1 and A2 as shown in Figure fl. By forming A2, a Ni alloy resistor 9 is formed between the patterns of AI and A2.
なお、抵抗体９の抵抗値はＡ１とＡ２のパターン間隔ｌ
とＮｉ合金の厚さＷ等によって決まるため、所定の回路
抵抗値に対応してパターン間隔ｌとＮ１合金の厚さＷ等
を決定している。Note that the resistance value of the resistor 9 is determined by the pattern interval l between A1 and A2.
The pattern spacing l and the thickness W of the N1 alloy are determined in accordance with a predetermined circuit resistance value.
次に、上記中間層基板は、積層前処理工程３において、
酢酸銅、酢酸アンモニュウム、硫酸銅およびアンモニヤ
の混合液に浸漬し、露出面に酸化膜１０（斜線にて示す
）を形成し、積層時の密着性をよくする。その後、積層
工程４において多層プリント基板に積層される。Next, the intermediate layer substrate is subjected to a lamination pretreatment step 3.
It is immersed in a mixed solution of copper acetate, ammonium acetate, copper sulfate, and ammonia to form an oxide film 10 (indicated by diagonal lines) on the exposed surface to improve adhesion during lamination. Thereafter, in a lamination step 4, the multilayer printed circuit board is laminated.
上記、プリント基板製造方法において、第４図ｆｆｌの
抵抗体形成後に積層前処理を行うと、処理液によって抵
抗体９のＮｉ合金が浸食され、第４図（幻に示すように
、抵抗体９ＯＮｉ合金部の幅Ｗが薄くなって抵抗値が変
化し、所要の抵抗回路が形成できないという問題がある
。In the above printed circuit board manufacturing method, when the lamination pretreatment is performed after forming the resistor shown in FIG. There is a problem in that the width W of the alloy portion becomes thinner and the resistance value changes, making it impossible to form a required resistance circuit.
本発明はこのような点に鑑みて創作されたもので、中間
層基板の製造工程中に抵抗体の抵抗値に変化が発生する
ことなく、高品質の多層プリント基板が得られる多層プ
リント基板製造方法を提供することを目的としている。The present invention was created in view of the above points, and is a multilayer printed circuit board manufacturing method that allows a high quality multilayer printed circuit board to be obtained without causing any change in the resistance value of the resistor during the manufacturing process of the intermediate layer board. The purpose is to provide a method.
第１図は本発明の多層プリント基板製造方法のブロック
図であり、中間層基板（５）上に抵抗体層（６）および
回路となる層（７）を積層形成し、次に該両層（６，７
）をパターン間隔グして回路パターンを形成し、次に抵
抗部（９）を形成するに先たち酸化処理（３）を施す構
成としている。FIG. 1 is a block diagram of the method for manufacturing a multilayer printed circuit board of the present invention, in which a resistor layer (6) and a layer (7) that will become a circuit are laminated on an intermediate layer board (5), and then both layers are laminated. (6,7
) is arranged at pattern intervals to form a circuit pattern, and then an oxidation treatment (3) is performed before forming a resistor part (9).
積層前処理工程３を抵抗体形成工程２の前に行う構成と
したことによって、従来積層前処理工程３で発生した処
理液による抵抗体への浸食がなくなる。また、積層前処
理を抵抗体形成工程前に行なっても十分な密着性が得ら
れる。By configuring the lamination pretreatment step 3 to be performed before the resistor formation step 2, erosion of the resistor by the treatment liquid that occurred in the conventional lamination pretreatment step 3 is eliminated. Furthermore, sufficient adhesion can be obtained even if the lamination pretreatment is performed before the resistor formation step.
（実施例〕
第２図ｆａｔ〜（ｆｌは本発明の一実施例の製造工程に
おける中間層基板の側断面図を示しており、パターン形
成工程１は第２図（ａｌ〜（ｄｌで示し、抵抗体形成工
程２は第２図ｔｅａ、 ｆｆｌで示している。また、積
層前処理工程３をパターン形成工程ｌの最終工程である
第２図＋ｄ＋の後で行うように構成している。(Example) Figure 2 (fat~(fl) shows a side sectional view of the intermediate layer substrate in the manufacturing process of an embodiment of the present invention, and the pattern forming step 1 is shown in Figure 2 (al~(dl), The resistor forming step 2 is shown in tea and ffl in FIG. 2. Furthermore, the lamination pretreatment step 3 is configured to be performed after the final step of the pattern forming step 1 in FIG. 2 +d+.
第２図ｔａ＋はガラス・エポキシの基材５上にニッケル
（Ｎｉ）合金６と銅（Ｃｕ）箔７をメッキする。回出）
は銅箔７上にパターン形成のためのレジスト８を塗布し
焼付け、現像を行う。図（Ｃ１はアルカリエツチングを
行い銅箔７のみエツチングを行ないパターン１２を形成
する。図ｆｄ＋はエツチング液に硫酸銅（ＣｕＳＯ４）
と硫酸（ｌ１２ｓＯ４）の混合液を用い、旧合金６をパ
ターン毎にエツチングを行う。In FIG. 2 ta+, a nickel (Ni) alloy 6 and a copper (Cu) foil 7 are plated on a glass epoxy base material 5. (output)
A resist 8 for pattern formation is applied onto the copper foil 7, baked, and developed. Figure (C1 shows alkali etching and etching only the copper foil 7 to form a pattern 12. Figure fd+ shows copper sulfate (CuSO4) used in the etching solution.
The old alloy 6 is etched pattern by pattern using a mixed solution of sulfuric acid and sulfuric acid (l12sO4).
次に、上記中間層基板は、積層前処理工程３において、
酢酸銅、酢酸アンモニュウム、硫酸銅およびアンモニヤ
の混合液に浸漬し、第２図（０１に示すように、露出部
分に酸化膜１０（斜線で示す）を形成し、Ｍｉ層時の密
着性をよくする。Next, the intermediate layer substrate is subjected to a lamination pretreatment step 3.
It was immersed in a mixed solution of copper acetate, ammonium acetate, copper sulfate and ammonia to form an oxide film 10 (indicated by diagonal lines) on the exposed part as shown in Figure 2 (01) to improve the adhesion of the Mi layer. do.
次に、図ｔｅ＋に示すように、レジスト８を銅箔Ａを分
割するように塗布し、アルカリエツチングして図（ｆｌ
に示すようにＡ１とＡ２パターンを形成する。このパタ
ーンＡ１とＡ２の形成により、パターンＡ１とＡ２間に
Ｎｉ合金の抵抗体９を形成する。Next, as shown in Figure te+, a resist 8 is applied so as to divide the copper foil A, and alkali etching is performed.
A1 and A2 patterns are formed as shown in FIG. By forming the patterns A1 and A2, a Ni alloy resistor 9 is formed between the patterns A1 and A2.
このように最終工程で抵抗体９を形成することにより、
製造工程途中での抵抗体９への影響をなくしている。By forming the resistor 9 in the final step in this way,
This eliminates any influence on the resistor 9 during the manufacturing process.
以上説明したように本発明によれば、従来発生した製造
工程中での抵抗体の抵抗値の変化がなくなり、高品質の
多層プリント基板が得られる。As explained above, according to the present invention, there is no change in the resistance value of the resistor during the manufacturing process, which conventionally occurs, and a high-quality multilayer printed circuit board can be obtained.
第１図は本発明の多層プリント基板製造方法の工程ブロ
ック図、
第２図は一実施例の製造工程における中間層基板の側断
面図、
第３図は従来の多層プリント基板製造方法のブロック図
、
第４図は従来の製造工程における中間層基板の側断面図
である。
図において、１はパターン形成工程、２は抵抗体形成工
程、３は積層前処理工程、４はせき層工程、５は基材、
６は旧合金、７は銅箔、８はレジスト、９は抵抗体、１
０は酸化膜、１１はパターンを示している。
不看江膚〆７す〉ト基り９恨遣方う炎のエネＥｒロブ７
ｍ第１図
−ｉ＊４列の一乞シＶ４１工ｔＭ＋：ＡＩす豫η１パに
１べｔノＦ、イルミのイリ’ＩＮ［有１υ９第２図
喪主のり７層７・ソ〉ト基破鳴吹遵丁才ｈ）′０ツ７図
第３Ｎ
５ａハ製お飯エネ至＋＝に１士３隼ｎ弓メ１２２々’Ｊ
Ｑ便・１ｒケｄムＧり第４図Fig. 1 is a process block diagram of the multilayer printed circuit board manufacturing method of the present invention, Fig. 2 is a side sectional view of an intermediate layer board in the manufacturing process of one embodiment, and Fig. 3 is a block diagram of the conventional multilayer printed circuit board manufacturing method. , FIG. 4 is a side sectional view of an intermediate layer substrate in a conventional manufacturing process. In the figure, 1 is a pattern forming process, 2 is a resistor forming process, 3 is a lamination pretreatment process, 4 is a weir layer process, 5 is a base material,
6 is old alloy, 7 is copper foil, 8 is resist, 9 is resistor, 1
0 indicates an oxide film, and 11 indicates a pattern. The energy of the flame Er Rob 7
m Fig. 1 - i * 4 rows of beggars V41 tM+: AI Su η 1 pa to 1 bet no F, Illumi's IRI'IN Hameibuki Junchosai h) '0tsu 7 figure 3N 5a ha made rice energy += 1 warrior 3 Hayabusa n bowman 122 'J
Q flight/1r Kem G train Figure 4
Claims (1)
板を形成する方法において、 前記中間層基板（５）上に抵抗体層（６）および回路と
なる層（７）を積層形成し、次に該両層（６、７）をパ
ターンニングして回路パターンを形成し、次に抵抗部（
９）を形成するに先だち酸化処理（３）を施すようにし
たことを特徴とする多層プリント基板の製造方法。[Claims] A method for forming a multilayer printed circuit board by laminating intermediate layer substrates on which resistors are formed, comprising: a resistor layer (6) and a layer (7) forming a circuit on the intermediate layer substrate (5); are laminated, then both layers (6, 7) are patterned to form a circuit pattern, and then a resistive part (6, 7) is formed.
9) A method for manufacturing a multilayer printed circuit board, characterized in that oxidation treatment (3) is performed prior to forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111523A JPH0787272B2 (en) | 1987-05-06 | 1987-05-06 | Method for manufacturing multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111523A JPH0787272B2 (en) | 1987-05-06 | 1987-05-06 | Method for manufacturing multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63275197A true JPS63275197A (en) | 1988-11-11 |
| JPH0787272B2 JPH0787272B2 (en) | 1995-09-20 |
Family
ID=14563488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62111523A Expired - Fee Related JPH0787272B2 (en) | 1987-05-06 | 1987-05-06 | Method for manufacturing multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0787272B2 (en) |
-
1987
- 1987-05-06 JP JP62111523A patent/JPH0787272B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0787272B2 (en) | 1995-09-20 |
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