JPS63273346A - Semiconductor integrated logic circuit - Google Patents

Abstract

PURPOSE:To easily detect the improper connection of a terminating resistor on a high density mounting substrate by connecting a pull-up resistor between the high potential point of a logic output and the emitter terminal of an emitter follower transistor Tr. CONSTITUTION:When a transmission line 300 falls into a non-bias state due to the improper connection of a terminating resistor 400, the potential of the output terminal 501 of a semiconductor integrated circuit 500 becomes a level determined by the resistance ratio of a pull-up resistor 221 to the input resistance of a circuit 550 as observed from the input terminal 551 of a semiconductor integrated circuit 550. That is, since the resistor 221 here is set to a sufficiently smaller resistance value than the input resistance of the circuit 550, the terminal 501 is raised to the vicinity of a ground level. Thus, an emitter follower Tr 212 is cut OFF, and the terminal 501 is secured to a high level irrespective of the signal applied to the input terminal 202. Thus, since the improper connection of the resistor 400 is reflected in the logical operation, this improper connection can be easily detected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated logic circuit using an emitter follower circuit in the output stage, and more specifically, to a semiconductor integrated logic circuit using an emitter follower circuit in the output stage. The present invention relates to a semiconductor integrated logic circuit that allows a connection failure of a termination resistor of the semiconductor integrated logic circuit to be easily detected by a normal logic operation test when a large number of semiconductor integrated logic circuits are installed to form a logic device.

[Conventional technology]

Conventionally, a logic device is constructed by interconnecting semiconductor integrated logic circuits as a unit, using an emitter follower circuit in the output stage, using the emitter terminal of the emitter follower transistor as an external output terminal, and externally attaching a terminating resistor for the load. It is constructed as shown in Figure 2.

In FIG. 2, a semiconductor integrated logic circuit 200 having an emitter terminal of an emitter follower transistor as an external output terminal 201 and another semiconductor integrated logic circuit 250 are mounted on a substrate 100. The terminating resistor 400 of the load is connected to the transmission line 30
A terminal 301, which is connected externally through a terminal 0 and is a connection point between the terminating resistor 400 and the transmission line 300, is connected to an input terminal 251 of a semiconductor integrated logic circuit 250 at the next stage.

When semiconductor integrated logic circuits using emitter follower circuits in the output stage are connected on a substrate in this way, the time constant of the signal transmission path is lowered to reduce the signal propagation delay time, and also to reduce reflection noise and noise. To prevent the occurrence of 1. Usually, as shown in Figure 2.

Terminating resistor 4 with the same resistance value as the impedance of the transmission line
00, the terminal 301 on the receiving end side of the transmission line is connected to the terminal 401 of the emitter follower circuit power supply.

As another example, as shown in FIG. 3, a power supply for the emitter follower circuit is not specially prepared, and a high potential terminal 41 such as the ground is connected to a low potential terminal 421 such as a power supply for an ECL type logic circuit. In some cases, the voltage is divided by two resistors 4] having a parallel resistance value equal to the impedance of the transmission line, 0.420, and the terminal 301 on the receiving end side of the transmission line is connected to the voltage division point.

[Problem that the invention seeks to solve]

By the way, when testing a board equipped with a semiconductor integrated logic circuit that uses an emitter follower circuit in the output stage, failures due to disconnections or short circuits in the transmission line are treated as logic fixed failures and cause logically abnormal operation. However, in the case of a fault in which the transmission line becomes unbiased due to a poor connection of the terminating resistor, the time constant of the transmission path is determined by the input impedance of the semiconductor integrated logic circuit on the receiving end, so the signal Although it is a practical problem because the propagation delay time is generally very large and reflection noise occurs, it works logically, so
There was a problem that it could not be detected by logic operation tests.

In addition, even in the case of the resistor voltage division type termination shown in Figure 3, 2
If either one of the two resistors 410, 420 has a connection failure, the logical operation will be abnormal and it can be detected by a normal logic operation test, but if one of the two resistors 410, 420
If the transmission line 300 becomes non-biased due to a connection failure in both of the transistors 20 and 20, there is a problem in that it cannot be detected by the logical FlX operation test because it logically operates normally.

In resistor voltage division type terminations, two resistors are usually connected at one point on the transmission line to prevent reflected noise, so it is very likely that a connection failure will occur at this point and the transmission line will become unbiased. It will be done.

In this way, connection failures in terminating resistors cannot be detected by logic operation tests, so conventional methods have been to measure the operating speed of the circuit and compare it with the design value, or to directly measure the DC resistance of the signal transmission path on the board. I was testing the connection status of the terminating resistor.

However, in order to measure the operating speed of a single circuit, it is necessary to set logical conditions so that the signal is transmitted from the input terminal of the board through the signal transmission path of the object to be measured to the output terminal. It is not suitable for large-scale logic devices equipped with many integrated logic circuits. Furthermore, as the mounting density on the substrate increases, there has been a problem in that it is becoming difficult to directly measure the DC resistance of the signal transmission path on the substrate.

The present invention has been made to solve the above problems.

It is an object of the present invention to easily detect connection failures of termination resistors on a board when a logic device is configured by mounting a large number of semiconductor integrated logic circuits using emitter follower circuits in the output stage by a normal logic operation test. An object of the present invention is to provide a detectable semiconductor integrated logic circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Among the present inventions made to achieve the above object, a brief outline of typical ones is as follows.

The present invention provides a semiconductor integrated logic circuit in which an emitter follower circuit is used in the output stage, the emitter terminal of the emitter follower transistor is used as an external output terminal, and a load termination resistor is externally connected. A pull-up resistor is provided that connects a potential point higher than the high-level side output potential and the emitter terminal of the emitter follower transistor, and the pull-up resistor is configured such that the emitter follower transistor is in a non-biased state when the load is within an allowable range. The main feature is that the resistance value is such that the potential of the emitter terminal becomes a high-level output potential when

[Effect]

According to the above means, the emitter terminal of the emitter follower transistor in the output stage of the semiconductor integrated logic circuit is connected to a potential point higher than the high-level output potential within the semiconductor integrated logic circuit via the pull-up resistor. This pull-up resistor is sufficiently larger than the resistance value of the external termination resistor.
The resistance value is such that the emitter terminal has an output potential on the high level side when a load within an allowable range is applied to the emitter terminal and the terminating resistor is removed. therefore.

When the termination resistor is correctly connected on the substrate, the output level of the emitter terminal of the emitter follower transistor in the output stage of the semiconductor integrated circuit becomes a high level and a low level correctly according to the logic operation.

In addition, if the emitter terminal falls into a non-biased state due to a poor connection of the terminating resistor, the output level of the emitter terminal is fixed at a high level by the pull-up resistor. It can be detected as a failure by testing the operation.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, semiconductor integrated logic circuits 500 and 550 provided with pull-up resistors according to the present invention are mounted on a substrate 100, and an output terminal 50F of the semiconductor integrated logic circuit 500 and an input terminal 551 of the semiconductor integrated logic circuit 550 are connected. transmission fi3
00 indicates a connected state. Also transmission line 3
A terminating resistor 400 is connected to the terminal 301 on the receiving end side of 00.

In the semiconductor integrated logic circuit 500, the output stage circuit includes a resistor 22.
0. Transistors 210, 211. A normal ECL type Ja logic circuit configured with a current @230, an emitter follower transistor 212. and pull-up resistor 221
It is made up of.

Here, the terminal 202 is an input terminal of the circuit, and the terminal 203 is a reference potential terminal. In addition, in Fig. 1, 205 is EC
This is an LC negative logic circuit source terminal.

Pull-up resistor 2 of semiconductor integrated logic circuit 500 in FIG.
The connection test 21 is performed by directly measuring the DC resistance between the ground terminal 504 and the output terminal 501 during a unit test of the semiconductor integrated logic circuit 500. Also, the resistance value of the pull-up resistor 221 here is equal to the resistance value of the terminating resistor 400.
jb is set to a value that is sufficiently larger than the resistance value of , and sufficiently smaller than the input resistance value of the semiconductor integrated logic circuit 550 viewed from the input terminal 551.

In this state, the output circuit in the semiconductor integrated circuit circuit W8500 performs the same operation as a normal ECL type logic circuit. That is, if a high level signal is applied to the input terminal 202, the output terminal 501 becomes a high level, and if a low level signal is applied to the input terminal 202, the output terminal 501 becomes a low level.

By the way, by the connector "1" of the terminating resistor 400.

When the transmission line 300 falls into an unbiased state, the output terminal 50
The potential of 1 is a level determined by the resistance ratio of the pull-up resistor 221 and the input resistor of the semiconductor integrated logic circuit 55Q viewed from the input terminal 551.

That is, since the pull-up resistor 221 here is set to a sufficiently small resistance value with respect to the input resistance of the semiconductor integrated logic circuit 550, the output terminal 501 is pulled up while approaching the ground level. Therefore, emitter follower transistor 212 is cut off, and output terminal 501 is fixed at a high level regardless of the signal applied to input terminal 202.

Further, since the connection of the pull-up resistor 221 is performed during a unit test of the semiconductor integrated circuit 500, a connection failure of the pull-up resistor 22L and a connection failure of the terminating resistor 400 do not occur at the same time.

In this way, using the semiconductor integrated logic circuit of this example,
Logic devices can be created by mounting multiple semiconductor integrated logic circuits on a board! 1, the connection failure of the terminating resistor is reflected in the logical operation of the circuit, so such failure can be easily detected.

Although the present invention has been specifically explained based on the above embodiments, the present invention is not limited to the above embodiments (although it is of course possible to make various modifications without departing from the gist thereof). .

〔Effect of the invention〕

As described above, according to the present invention, in a substrate mounted with a semiconductor integrated logic circuit using an emitter follower circuit in the output stage, a connection failure of a termination resistor on the substrate is detected by a normal logic operation test. This has the effect that connection failures of termination resistors on large-scale logic boards and high-density mounting boards on which many semiconductor integrated logic circuits are mounted can be detected more easily than in the past.

[Brief explanation of drawings]

Fig. 1 shows a state in which a semiconductor integrated circuit according to an embodiment of the present invention is mounted on a substrate 1 and normal termination is performed, and Fig. 2 shows a state in which a conventional semiconductor integrated logic circuit is mounted on a board. A diagram showing a state in which normal termination has been performed. Figure 3 shows a conventional semiconductor integrated logic circuit mounted on a board.
FIG. 3 is a diagram illustrating a state in which resistance-divided voltage termination is performed. In the figure, 100...J&tentative, 200, 250, 500°550... semiconductor integrated circuit, 201. sat...output terminal, 202...input terminal, 203...reference upper terminal, 504.411...ground terminal, 205+
421...ECL type logic circuit power supply terminal, 210,
211°212-transistor, 2201221140
01410.420...Resistance, 300...Transmission line,
301 - Terminal resistor connection terminal, 251, 551... Input terminal.

Claims (1)

[Claims] 1. In a semiconductor integrated logic circuit in which an emitter follower circuit is used in the output stage, the emitter terminal of the emitter follower transistor is used as an external output terminal, and a load termination resistor is externally attached. A pull-up resistor is provided to connect between a potential point higher than the output potential of the emitter terminal of the emitter-follower transistor and the emitter terminal of the emitter-follower transistor, and the pull-up resistor is connected when the emitter-follower transistor is in a non-biased state in an allowable load state. A semiconductor integrated logic circuit characterized in that the resistance value is such that the potential of the emitter terminal becomes a high-level output potential.