JPS63269677A - Picture processor - Google Patents

Abstract

PURPOSE:To eliminate control for stopping a picture reader so as to suppress the deterioration of picture quality to the minimum, by writing data in a buffer memory in a picture memory and changing auxiliary scanning densities at every time when a counting means counts a prescribed number of lines. CONSTITUTION:A picture memory 26 which stores output picture data, means 21 which counts the number of lines of picture signals inputted from a picture reader, and buffer memory 24 which successively stores picture data of one line inputted from the picture reader, are provided. Then, by writing the data in the buffer memory 24 in the picture memory 26 at every time when the counting means 21 counts a prescribed number of lines, the auxiliary scanning density is changed. Therefore, the picture element density in the auxiliary scanning direction can be changed without controlling the operation of the picture reader. As a result, problems of deterioration of picture quality can be solved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that density-converts image data input from an image reading device in the sub-scanning direction and outputs the resultant image data.

[Prior Art] Currently, the G3 system, which transmits and receives image signals using analog lines such as subscriber telephone lines, is the mainstream for facsimile machines. Furthermore, the G4 system, which transmits and receives image signals via digital lines, is also becoming popular.

G3. The G4 system uses a different encoding method for suppressing redundancy and also has a different standard pixel density. Therefore G
3. When configuring a G4 system dual-purpose machine, or by changing or adding some of the conventional G3 system hardware, the G3. When configuring a G4 system dual-purpose machine, it is necessary to convert the pixel density of the encoding system. Particularly in a facsimile machine having an image reading device and an image recording section, it is uneconomical to provide different reading sections and recording sections depending on the system, so conversion of pixel density is inevitably required.

[Problems to be Solved by the Invention] Figure 3 shows the difference between G3 and G4 in a conventional facsimile machine.
This is the configuration of a conversion circuit used for pixel density conversion to the following method. In Fig. 3, two black and white video signals V are input in synchronization with a video clock Vclk and a horizontal synchronization signal 1 (sync).Here, the video clock Vclk is output for each pixel in the main scanning (horizontal) direction. The horizontal synchronizing signal Hsync is output for each main scanning line, that is, for each sub-scanning.

Here, the bar above the symbol in the figure indicates that the signal is negative logic active. However, this bar will be omitted in the following text.

The horizontal synchronizing signal Hsync is input to a counter 1, and when the counter l counts up the number of horizontal synchronizing signals, that is, the number of lines, by a predetermined number, it outputs a carry CR to the set terminal of the clip prop 2. Counter 1 and flip-flop 2 are video clock Vclk
operates in sync with

The reset terminal of flip-flop 2 receives the horizontal synchronization signal H.
sync is input. The non-inverted output of the flip-flop 2 is input to an AND gate 11, and the inverted output is input to an AND gate 3 that controls the output of the video signal V, and an AND gate that controls the output of a motor-on signal that controls the sub-scanning of the document.
10, and also as a reset signal for counter l and as a write signal for buffer memory 4. A horizontal synchronizing signal Hsync is input to the other input of the computer game 11, and the output of the game system 11 is input to the buffer memory 4 as a read signal.

Further, the output of the buffer memory 4 is controlled by the output of the AND gate 11.

The video signal is output either directly via the AND gate 3 or via either the buffer memory 4 or the AND gate 5. The OR gate 6 outputs the image signal Q or B processed through one of the above paths.

On the other hand, the output of the AND gate 10 is input to the controller 9 of the motor 7 that controls sub-scanning. The output of the controller 9 controls the motor 7 via the inverter 8.

4 and 5 show signal waveforms in the configuration of FIG. 3. As shown in the upper part of FIG. 4, the horizontal synchronizing signal Hsync is output for each scanning line. As shown in the second stage, the video signal V is a horizontal synchronizing signal Hsyn.
One line is output for each c. One pixel data from the image sensor is output in synchronization with the video clock Vclk shown in the lower part of FIG.

Here, the document size is A4, and one line of 218 mm has a pixel density of 18 pel/mm.

Therefore, one line of binarized data is 3456 dots, and the buffer memory 4 stores three of these 3456 dots for one line.
It is assumed that 456-bit data can be written.

In order to perform sub-scanning density conversion during reading with the above configuration, it is sufficient to increase 15.4 lines/m+a (G3) to 15.7 lines/mm (G4). Here, the scanning line density of the reading section corresponds to 15.7 lines/am of G4, which is twice the standard of 7.7 lines/ml11 of G3.

Here, the increase ratio of the sub-scanning density is 101.9%, so
By increasing one line every 50 lines, density conversion from G3 to G4 can be performed.

In the structure shown in FIG. 3, counter 1 counts 50 lines, and when counter 1 outputs a carry, it is sufficient to add one line of data. The data of the line to be added is the data of the previous line stored in the buffer memory 4.

During normal data reading, the flip-flop 2 is not set by the counter l and its inverted output is at a high level, so the AND gate 3 is open and the input video signal V is passed through the AND gate 3 and the OR gate 6 as it is. Output.

On the other hand, FIG. 5 shows the operation when the counter l counts 50 lines and adds one line of data.

Counter l outputs carry CR in synchronization with horizontal synchronization signal Hsync. As a result, the inverted output of the flip-flop 2 becomes low level as shown in the fourth stage of FIG. Further, the output Q' of the AND gate 11 becomes high level in synchronization with the rise of the horizontal synchronizing signal Hsync. The above state is maintained until the horizontal synchronization signal Hsync of the next line falls.

One line of data is written and erased in the buffer memory 4 one after another. This is done by inputting the output of the inverting output terminal of the flip-flop 2 to the write terminal of the buffer memory 4. As shown in FIG. 5, when the output of the analog gate 11 is inverted, the read terminal of the buffer memory 4 becomes high level, and the inverted output of the flip-flop 2 causes the write signal of the buffer memory 4 to become low level.

As a result, the direct output of the video signal Q via the AND gate 3 is stopped, and as shown in the lower part of FIG. Output via . Also, by the inverted output of flip-flop 2, the ant game) 1
0 is closed and the motor-on signal is masked, so the sub-scanning for this line, that is, the conveyance of the document, is stopped for one line.

In the conventional configuration as described above, for an apparatus having only a 03 type reading section, the configuration shown in FIG. 3 must be added, making the configuration complicated. Further, even if the configuration shown in FIG. 3 is installed in advance, it is necessary to control which of G3 and G4 is used for the interface with the image reading section. Further, in the circuit configuration shown in FIG. 3, since the document reading motor is stopped at the time when the l-line video signal is added, there is a problem that the image deteriorates or the reading speed decreases.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, an image processing device that converts the sub-scanning density of an image signal output from an image reading device and outputs the output image data. An image memory for storing image data, a means for counting the number of lines of an image signal inputted from the image reading device, and a buffer memory for sequentially storing the image data of 1 line inputted from the image reading device, A configuration is adopted in which the sub-scanning density is converted by writing data in the buffer memory to the image memory every time a number of lines are counted.

[Operation] According to the above configuration, pixel density conversion in the sub-scanning direction can be performed without controlling the operation of the image reading device.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

FIG. 1 shows the configuration of a pixel density conversion section of an image processing apparatus employing the present invention. The image signal input to the circuit shown in FIG. 1 is output from an image reading section composed of, for example, a CCD line sensor of a G3 facsimile machine. As will be described later, according to the configuration shown in FIG. 1, it is not necessary to modify the image reading device having the pixel density of the 03 method or to provide a circuit to control it, and the density of the input image signal can be converted only by memory operations. can do.

In FIG. 1, reference numeral 20 is an encoder having a desired encoding method such as the MH method, MR, or MMR method.
k, a video signal V and a horizontal synchronization signal Hsync are input. The encoder 20 converts serial image data into parallel 6-bit encoded data. In this embodiment, the 6-bit encoded output of the encoder 20 is input to an image memory 26 that stores output image data. For this reason,
The encoder 20 and the image memory 26 are connected by at least a 6-bit data bus DB and an input/output control signal I/F. Also, encoder 20, image memory 26
Connected between them is a buffer memory 24 that sequentially stores one line of image data for density conversion.

The horizontal synchronization signal Hsync input to the encoder 20 is input to a counter 21 that counts horizontal synchronization signals for 50 lines as in the conventional case, and a delay circuit 22 that delays the input signal by approximately 320 JLS. The counter 21 and the delay circuit 22 operate in synchronization with the video clock Vclk. The flip-flop 23 is reset by the delayed horizontal synchronization signal output from the delay circuit 22. The non-inverted output of the flip-flop 23 is input to the buffer memory 24 as a read signal. Further, the inverted output signal of the flip-flop 23 is inputted as a reset signal of the counter 21.

Input/output operations of the buffer memory 24 and the image memory 26 are controlled according to a clock output from an oscillator 25.

Next, the operation in the above configuration will be explained.

First, the timing of signal processing when performing pixel density conversion from G3 to G4 in this embodiment will be described. When an image reading device (not shown) reads an A4 document, the main scanning synchronization is set to 1.35 m5, and the size of the A4 document is 210×2.
87 mm, and further assume that the image reading device has a standard 03 method line density of 15.4 lines/mm.
(297X 15.4) X 1.35ζ One page of original can be read at a speed of 6.2 seconds. It is also assumed that approximately 320g5 is required for the sub-scanning time.

Therefore, the timing of the horizontal synchronizing signal Hsyr+c is as shown in the top row of FIG. That is, the horizontal synchronization signal H
sync produces a low level of 320 JLs every 1350 JJ, s. In this example, every 50 lines, 32
During the period when the horizontal synchronizing signal of 01Ls is at a low level, one line of data stored in the buffer memory 24 is double stored in the image memory 26, and the scanning density is converted.

In FIG. 2, the counter 21 does not count 50 lines during the period t2, and the carry CR is not output as shown in the third stage. Therefore, data encoded by the encoder 20 is stored in the buffer memory 24 and the image memory 26 at the same time. Buffer memory 24 is flip-flop 2
During a period in which reading is not supported by the non-inverted output of No. 3, input data is stored sequentially from a predetermined address. However, the address of the buffer memory 24 is cleared at the start of accumulation of one line by the horizontal synchronization signal delayed by the horizontal synchronization signal of 320 ps by the delay circuit 22. That is, the write address for the buffer memory 24 is reset to a predetermined initial value.

In FIG. 2, the period t3 indicates reading of 50 lines and 100 lines, and when this reading is completed, the counter 21 outputs a carry CR in synchronization with the fall of the horizontal synchronizing signal Hsync. As a result, the flip-flop 23 is set and the buffer memory 24 is controlled to be in the read state.

At this time, the data of the 50th line accumulated during the period t3 is stored in the buffer memory 24, and by setting the flip-flop 23, the data in the buffer memory 24 is transferred to the image memory 24 as indicated by the symbol T in FIG. will be forwarded to. At this time, the transfer rate between the buffer memory 24 and the image memory 26 controlled by the clock of the oscillator 25 is set to 1.
Assuming 400 ns per byte, approximately 230 g 5-
tsOne line of data can be transferred from the buffer memory 24 to the image memory 26, and one line of data can be transferred sufficiently during the low level period of the horizontal synchronizing signal of 320ILS.

As a result, the data of the 50th line is stored twice in the image memory 26. The count value of the counter 21 is reset by the low level of the inverting output terminal of the flip-flop 23 due to the output of the carry CR.

Since data of one line every 50 lines is double stored in the image memory 26, if this data is inputted to a recording section having a pixel density of the 04 method via a known G4 communication control section, etc. The pixel density in the scan direction can be increased by 2%.

According to the above configuration, there is no need to control the sub-scanning of the image reading unit as in the conventional case, so the configuration shown in Fig. 1 can be simply added without modifying the conventional image reading unit having a pixel density of 0.3 It is possible to perform pixel density conversion from G3 to G4. According to this embodiment, data for one line in the buffer memory is double stored in the output image memory during the synchronization period of the horizontal synchronization signal, so there is no need to stop the reading section, and the image quality is improved. There is no problem of deterioration or reduction in reading speed.

The above configuration adds a circuit to the G3 hardware configuration,
G3. It is very effective when building up to a G4 dual-purpose machine.

Although the pixel density conversion from the 03 system to the 04 system is excited in the above, the pixel density conversion ratio can be freely set by changing the count value of the counter 21. Therefore, the configuration of the present invention is not limited to facsimile machines;
The present invention can be applied to image processing devices that require various types of pixel density conversion.

[Effects of the Invention] As is clear from the above description, according to the present invention, in an image processing device that converts and outputs the sub-scanning density of an image signal output from an image reading device, output image data is stored. An image memory, means for calculating the number of lines of an image signal inputted from the image reading device, and a buffer memory for sequentially storing image data of 1 line inputted from the image reading device are provided, and the counting means has a predetermined number of lines. Since the configuration is such that the sub-scanning density is converted by writing the data in the buffer memory to the image memory every time a line is counted, there is no need to perform control to stop the image reading device, and the memory processing Since it is possible to perform pixel density conversion by
An excellent effect is that pixel density conversion can be performed using an existing image reading unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of the pixel density conversion unit of an image processing device adopting the present invention, FIG. 2 is a timing chart showing the operation of the circuit in FIG. FIGS. 4 and 5 are block diagrams showing the configuration of the density conversion section, and timing charts showing the operation in the conventional configuration shown in FIG. 3. 20...Encoder f 21...Counter 22.
...Delay circuit 23...Flip-flop 24...Buffer memory

Claims (1)

[Claims] In an image processing device that converts the sub-scanning density of an image signal output from an image reading device and outputs the converted image signal, an image memory for storing output image data and means for counting the number of lines of an image signal input from the image reading device are provided. and a buffer memory for sequentially storing one line of image data input from an image reading device, and each time the counting means counts a predetermined number of lines, the data in the buffer memory is written to the image memory. An image processing device characterized by converting sub-scanning density by.