JPH03117171A - Picture processing system and its equipment - Google Patents

Abstract

PURPOSE:To facilitate the thinning processing in the subscanning direction by transferring both address signals at an adjacent main scanning line position to a picture memory, reading a couple of picture element data with at least plural bits or over, applying control while taking OR of the both picture element data and transferring a signal to a shift register applying serial conversion based on a video clock. CONSTITUTION:At first under the control of an MPU 1, a line interval corresponding to a picture reduction rate from the MPU 1 is set to a main register 131, a page head initial address data is inputted to the register 131, a thinning request signal is outputted from a main control section, the MPU 1 and the system bus line are disconnected, the picture transfer operation is transited and the processing operation of A is implemented. As a result, an n-bit picture data in the current main scanning line is stored to an n-bit register 141 and an n-bit picture data on a succeeding relevant main scanning line is stored in other n-bit register 142 respectively and the content of the registers is ORed by an OR circuit 143 to apply interleave control to the picture data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing method used in facsimiles, printers, image scanners, etc. that have an image reduction function. The present invention relates to an image processing method and device for reducing an image in the sub-scanning direction while thinning it out.

``Prior Art'' Conventionally, image data developed in a dot shape in a video memory is once loaded into a line buffer memory one scanning line (or n bits) at a time based on a horizontal synchronizing signal, and then the loaded line Data is serially outputted to the print engine side based on the video clock, and the above operation is repeated every time a horizontal synchronization signal is input, and image data of one page or a predetermined bandwidth is outputted to the print engine side. Image processing methods used in, for example, laser printers and other page printers are well known.

In this type of processing device, there are cases where it is necessary to reduce the pixel density in the sub-scanning direction, either in combination with the main-scanning direction or alone. A method in which the pixel data is expanded and stored in the sub-scanning direction, and then the pixel data is automatically thinned out in units of scanning lines at predetermined intervals S corresponding to the reduction ratio (s-1/S), and the pixel density in the sub-scanning direction is reduced; There is a method in which three or more line memories are prepared in which writing and reading are performed in a cyclic manner, and the pixel density in the sub-scanning direction is reduced while selectively writing and reading from the line memories.
Since both are so-called simple thinning methods that thin out pixel data in units of scanning lines, if there is an isolated pixel line at the thinning position, that pixel line will be erased as is, which will have a negative impact on image reproducibility and readability. A problem arises.

In order to eliminate this drawback, thinning control is performed by calculating the logical sum for each dot at the corresponding main scanning address position between the pixel line existing at the thinning position and the next (previous) pixel line adjacent to the pixel line existing at the thinning position. However, unlike thinning control in the main scanning direction, thinning control is difficult because the address positions between the two dots that are ORed are not consecutive, and even if thinning control is possible. Even in some cases, the circuit configuration becomes complicated and high-speed processing is easily restricted.

For example, using a shift register that can store image data for at least one main scanning line, after discharging one main scanning line's worth of image data from the video memory to the shift register based on a horizontal synchronization signal from the print engine side,
In an image processing device that performs print output while performing serial conversion in synchronization with a video clock, a line buffer capable of storing image data for one main scanning line is prepared separately from the shift register, and thinning processing is performed. In this case, the pixel line existing at the thinning position and the next pixel line adjacent to the pixel line are stored in the shift register and line buffer (hereinafter referred to as both buffers) in advance before data output, and the video clock It is also possible to perform thinning control by outputting data to the print engine side while sequentially ORing each dot from the head position of both buffers when serial output is performed based on the above. In this method, since the dot positions of both buffers have a correspondence with the main scanning address, it is possible to automatically control thinning in the sub-scanning direction by sequentially reading from the top position. However, this method is applicable only to a device using a shift register having a memory capacity (L) for one scanning line; for example, an n-pid shift register in which the above is divided (L: nXm). It cannot be applied to devices using

However, in the above device, in addition to the shift register, a line buffer for one scan must be prepared, and both of the above-mentioned It is necessary to read the memory into the buffer, which complicates the control and cannot support high speed.

In view of the shortcomings of the prior art, the present invention provides an image processing method and an apparatus thereof that can easily perform thinning processing in the sub-scanning direction while performing logical ORing at high speed without complicating the circuit configuration. The purpose is to do.

Another object of the present invention is to provide an image processing method and its device, which is not limited to a device that reads out one scanning line at a time from a video memory, but can be easily applied to a device that reads out n bits at a time. shall be.

"Means for Solving the Problem" The present invention provides image data at a predetermined address position of a main scanning pixel line and an image data at a predetermined address position of the next (previous) pixel line adjacent to the main scanning pixel line. Although the address positions are not consecutive with the data, the address position is simply shifted by one scanning line (L), so the address position can be easily calculated based on the following formula 1. It is.

Bn= An+ L (Bo= Ao±L)...
Bn: n-bit address data in the next (previous) scanning line (Bo: start address data) An:
n-bit address data (A
O: leading address data) That is, as is clear from the basic configuration diagram shown in FIG. an address transfer unit A that transfers the signal and a corresponding address signal in an adjacent main scanning line to an image memory side by arithmetic processing of the address signal, and reads out a pair of pixel data of at least a plurality of bits or more by the address transfer; It consists of a thinning control unit B that performs thinning control while calculating the logical sum of both pixel data, and stores the pixel data after nuclear thinning control in the shift register 140.

The address transfer unit A includes a storage unit 1 that repeatedly stores address signals at main scanning line positions, for example.
31, an address conversion means 134 for processing the address signal to generate a corresponding address signal in an adjacent main scanning line, and converting both address signals based on a thinning request signal generated at each arbitrary main scanning line interval. It consists of a means for continuously transferring the image data to the image memory side, for example, a multiplexer MPX.

In addition, the listening control unit B also has a pair of registers 141 and 142 for temporarily storing the pair of pixel data, and the register 141.
．． 142, and a shift register 140 that synchronizes the pixel data after the thinning control with the video clock and transfers it to the print engine side, for example. .

In this case, by configuring the storage means 131 as a storage means with a counter function in which the stored address signal is updated by n bits each time data is read, the address signal for one scan can be automatically stored. In other words, even when the storage means is configured with an n-bit register, image data for one scanning line can be easily thinned out.

"Effects" Since the present invention can generate corresponding address signals for adjacent main scanning lines through arithmetic processing, it is possible to generate main scanning addresses in units of dots or predetermined bits without using line buffers for -scanning lines. It is possible to read the image data at the corresponding address position in the next (previous) main scanning pixel line whose address position is not continuous with the image data at the position, and as a result, the shift register for the scanning line is The present invention is not limited only to devices using the above, but can also be easily applied to devices using an n-bit shift register in which the main scanning line is divided, and has versatility.

Furthermore, according to the present invention, it is possible to read out a pair of image data for which thinning control is automatically performed simply by continuously transferring both of the address signals to the image memory side, and the image data is not read in units of dots. Since thinning control is possible in units of n bits, extremely high speed can be achieved.

Furthermore, the ability to read out both image data in units of n bits obtained by dividing the main scanning line leads to a corresponding reduction in memory capacity, and the readout and thinning control of the image data is performed in a series of steps based on the thinning request signal. The control circuit does not become complicated because it can be performed as a flow.

It has various effects such as

"Embodiments" Hereinafter, preferred embodiments of the present invention will be described in detail by way of example with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, and relative arrangements of the components described in this example are not intended to limit the scope of this invention, but are merely illustrative examples. It's nothing more than that.

FIG. 2 is an overall block diagram of an image processing device into which the present invention is incorporated. To briefly explain its circuit configuration, l is a block diagram of an image processing device incorporating the present invention. In charge of overall control. MPU,
2 is a video memory having a memory capacity capable of storing image data of a predetermined bandwidth; 3 is a control unit that performs scaling processing of the image data stored in the video memory 2 in the sub-scanning direction and outputs it to the print engine side; It is.

The MPUI and video memory 2 are connected to other R
Address bus S along with OM, Ilo and other devices
It is connected via a system path line SB consisting of a bus, a data bus SBb, and a control bus SBc.
As is well known, a character pattern read out via a font ROM (not shown) under the control of the MPUI or based on a DMA request signal output from another device is sent to a predetermined address in the video memory 2 via the system path line. It is configured so that a dot can be developed at any position.

On the other hand, the control unit 3 is configured to be able to access the MPUI or the video memory 2 via a local path line LB consisting of a local address bus LBa, a local data bus LBb, and a local control bus LBc branched from the system path line SB. For example,
When the control unit 3 reads the reduction rate (s-1/s) from the MPUI side, the control unit 3 side receives an address signal output from the MPUI under the control of the MPUI, for example, via an address decoder. Data can be sent and received via the system data bus. On the other hand, when the control unit 3 accesses the video memory 2, the control unit 3 first outputs a DMA request signal to the MPUI side. At the same time as disconnecting the system path line SB, the control unit 3 becomes the bus master, and as a result, the control unit 3
is connected to video memory 2 via local address bus LBa.
By outputting an address signal to the controller 3, it is possible to transfer image data at a designated address to the control unit 3 side.

Next, the detailed configuration of the control section 3 that performs image data enlargement or reduction processing will be explained based on FIG. 3.

In this embodiment, the main scanning pixel line L in the video memory 2 is divided and transferred n bits at a time (L:nX1) in order to reduce the memory capacity of the shift register and the like in the control unit 3. However, it goes without saying that the present invention is not limited to this, but can also be applied to an apparatus that transfers one scanning line at a time.

The configuration of the control unit 3 is, for example, the above-mentioned DMA.
A main control unit 11 consisting of an LSI, which receives the output of a request signal or various control signals from the MPUI side, etc. and controls various control operations to be described later, calculates the desired reduction rate (s -
17s) or a line spacing s corresponding to the enlargement rate (t+17t), a signal generation unit 12 that outputs a thinning or duplication request signal of main scanning pixel lines to the main control unit 11 every time; An address generation unit 13 generates an address signal for image data to be read out from the video memory 2 based on a control signal from the video memory 2, and outputs a video to the print engine side while serially converting the image data read out based on the address signal. Each of these blocks will be explained in detail.

The signal generation unit 12 has a register 121 that temporarily stores the line spacing values s and t corresponding to the image reduction rate or enlargement rate output from the MPUI side, and a register 121 that temporarily stores the line spacing values s and t that are read from the register 121 and horizontally stores the line spacing values s and t that are output from the MPUI side. It consists of a counter 122 that counts down each time a synchronization signal is input, and when the count value reaches 0, it outputs an image line duplication request signal to the main control unit 11 side, and also outputs an image line duplication request signal to the register 121 each time the signal is output. The stored interval values s and t are loaded into the counter 122, and the above operation is repeated thereafter.

Note that the interval values s and t are not the same, and the interval values s and t are not the same.
- A plurality of interval values s l and s 2 may be set and alternately loaded to the counter 122 side.

The address generation unit 13 includes a main register 131 having a counter function, a save register 133 that saves and stores the start address data of the main scanning line currently being scanned.
a first address converter 132 that converts the first address data stored in the save register 133 into the first address data of the next main scanning line by performing arithmetic processing based on the first equation below; A second process is used for reduction processing, and converts the address data stored in the main register 131 into corresponding address data in the next main scanning line by performing arithmetic processing based on the first equation below. address converter 134 and main control unit 1
Based on the control signal from 1, the local data bus LB
MPX+ and MPX2 (multiplexers) that select the start address data output from the MPUI via b and the address data stored in the first address converter 132 or the save register 133;
It consists of an MPX 3 that selectively transfers the address data stored in the main register 131 and the second address converter 134 to the image memory side, and the address data output from the MPX 3 specifies the designation in the video memory 2. It becomes possible to transfer the n-bit image data at the address position to the serial converter 14 side via the data bus LBb.

The serial converter 14 includes a pair of n-bit registers 141
．． 142 and an OR circuit 143 that logically ORs the contents of the image register and transfers the result to the n-bit shift register 140 side.
The shift register 1
The image data after enlargement or reduction processing transferred n bits at a time to 40 can be serially outputted to the print engine side in synchronization with the video clock.

Next, the operation of this embodiment will be explained separately for the case of performing enlargement processing and the case of performing reduction processing.

First, the enlargement processing method will be explained.

First, under the control of the MP old, the line spacing value t corresponding to the image enlargement rate is sent to the register 121 from the liver side via the data bus LBb, and the initial address of the top of the page is sent to the main register 131 via MPXI and MPX2. Input data AO.

After the above settings are completed, the main control section 11 outputs a DMA request signal and disconnects the MPUI from the system path line SB, so that the control section 3 becomes the bus master, thereby shifting to the image transfer operation described later.

That is, the horizontal synchronization signal is sent from the print engine to the control unit 3.
When output to the side, the value in the counter 122 becomes (5-1)
At the same time, based on the control signal from the main control unit 11 side, the initial address stored in the main register 131 is saved in the MPX along with the save register 133.
3 to the video memory 2 side.

Then, by transferring the initial address data AO, the corresponding n-bit image data is transferred from the video memory 2 to the n-bit register 141, and the initial address data stored in the main register 131 is counted up bit by bit. Ru.

7- Then, the n-bit image data transferred to the register is transferred to the shift register 140 via the OR circuit 143, and then serially outputted to the print engine side based on the control signal from the main control unit 11, and The uploaded address data An is transmitted to the video memory 2 side, and the image data corresponding to the address is stored in the n-bit register 141 after the transfer.

Below - The above operation is repeated until the image data for the main scanning line is output to the print engine side, but since the horizontal synchronization signal is not output during this time, the start address data in the save register 133 is updated. There is no.

When a horizontal synchronizing signal is output from the print engine side after outputting data for one main scanning line, MPX 1 is switched and the next leading address data stored in the first address converter 132 is output. The data is loaded into the main register 131, and the above operation is repeated thereafter. (This operation is called A processing because it is performed in the same way when performing reduction processing.) 8 Then, after the image data for t-1 scan lines is output to the print engine side, the horizontal synchronization signal is output for the 1st time. When it is output, the count value of the counter 122 underflows and an enlargement request signal is output to the main control section 11 side.
By closing MPX1 and switching MPX2, the start address data SO in the current scanning line stored in the save register 133 is loaded into the main register 131.

As a result, the address data is transferred to the video memory 2 side, and the image data for S scanning lines is transferred again to the n-bit registers 141, 142 side, and the main scanning image data lines are overlapped and transferred to the print engine side. The image will be output, and the image will be enlarged.

Thereafter, by repeating the above operations, image processing corresponding to the desired enlargement magnification becomes possible.

Next, a reduction processing method will be explained.

First, under the control of the MPUI, the MPUI side inputs the line spacing value S corresponding to the image reduction rate into the register 121 and the initial address data AO of the top of the page into the main register 131, and then the main controller 11 inputs the DMA A request signal is output, the old MP and the system path line are separated, the image transfer operation is started, and the processing operation A is performed.

Then, when the count value of the counter 122 underflows due to the S-th horizontal synchronization signal after the image data for S-1 scan lines is output to the print engine side based on the processing operation of A, the main A reduction request signal is issued to the control unit 11 side, which starts the arithmetic processing of the second address converter 134, and the data in the current main scanning line is stored in the main register 131 and the address is sequentially updated by n bits. The address data and the corresponding address data in the next main scanning line, which has been arithmetic-processed by the second address converter 134 based on the address data, are selectively transferred to the image memory side via the MPX 3.

As a result, n-bit image data for the current main scanning line is stored in the - n-bit register 141, and n-bit image data for the corresponding next main scanning line is stored in the other n-bit registers 142. Then, by logically ORing the contents of both registers by the OR circuit 143, the image data is thinned out by n bits at a time, and the image data after the nucleus thinning control is transferred to the n-bit shift register 140 side. By repeating the above operation for each serial output while serially outputting it to the print engine in synchronization with the video clock, thinning control for 1 scan of 542 minutes is performed smoothly, and a predetermined image reduction process is performed. It happens.

By repeating the above operations, image processing corresponding to the desired reduction magnification becomes possible.

[Brief explanation of drawings]

Fig. 1 is a basic configuration diagram of the present invention, Fig. 2 is an overall block diagram showing an image processing device according to an embodiment of the present invention used in a laser printer, and Fig. 3 is a thinning control section which is the main part of the present invention. It is a detailed block diagram showing the. 1-

Claims (1)

[Claims] 1) A thinning request that is generated at every arbitrary main scanning line interval after processing the address signal at the corresponding main scanning line position to generate a corresponding address signal in the adjacent main scanning line. Based on the signal, both address signals at the adjacent main scanning line positions are transferred to the image memory side, a pair of pixel data of at least a plurality of bits or more is read out, and thinning control is performed while calculating the logical sum of the two pixel data. , an image processing method characterized in that data is transferred to a shift register that performs serial conversion based on a video clock 2) Based on a thinning request signal generated at each arbitrary main scanning line interval, the corresponding main scanning line position is determined. an address transfer unit that transfers an address signal in the image memory side and a corresponding address signal in an adjacent main scanning line after arithmetic processing of the address signal; and a pair of pixel data of at least a plurality of bits or more is read out by the address transfer. , a thinning control unit that performs thinning control while calculating the logical sum of both pixel data, and stores the pixel data after the thinning control in a shift register, and controls the pixel data stored in the shift register based on the video clock. Image processing device characterized by being configured to be capable of serial output 3) The generation unit of the "address signal at the corresponding main scanning line position" is a counter whose address is updated by predetermined bits of the stored address signal every time data is read. The image processing device according to claim 2), which is a functional storage means.