JPS6326923Y2 - - Google Patents
Info
- Publication number
- JPS6326923Y2 JPS6326923Y2 JP17436779U JP17436779U JPS6326923Y2 JP S6326923 Y2 JPS6326923 Y2 JP S6326923Y2 JP 17436779 U JP17436779 U JP 17436779U JP 17436779 U JP17436779 U JP 17436779U JP S6326923 Y2 JPS6326923 Y2 JP S6326923Y2
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- light
- display panel
- cathode ray
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims description 3
- 230000006386 memory function Effects 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003446 memory effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
【考案の詳細な説明】
本考案は陰極線表示パネルにおける各発光点の
字欠け現象を解消する陰極線表示パネルに関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cathode ray display panel that eliminates the phenomenon of missing characters at each light emitting point in the cathode ray display panel.
一般に陰極線表示パネルはプレート電極上に蛍
光体を塗布し、この蛍光体を低速電子線によつて
励起発光させると共に、スイツチング素子をコン
トロールすることによつて、その発光強度を変化
させ、そして、比較的少ないリフレツシユ回数で
もちらつきが感じられないように、メモリ機能を
もたせたメモリ機能付発光エレメントをＭ行Ｎ列
のマトリツクス状に配置するものである。 Generally, in a cathode ray display panel, a phosphor is coated on a plate electrode, and the phosphor is excited by a slow electron beam to emit light, and the intensity of the emitted light is changed by controlling a switching element. Light-emitting elements with a memory function are arranged in a matrix of M rows and N columns so that no flicker is perceived even with a small number of refreshes.
第１図は従来の１個の発光エレメントが発光す
る場合の回路図である。同図において、１は走査
信号が入力するＸ軸方向駆動線に接続する走査入
力端子、２は映像信号が入力するＹ軸方向駆動線
に接続する映像入力端子、３はゲート３ａが走査
入力端子１に接続し、ドレイン３ｂが映像入力端
子２に接続し、ソース３ｃが接続点４に接続する
第１スイツチング素子、５はこの接続点４とアー
スとの間に接続するメモリ用コンデンサ、６はプ
レート電極、７はこのプレート電極６上に塗布し
た蛍光体、８は電源電圧Vbの電源、９はゲート
９ａが接続点４に接続し、ドレイン９ｂがプレー
ト電極６に接続し、ソース９ｃがアースに接続す
る第２スイツチング素子、１０は電源８に接続す
るカソード電極、１１は端子電圧Vgの電源、１
２はこの電源１１に接続するグリツド電極であ
る。 FIG. 1 is a conventional circuit diagram when one light emitting element emits light. In the figure, 1 is a scanning input terminal connected to an X-axis direction drive line to which a scanning signal is input, 2 is a video input terminal connected to a Y-axis direction drive line to which a video signal is input, and 3 is a gate 3a is a scanning input terminal. 1, a drain 3b is connected to the video input terminal 2, and a source 3c is connected to the connection point 4; 5 is a memory capacitor connected between this connection point 4 and the ground; 6 is a memory capacitor connected to the connection point 4; A plate electrode, 7 is a phosphor coated on this plate electrode 6, 8 is a power source with a power supply voltage V b , 9 is a gate 9a connected to the connection point 4, a drain 9b connected to the plate electrode 6, and a source 9c a second switching element connected to ground; 10 a cathode electrode connected to a power source 8; 11 a power source with terminal voltage V g ;
2 is a grid electrode connected to this power source 11.
次に、上記構成に係る陰極線表示パネルの動作
について簡単に説明する。まず、映像入力端子２
に“１”信号が入力し、走査入力端子１に、例え
ば60μsecのパルス幅で60Hzの信号が入力したと
き、第１スイツチング素子３がオン状態になる。
このため、メモリ用コンデンサ５は充電される。
一方第１スイツチング素子３のオンにより、第２
スイツチング素子９がオン状態となる。このた
め、発光エレメントが発光する。そしてメモリ用
コンデンサ５の放電により、第２スイツチング素
子９は60μsec以外の所定時間だけオン状態を維持
するため、発光エレメントの発光はちらつきを感
じさせず、明るく発光する（メモリー効果の為）
ようにしている。 Next, the operation of the cathode ray display panel having the above configuration will be briefly described. First, video input terminal 2
When a "1" signal is input to the scanning input terminal 1 and a 60 Hz signal with a pulse width of 60 μsec, for example, is input to the scanning input terminal 1, the first switching element 3 is turned on.
Therefore, the memory capacitor 5 is charged.
On the other hand, by turning on the first switching element 3, the second
Switching element 9 is turned on. Therefore, the light emitting element emits light. As the memory capacitor 5 is discharged, the second switching element 9 remains on for a predetermined period of time other than 60 μsec, so the light emitting element emits bright light without flickering (due to the memory effect).
That's what I do.
上記構成の発光エレメントをＰチヤネル
MOSFET上にＭ行Ｎ列のマトリツクス状に配置
して陰極線表示パネルを作成することができる。
一方、ｎチヤネルMOSFET上にＭ行Ｎ列の発光
エレメントを配置して陰極線表示パネルを構成す
る場合、１個の発光エレメントの回路を第２図に
示すことができる。同図において、第２スイツチ
ング素子９のソース９ｃは正の電源１３に接続
し、カソード電極１０はアースに接続する。な
お、発光エレメントの発光動作については第１図
と同様であることはもちろんであるが、基板（サ
ブストレート）がほぼカソード電位となる。この
ため、第３図に示すように、選択されたＸ軸方向
駆動線１４ａおよびＹ軸方向駆動線１５ａによつ
て発光した発光エレメント１６は他の選択されな
いＸ軸方向駆動線１４ｂおよびＹ軸方向駆動線１
５ｂによつて囲まれているため、この発光エレメ
ント１６は斜線で示すように発光するが、一部１
６ａでは発光せず、暗くなる、いわゆる字欠け現
象が生ずる。この字欠け現象は基板（サブストレ
ート）をある電圧にバイアスすることによつて解
消することができるが、第２図に示すように、発
光エレメントをｎチヤネルMOSFET上に構成す
る場合には第１スイツチング素子３も同時に基板
バイアスされ、第２スイツチング素子９のゲート
電極９ａには常に基板電圧が印加する。このた
め、第２スイツチング素子９のソース電極９ｃの
電位によつて、各発光エレメントの字欠け現象の
程度にバラツキが生ずる欠点があつた。 The light emitting element with the above configuration is used as a P channel.
A cathode ray display panel can be created by arranging them in a matrix of M rows and N columns on a MOSFET.
On the other hand, when a cathode ray display panel is constructed by arranging M rows and N columns of light emitting elements on an n-channel MOSFET, the circuit of one light emitting element can be shown in FIG. In the figure, the source 9c of the second switching element 9 is connected to a positive power source 13, and the cathode electrode 10 is connected to ground. Note that the light emitting operation of the light emitting element is of course the same as that shown in FIG. 1, but the substrate is approximately at cathode potential. Therefore, as shown in FIG. 3, the light emitting element 16 emitted by the selected X-axis direction drive line 14a and the Y-axis direction drive line 15a is used for the other unselected X-axis direction drive line 14b and the Y-axis direction. Drive line 1
5b, this light emitting element 16 emits light as shown by diagonal lines, but a part of it
6a does not emit light and becomes dark, a so-called missing character phenomenon occurs. This character missing phenomenon can be eliminated by biasing the substrate to a certain voltage, but as shown in Figure 2, when the light emitting element is configured on an n-channel MOSFET, the first The switching element 3 is also subjected to a substrate bias at the same time, and a substrate voltage is always applied to the gate electrode 9a of the second switching element 9. For this reason, there is a drawback that the degree of the missing character phenomenon of each light emitting element varies depending on the potential of the source electrode 9c of the second switching element 9.
したがつて、本考案の目的はｎチヤネル
MOSFETを用いたメモリ機能付発光エレメント
における字欠け現象を簡単な構成によつて解消す
ることができる陰極線表示パネルを提供するもの
である。 Therefore, the purpose of this invention is to
The object of the present invention is to provide a cathode ray display panel that can eliminate the character missing phenomenon in a light emitting element with a memory function using a MOSFET with a simple configuration.
このような目的を達成するため、本考案は発光
エレメントの字欠け現象部分に隣接して、常時正
電圧が印加する電源ラインを配置するものであ
り、以下実施例を用いて詳細に説明する。 In order to achieve this object, the present invention disposes a power line to which a positive voltage is always applied adjacent to the part of the light emitting element where the character is missing, and will be described in detail below using examples.
第４図は本考案に係る陰極線表示パネルの一実
施例を示す一部詳細な構成図であり、そのＡ−
A′断面を第５図に示し、そのＢ−B′断面を第６
図に示す。第４図において、１７は発光エレメン
ト１６の右側および下側、すなわち字欠け現象部
分１６ａに接近するように配置し、常に正電位
（例えば30V）が印加する電源ライン、１８は２
点鎖線の枠で示す第１スイツチング素子３の第
1FET、１９は２点鎖線の枠で示す第２スイツチ
ング素子９の第2FET、２０は１点鎖線の枠で示
すメモリ用コンデンサ５を構成する構成電極、２
１ａ，２１ｂおよび２１ｃは×印で示すスルーホ
ール部、２２はバリツドコンタクトである。 FIG. 4 is a partially detailed configuration diagram showing one embodiment of the cathode ray display panel according to the present invention, and its A-
The A' cross section is shown in Figure 5, and the B-B' cross section is shown in Figure 6.
As shown in the figure. In FIG. 4, reference numeral 17 is a power line that is arranged to be close to the right side and lower side of the light-emitting element 16, that is, the missing character part 16a, and to which a positive potential (for example, 30 V) is always applied;
The first switching element 3 indicated by the dotted chain line frame
1FET, 19 is the second FET of the second switching element 9, which is indicated by a frame with two-dot chain lines; 20 is a component electrode that constitutes the memory capacitor 5, which is indicated by a frame with one-dot chain lines;
1a, 21b and 21c are through-hole portions indicated by x marks, and 22 is a bullet contact.
なお、プレート電極６は実線の枠で示し、蛍光
体７は点線の枠で示す。また、第５図および第６
図において、２３は絶縁層、２４は裏面電極であ
る。 Note that the plate electrode 6 is shown in a solid line frame, and the phosphor 7 is shown in a dotted line frame. Also, Figures 5 and 6
In the figure, 23 is an insulating layer, and 24 is a back electrode.
次に、上記構成に係る陰極線表示パネルの発光
エレメントの字欠け現象を解消する動作について
説明する。 Next, an operation for eliminating the missing character phenomenon in the light emitting elements of the cathode ray display panel according to the above configuration will be described.
まず、発光エレメント１６を発光させるために
はＸ軸方向駆動線１４ａおよびＹ軸方向駆動線１
５ａに正電位を印加すると、前記したように、第
１スイツチング素子３の第1FET１８がオン状態
になり、メモリ用コンデンサ５は充電される。一
方、この第１スイツチング素子３の第1FET１８
がオン状態になると、第２スイツチング素子９の
第2FET１９もオン状態になる。このため、発光
エレメント１６が発光する。このとき、発光エレ
メント１６の右側および下側の字欠け現象部分１
６ａに隣接して、正電圧が印加する電源ライン１
７が配置されているため、この字欠け現象部分１
６ａは正常に発光し、字欠け現象を解消すること
ができる。 First, in order to cause the light emitting element 16 to emit light, the X-axis direction drive line 14a and the Y-axis direction drive line 1 are
When a positive potential is applied to 5a, the first FET 18 of the first switching element 3 is turned on, as described above, and the memory capacitor 5 is charged. On the other hand, the first FET 18 of this first switching element 3
When FET 19 of the second switching element 9 is turned on, the second FET 19 of the second switching element 9 is also turned on. Therefore, the light emitting element 16 emits light. At this time, the missing character portion 1 on the right side and lower side of the light emitting element 16
Adjacent to 6a, a power supply line 1 to which a positive voltage is applied
Because 7 is placed, this character missing phenomenon part 1
6a emits light normally and can eliminate the missing character phenomenon.
以上、詳細に説明したように、本考案に係る陰
極線表示パネルによれば電源ラインの形状を変え
るのみであるから、電源ラインを配置する工程を
変えることなく、簡単に字欠け現象を解消するこ
とができる効果がある。 As explained above in detail, according to the cathode ray display panel according to the present invention, only the shape of the power supply line is changed, so the missing character phenomenon can be easily solved without changing the process of arranging the power supply line. It has the effect of
第１図は従来の１個の発光エレメントを発光す
る場合の回路図、第２図は従来のｎチヤネル
MOSFET上に発光エレメントを構成する場合の
回路図、第３図は第２図における字欠け現象を説
明するための図、第４図は本考案に係る陰極線表
示パネルの一実施例を示す一部詳細な構成図、第
５図は第４図のＡ−A′断面図、第６図は第４図
のＢ−B′断面図である。
１……走査入力端子、２……映像入力端子、３
……第１スイツチング素子、３ａ……ゲート、３
ｂ……ドレイン、３ｃ……ソース、４……接続
点、５……メモリ用コンデンサ、６……プレート
電極、７……蛍光灯、８……電源、９……第２ス
イツチング素子、９ａ……ゲート、９ｂ……ドレ
イン、９ｃ……ソース、１０……カソード電極、
１１……電源、１２……グリツド電極、１３……
正の電源、１４ａおよび１４ｂ……Ｘ軸方向駆動
線、１５ａおよび１５ｂ……Ｙ軸方向駆動線、１
６……発光エレメント、１６ａ……字欠け現象部
分、１７……電源ライン、１８……第1FET、１
９……第2FET、２０……構成電極、２１ａ〜２
１ｃ……スルーホール部、２２……バリツドコン
タクト、２３……絶縁層、２４……裏面電極。
Figure 1 is a conventional circuit diagram for emitting light from one light emitting element, and Figure 2 is a conventional circuit diagram for the case of emitting light from one light emitting element.
A circuit diagram when a light-emitting element is configured on a MOSFET, FIG. 3 is a diagram for explaining the missing character phenomenon in FIG. 2, and FIG. 4 is a part showing an embodiment of a cathode ray display panel according to the present invention. 5 is a sectional view taken along the line AA' in FIG. 4, and FIG. 6 is a sectional view taken along the line BB' in FIG. 4. 1...Scanning input terminal, 2...Video input terminal, 3
...First switching element, 3a...Gate, 3
b...Drain, 3c...Source, 4...Connection point, 5...Memory capacitor, 6...Plate electrode, 7...Fluorescent lamp, 8...Power source, 9...Second switching element, 9a... ...gate, 9b...drain, 9c...source, 10...cathode electrode,
11...Power supply, 12...Grid electrode, 13...
Positive power supply, 14a and 14b...X-axis direction drive line, 15a and 15b...Y-axis direction drive line, 1
6...Light emitting element, 16a... Character missing phenomenon part, 17... Power line, 18... 1st FET, 1
9...Second FET, 20...Constituent electrode, 21a-2
1c...Through-hole portion, 22...Barrier contact, 23...Insulating layer, 24...Back electrode.
Claims (1)
体を低速電子線によつて励起させ、この発光強
度をスイツチング素子によつてコントロールす
ると共に、その発光を持続させるためのメモリ
機能をもつ発光エレメントを、ｎチヤネル
MOSFETを構成するシリコン基板上にＭ行Ｎ
列のマトリツクス状に配置し、これらの発光エ
レメントを行方向に配置したＸ軸方向駆動線お
よび列方向に配置したＹ軸方向駆動線とによつ
て選択的に発光させる陰極線表示パネルにおい
て、前記発光エレメントに接続されていない隣
接する発光エレメント用のＸ軸方向駆動線およ
びＹ軸方向駆動線と発光エレメントとの間に常
時正電圧が印加する電源ラインを配置してなる
陰極線表示パネル。 (2) 電源ラインの発光エレメントに隣接する部分
では、行方向、あるいは列方向に突出させ、発
光エレメントの２辺に隣接するようにしたこと
を特徴とする実用新案登録請求の範囲第１項記
載の陰極線表示パネル。[Claims for Utility Model Registration] (1) A phosphor is coated on a plate electrode, the phosphor is excited by a slow electron beam, the intensity of this emission is controlled by a switching element, and the emission is controlled by a switching element. N-channel light-emitting elements with memory function to last
M rows and N on the silicon substrate that constitutes the MOSFET.
In a cathode ray display panel, the light emitting elements are arranged in a matrix of columns and selectively emit light by means of X-axis drive lines arranged in the row direction and Y-axis drive lines arranged in the column direction. A cathode ray display panel in which a power supply line to which a positive voltage is constantly applied is arranged between the light emitting elements and the X-axis direction drive lines and Y-axis direction drive lines for adjacent light-emitting elements that are not connected to the elements. (2) Claim 1 of the utility model registration characterized in that the portion of the power supply line adjacent to the light emitting element is made to protrude in the row direction or column direction so as to be adjacent to two sides of the light emitting element. cathode ray display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17436779U JPS6326923Y2 (en) | 1979-12-18 | 1979-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17436779U JPS6326923Y2 (en) | 1979-12-18 | 1979-12-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5692189U JPS5692189U (en) | 1981-07-22 |
| JPS6326923Y2 true JPS6326923Y2 (en) | 1988-07-21 |
Family
ID=29685106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17436779U Expired JPS6326923Y2 (en) | 1979-12-18 | 1979-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6326923Y2 (en) |
-
1979
- 1979-12-18 JP JP17436779U patent/JPS6326923Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5692189U (en) | 1981-07-22 |
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