JPS6326909B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a character processing device capable of editing a document input to a device.

[Prior art]

Conventional English character processing device (word processor)
When editing a document, it had a function to transfer words, sentences, or paragraphs to other parts of the document, but there is also a function to transfer a string of arbitrary length in a paragraph or a single sentence. It did not have the ability to transfer character strings of arbitrary length. In particular, when considering Japanese word processors, this drawback is that in Japanese sentences, the words are not separated by spaces like in English sentences, so the word breaks are unclear, and English word processors It was not suitable to equip a Japanese word processor with the transfer structure of .

There was also plenty of room for improvement in terms of operability and high speed.

[Object] In view of the above points, an object of the present invention is to be able to specify a desired character string by specifying the beginning and end, and further to store the specified character string. It is an object of the present invention to provide a character processing device capable of quickly inserting a specified character string each time insertion is instructed to a desired insertion location in a document.

An object of the present invention is to be able to specify a character string in a document being created, and to insert the desired character string each time an instruction to insert it into a desired position in the document is made. To provide a highly operable character processing device that can be created while duplicating a desired character string in the document.

[Example] An embodiment according to the present invention will be described below.

[Block diagram]

FIG. 1 is a block diagram of a character processing device according to the present invention. In the figure, the CPU is a microprocessor that performs calculations, logical judgments, etc. AB is an address bus that transfers signals indicating the control target. DB is a data bus that transfers various data and is a bidirectional bus. CB is a control bus that applies control signals to various control targets.

KB is a keyboard with keys KB1 for inputting characters, functions, and modes, space key KB2 for inputting spaces, movement range key KB3 for moving input sentences, and movement destination for inserting sentences to be moved. It has key KB4 etc.

KBC is a keyboard controller that encodes data input from the keyboard KB and also sends interrupt signals to the control bus CB. DPC is a CRT controller, CRT device DP,
It controls the character generator CG, the refresh memory M, and the refresh memory controller MC3. The CRT device DP is capable of displaying characters, symbols, strokes, etc. character generator
The CG outputs a desired character symbol pattern by inputting codes such as a character code symbol code and a line address of the character symbol pattern. The character and symbol patterns are formed in a matrix, and by changing the row addresses, the character and symbol patterns are output. The refresh memory M stores the character symbol code displayed on the CRT device DP, and repeatedly outputs the character symbol code under the control of the CRT controller DPC.
The refresh memory controller MC3 controls the refresh cycle of the refresh memory M and the writing and reading of data from the microprocessor CPU in accordance with instructions from the CRT controller DPC. The ROM is a control memory that stores various processing procedures, control procedures shown in FIGS. 4 to 20, Kanji information, etc.

The control memory ROM above is the ROM controller MC
1, the stored processing procedure is read out.
RAM is a random access memory used for temporary storage of various data.

[RAM explanation]

Figure 2 further explains the main parts of the memory RAM, where MRSR is the moving range status register, SAR is the moving range start address register,
EAR is the movement range end address register, MB is the movement buffer, IDB is the input data buffer,
UB is an unused buffer, P1 to P4 are parameter registers, CR is a cursor register, N is a register, FDRP is a first data record pointer,
LDRP has a last data record pointer, FBRP has a first unused record pointer, LBRP has a last unused record pointer, FTBRP has a record pointer for moving to the beginning, LTBRP has a record pointer for moving to the end, etc., and it also has the register group shown in the figure. .

[Batsuhua composition]

The block moving buffer MB that stores the text to be moved has the structure shown in Figure 3, and the input data buffer IDB that stores the input data has the same structure. Batsuhua UB has a similar structure. The moving buffer MB, input data buffer IDB, and unused buffer UB are each made up of one or more records shown in FIG. 3, and are increased or decreased as necessary as described below.

B1 is a memory location that stores the start address of the record that precedes this record.
B2 is a memory location that stores the start address of the record that follows this record.
3 is a memory location that stores the length of valid data contained in this record. The data stored in the record is up to 28 words and is filled in sequentially starting from memory location B4. This is usually called a list structure.

The connection of a plurality of records is as described above, and the addresses of the first record that precedes a certain record and the last record that follows a certain record are indicated by various pointers.
That is, in this case, the first record of the moving buffer MB is stored in the pointer FTBRP, and the last record is stored in the pointer LTBRP. Similarly, the first data record pointer of the input data buffer IDB is stored in a pointer FDRP, the last data record pointer thereof is stored in a pointer LDRP, and the records of the unused buffer UB are stored in a pointer FBRP and a pointer LBRP, respectively.

The memory RAM is written and read by the RAM controller MC2. Shown in Figure 1
MD is a magnetic disk device that stores kanji information in the format described below. The magnetic disk device MD is controlled by a magnetic disk controller MDD.

P is a printer that records information such as kanji information, katakana, hiragana, etc., and is controlled by a printer controller PD.

[Control explanation]

The operation of the embodiment constructed as described above will now be described in detail.

This character processing device is activated by operating the keyboard KB. When the keyboard KB is operated, an interrupt signal generated by the keyboard KB is transmitted to the microprocessor CPU, which calls the control procedure in the control memory ROM via the microprocessor CPU.
Each control is performed according to the control procedure.

In this way, the object of the invention is achieved by the control procedure stored in the first illustrated memory ROM. When various inputs are made from the keyboard KB, an interrupt occurs and the ROM is
Control is transferred to the program area stored in ROM. This control program is shown in the flowchart shown in FIG. 4 and below, and will be explained in order below.

[Block transfer function explanation diagram]

In the flowchart of FIG. 4, in order to make the block transfer function of the present invention particularly clear, various processing routines in the word processor are omitted and only shown as various word processor processing routines 20. When moving blocks, first use CRT, which is one of the processing functions of a word processor.
Using the cursor displayed on the device DP, position the cursor at the beginning of the block of text, etc. that you want to move. The data such as text for which block movement is to be performed is data that has already been input into the input data buffer IDB and is displayed on the CRT device DP.

To specify the text or other data for which a block is to be moved, as described above, move the cursor to the beginning of the text or other data you wish to move, and use key 22 to determine if the "move range" key KB3 has been pressed for the first time. Therefore, in step 23, the status of the moving range is set in the moving range status register MRSR. Next, in step 24, the address data in the register CR of the memory RAM that stores the data indicated at the cursor position described above is transferred to the range start address register in the memory RAM.
It is stored in the SAR and waits for the next key input.

The position of the cursor and the address of the data in the memory RAM corresponding to the position of the cursor are detected in various word processor processing routines 20 when the cursor is moved, etc. Since this is a matter of course in Setsa, the explanation will be omitted in this explanation.

Next, move the cursor to the final position of the data such as a sentence that you want to move, and press the "Move range" key KB3 again in this state. Test whether there is a status of entry movement range. Microprocessor CPU register MRSR
Find out. In this case, since it has already been set in step 23, the YES branch is selected and the process moves to step 25.

In step 25, the address data of the register CR corresponding to the cursor position at the end of the range is set to the end of range address register EAR. In the next step 26, the subroutine parameter register P1 is set in order to clear the storage area for temporarily storing data for block movement. That is, by setting the register P1 to 2, clearing of the block movement buffer MB is designated as described later.

[Clear record processing]

Since the moving buffer MB has the structure shown in FIG. 3 described above, each record of the moving buffer MB is cleared by the procedure shown in FIG. 5.
That is, since register P1 is set to 2 in step 26, steps 39 and 40 are followed by steps 41 and subsequent steps. Step 41 tests whether the contents of the buffer pointer FTBRP for head movement, that is, the contents of the address next to the head address of the record for head movement, that is, the head address of the record following this record, is 0.

That is, the contents shown at memory location B2 in FIG. 3 are tested.

In Figure 3, memory location B1
The contents written in (FTBRP), that is, the start address of the record leading to the record is 0.
If it is, it indicates that it is the first record of data, etc., and indicates that there are no records that follow before it. Similarly, B2 (FTBRP+
The content written in 1), that is, when the start address of the record following the record is 0, indicates that there are no records following this record, that is, it is the last record.

In the flow described here, the symbol (XX) indicates the contents of the address "XX". For example, in step 41, the result of adding 1 to the contents (address data) of the pointer FTBRP is the address. We are testing whether the content is 0. If there is no next record, step 41 returns YES, so step 42
Then, write 0 to the address of the contents of pointer FTBRP + 2, and return from this subroutine.

In a flow, etc., the notation (XX)→YY means to put the contents of address XX into address YY.

On the other hand, in step 41, the transfer buffer MB is
If there is a record following the first record of B2 ((FTBRP)+1)≠0, step
43, the content of the first address +1 of the first record of the moving buffer MB, ie (FTBRP)+1, is entered at the end of the aforementioned unused record, the second word of the record, ie, the address obtained by adding 1 to the content of LBRP.
In other words, the second record of the moving buffer MB is designated as the record following the last record of the unused records.

Step 44 inputs the address of the last record of the moving buffer MB into the last record pointer LBRP of unused records. Next, in steps 45 and 46, 0 is written into the second and third words of the first record of the moving buffer MB. Step 47 is the record pointer for moving to the beginning of the moving buffer MB.
Record pointer for moving the contents of FTBRP to the end
Completes the subroutine for writing to LTBRP and clearing the transfer buffer MB.

Returning to Figure 4, step 48, 49, 50 in Figure 4,
51, the data of the input data buffer IDB shown in the range stored in steps 24 and 25 is inserted into the moving buffer MB. More specifically, the range start address, range end address, and insertion destination address are entered into parameter registers P1, P2, and P3, respectively, and the block insertion subroutine 51 is entered.

[Block insertion]

This subroutine is shown in FIG. 6, and in steps 52 to 54 registers P1 to P3 are
The contents of , that is, the moving range start address, moving range end address, and insertion destination address, are stored in the register.
SFA, SLA, and IA, the parameters are saved, and in step 55, the start address of the movement range is stored in register SCA. Next step 56,
57 sets the parameters of the data insertion step 58 and inserts one data.

[Data insertion]

Data insertion is shown in FIG. 7, and in steps 59 and 60, register P1, that is, the address of the data to be inserted, is placed in register SDA, and register P2, that is, the address of the insertion destination, is placed in register DA.
Save to. In step 61, the insertion destination address of register DA is ANDed with 1F in hexadecimal notation, or 00011111 in bit notation, or in other words, the LSB (least significant bit) of 1 word (16 bits) is taken. Extrude only the 5th bit from the side, then subtract 3 from the extrusion result and store it in the register DP. The meaning of this step is the data part of the data record, that is, the record in the format shown in FIG.
The number of words to be inserted in the 28 words starting from is stored in register DP.

Next, in step 62, the insertion destination address, that is, the contents of register DA and the address of FFEO in hexadecimal notation, are taken and stored in register RA. This registers the start address of the record at the insertion destination address.
As shown in Figure 3 by storing it in RA, Figure B
1 address is stored in register RA. Note that (XXXX) ₁₆ in steps 61, 62, etc. described above in the flow indicates that XXXX is expressed in hexadecimal notation.

Next, in step 63, it is checked whether the contents of RA+2, that is, the length of the data of the record, is smaller than 28. If the length is less than 28, this indicates that there is a free space in this record, so the data after the data at the insertion destination address is shifted to the right by one word in the form shown in FIG. 3.
That is, the final address of the word group to be shifted is set in register P1, the final address of the word group after shifting is set in register P2, and the word length to be shifted is set in register P3, and the transfer is performed in step 67.

[Transfer processing]

To explain step 67 in detail, as shown in Figure 8,
First, set register N to 0 in step 68.
When the contents of the register N reach the register P3, that is, the word length, in step 69, this subroutine is terminated, and until then, shifting is performed in step 70. Returning to FIG. 7, when this transfer step 67 is completed, the word length of the data of this record is incremented in step 72. Next, in step 73, the data to be inserted, that is, the contents of the register SDA, is transferred to the insertion destination address, that is, the register.
Insert into DA to finish data transfer. On the other hand, in step 63, the data word length of this record is 28.
The above case indicates that there is no space in this record, so it is first tested in step 74 whether the inserted part is the start address of this record, that is, it is tested whether the register DP is 1.
If not, move on to create a new record. In FIG. 9, in steps 75 to 78, the contents of the current first unused record pointer FBRP are placed in register NEWRP, the address of the record following the current record is placed in register CNRP, and the address of the record next to the current first unused record is placed in register CNBRP.
register the length of the current data record.
Save to CRL. Next, in steps 79 to 84, connections of newly created records and connections of unused records are changed. In step 79, the contents of the first unused record pointer CNBRP are changed to the address of the second unused record. Next, step 80 sets 0 to the start address of the record indicated by this newly indicated first unused record pointer FBRP. Next, in step 81, the content saved in step 75 is entered into the second word of the current record, that is, the word indicating the address of the next record. Next, in step 82, a register is added to the address of the contents of register CNRP saved in step 76.
Insert NEWRP content. Next step 83
Now, put the contents of register CNRP into the address indicated by (NEWRP)+1. In step 84, the register RA is placed at the address indicated by the contents of the register NEWRP, completing the combination of new records and the change of the connection of unused records.

Next, in steps 85 to 88, data from the address to be inserted to the end of the record is transferred to a new record. The routine for this transfer is shown in FIG. 8, as described above.
In step 89, change the record length of the record into which data is to be inserted to a new one. In other words, when inserting data, the contents of register DP are RA+
Enter the address shown in 2. In step 90, the data length of the new record is set to the transferred data length. Moving to the next step, the data to be inserted is put into the address indicated by the register DA in step 73 shown in the seventh figure, and the data insertion routine is completed. Also, in step 74, the register DP, that is, the insertion position is set to the first position of the data portion of the record.
If it is the word, the program moves to AL, ie, to FIG. 10, and in steps 91 to 95, the address of the data immediately before the address of the inserted portion is determined. Specifically, the data scanner in step 95 uses as parameters: register P1 is the scan start address, register P2 is the data scan length, register P3 is the scan end address, and register P4 is the scan direction. , 0 indicates the forward direction, and 1' indicates the reverse direction. Note that register P2 and register P3 are used exclusively and are set to 0 if not used.
If you enter , the answer will be entered when you complete Data Scanner 95. For example, in this example, P1=DA, P2=1,
Since P3=0 and P4=1 are specified, register P
3, the data scanner 95 outputs an address at a position scanned from register P1, that is, register DA, by one word, that is, register P2, in the direction indicated by register P4, that is, in the reverse direction. More specifically, in steps 96 to 99 in FIG. 11, the above registers P1 to P4 are saved and the registers are
Store in CSBA, CSL, CSEA, and CSD. In steps 100 and 101, register SCA is set to the contents of register CSBA, and register DSC is set to 0 to set an initial value.

Next, in step 102, if register CSL is less than 0, that is, the scan length is less than 0, step 102 is executed.
At step 103, the register CSEA, that is, the scan final address is checked, and if this is also less than 0, the parameter is defective and this subroutine ends. In other cases, move to and start scanning. In FIG. 12, in step 104, the start address of the record at the current address being scanned is stored in register SRA. Next, in step 105, SCA+1-2×CSD is stored in register SCA.That is, if register CSD is 0, that is, in the case of forward scan, register SCA is counted up, and if register SCA is 1, that is, in the case of backward scan, register SCA is counted up. Count down. (In this example, it is a countdown.) Next, in step 106, the contents of the register SCA that has been counted up or down in the above are set to SRA+
It is checked whether the address is smaller than 3, that is, if it is in the addresses shown in B1, B2, B3, and B4 of the record, as shown in FIG. this is
SCA≦SRA+(SRA+2)+3 i.e. register SCA
This is to test whether the contents of register SRA are within the address of the last data of the record starting with the contents of register SRA. If YES, the process moves to step 109 and increments the register DSC that counts the scan length. Next step
At 110, it is checked whether the register CSL is less than or equal to 0. In other words, when the contents of register CSL are greater than 0, it indicates that the scan length is specified as described above, so the process moves to step 111 and compares register DSC and register CSL, and register DSC is higher than register CSL. If it is smaller, the same routine as above is executed again from AM, and when DSC=CSL, step 112 is entered. In step 112, the contents of register P3 are stored in register SCA. That is, register P3 is set as the current address and this subroutine is exited.

On the other hand, if CSL≦0 in step 110, that is, if the scan length is not specified, step 110
113, the register SCA and the register CSEA are compared to see if they are equal, that is, the current address and the scan final address are compared, and if they are equal, the step is executed.
At step 114, the register P2 is stored in the register DSC, that is, the value counted up during the scan is made into the value, and this subroutine ends.

On the other hand, if SCA≦SRA+3 in step 106, proceed to step 115 (SRA+1−CSD)
Test whether is 0. That is, step 115 checks whether the next record to be scanned is 0, and if the next record to be scanned is 0.
In other words, if there is no record following the current record, the process moves to step 116, and if CSL≦0, CSD-1 is stored in P3 in step 117, and CSL>
If it is 0, the subroutine ends with P2=DSC at step 118. If it is found in step 115 that there is a record to be scanned next, the process goes to step 119 and the SRA is (SRA+1-1).
CSD), and in step 120, SCA is SRA+
4 + CSD × [(SRA + 2)] In other words, SCA is set as SRA + 4 when CSD (scan direction) is 0, and
When CSD is 1, SRA+4+CSD×[(SRA+
2)].

In this formula, the same as in other cases (SRA + 2)
indicates the content of SRA+2. After completing the above steps, the process returns to step 105 and repeats the same steps as above. Also step 108
If the answer is NO, step 119 is entered and steps similar to those described above are executed. When step 95 of the data scanner subroutine in FIG. 10 is completed as described above, step 120 in FIG. 10 is entered next. In step 120, P3 and (FFEO) ₁₆ are ANDed and stored in register PR. That is, if the address to be inserted is at the beginning of the data portion of the current record, the address of the previous record is stored in register PR. After that, in step 121, check the data length of the record indicated by the register PR, that is, check (PR+2)≧28. If YES, there is no longer a free address to insert here, so the data is transferred. Perform the steps mentioned above in the same way. If NO, the program moves to step 122 and writes the data to be pressed (SDA) to P3+1, that is, the address next to the address of P3 determined in data scanner step 95. Next, in step 123, the data length of this record is incremented, and this data insertion subroutine is terminated.
Complete step 58 in the diagram.

Subsequently, in steps 124 to 128 in FIG. 6, the address of the data next to the address of the register SCA is determined. The data scanner for step 128 is the 10th
As explained above, step 95 in the figure is exactly the same as that explained in FIG. 11 et seq. Therefore, in data scanner step 128, the next address is placed in register P3. Next, in step 129, the SCA and SLA, that is, the source data address for data insertion executed in step 58 and the final address of block insertion are compared, and if they are equal, step 130 is performed.
The contents of the register P3, which stores the address obtained in the data scanner step 128, are placed in the current value register NR, thereby completing the block insertion. If NO in step 129, the contents of P3 are stored in the register SCA in step 131, and the process goes to step 132.In step 58, it is checked whether the inserted data is a character code.If YES, in step 133, the contents of P3 are stored in the register SCA. After incrementing the cursor position, if NO again, the process immediately moves to step 134. Steps 134 to 138 determine the next insertion destination address. The result, that is, the contents of register P3, is stored in IA at step 139, and the process returns to step 56 to repeat the routine already described. Insert the fourth block by the above process.
Upon completion of FIG. 51, the process enters the step of FIG. 4 140.
In steps 140 to 142, the source data of the data inserted in step 51, that is, the block whose range was set in steps 24 and 25, is deleted.
Specifically, in step 140, register P1
Let the contents of be the start address of the data to be deleted,
The final address of the data to be deleted is set in P2. Next, the process moves to step 142, ie, step 143 in FIG. 13 is entered. Steps 143 to 144 save the parameters of registers P1 and P2 above in registers DLFA and DLLA, respectively, and
Store the contents of DLCA in DLLA. This block deletion is performed by sequentially deleting the last data of the block to be deleted up to the first data. The contents of the register DLLA, which stores the final address of the block to be deleted, are stored in the register DLCA in step 145, and in steps 146 and below, the data at the address indicated by the register DLCA is deleted, and then the previous data in the register DLCA is searched. The block is deleted by deleting it again. More specifically, in step 146, P1=DLCA is set and a data deletion subroutine 147 is entered. Step 147 is explained in FIG. Step 148 stores the address of the data to be deleted in the register SDLA, and step 149 stores the address of the record of the address of the data to be deleted in the register SDRA. Next, in step 150, it is tested whether the data length of this record is less than or equal to 1, and if it is not less than or equal to 1, step 151 is entered. In step 151, it is checked whether the contents of register SDLA are the address of the end data of the record, that is, SDLA≧SDLRA+
If (SDLRA+2)+3, enter step 152,
Decrement the data length of this record.

Next, at step 153, the register SDLA is also decremented, and the process moves to FIG. 16, at step 154.
-157, the address of the next data in the current register SDLA is obtained, and step 159 sets P2=P3, and this subroutine ends. Also, step
If NO in step 151, specify parameters for reverse transfer step 163 in steps 160-162. That is, register P1 is the start address of the transfer source, register P2 is
is the start address of the transfer destination, register P3 is the transfer length, and the data to be transferred is transferred to the transfer destination in order from the beginning by the transfer length. More specifically, in FIG. 15, in step 164, N=
0, then in step 165 register N
is compared with register P3, that is, the transfer length, and repeats steps 166 and 167 until the transfer length is equal.
When it becomes equal, this reverse transfer routine ends and the 14th
Enter step 168 in the figure. Step 168 decrements the data length of the record and then steps
168' sets P2=SDLA and exits from the data deletion subroutine. Also, if the data length of this record is 1 in step 150, enter
In step 169 of FIG. 17, it is tested whether this record is the last record of the data records, that is, the content of the last data record pointer, and if it is not the last record, that is, SDLR≠
(LDRP), this record is deleted by steps 170 to 177. To explain in detail, in step 170, the contents of the last unused record pointer LBRP are saved as the contents of register LBR1,
In step 171, the address indicated by the register SDLRA, ie, the start address of the record following the record to be deleted, is entered into the address indicated by (SDLRA+1), ie, the start address of the record following the record to be deleted. Next, in step 172, (SDLRA+1) is converted to (SDLRA)+
1, that is, the start address of the next succeeding record is entered in the second word of the preceding record. Next, in step 173, SDLRA is placed at the address indicated by (LBRP)+1, ie, the record to be deleted is placed in the string of unused records. Next, in step 174, the second word of this record to be deleted is set to 0. At step 175, register SDLRA, that is, the address of the record to be deleted, is placed in the last unused record pointer LBRP. Next step
At step 176, the contents of register P2 are set to be the address contained in the data following the deleted data. Next, in step 177, the deleted record, ie, the record saved in step 170, is inserted into the address indicated by the end unused record pointer LBRP, and the data deletion subroutine is ended. Also, in step 169
If YES, that is, if the record to be deleted is the last data record, the process moves to AJ, and this record is deleted by steps 178 to 186 in FIG. To explain in detail, steps 178 and 179 point to the last data record pointer.
The addresses indicated by LDRP and the last unused record pointer LBRP are stored in registers LDR1 and LBR1, respectively.
Save to. In step 180, the last data record pointer LDRP is the first address of the record following the record to be deleted, that is, the register LDR.
1 contents, and then step to the last unused record pointer LBRP in step 181.
Enter LDR1 saved in step 178, that is, the start address of the record to be deleted. Next, in step 182,
Insert 0 into the address indicated by (LDRP)+1.
Next, in step 183, LBR1 is placed in the address indicated by register LDR1. Next step
At step 184, the contents of register LDR1 are placed in the address indicated by LBR+1.

Next, in step 185, 0 is put into the address of (LDRP)+1. Next, in step 186, register P2 is set to -1 to indicate that the current cursor position is the last position of the record, and the data at the address specified in register P1 is deleted by the data deletion routine, and the data at the address specified by register P2 is stored in register P2. Finishes the job of entering the address of the next data after the data. Next, in step 187, the register P2 is changed to the contents of register DLCA, and then in steps 188 to 193, the contents of register DLCA are changed to the address of the data immediately preceding the data currently indicated by DLCA. That is, the data scanner described above returns the address of the previous data to the register P3, and in step 193 it is set as the contents of the register DLCA. Then register in 194 steps.
The contents of DLCA are the registers saved in step 143.
Steps 146 to 193 are repeated until the address becomes equal to DLFA, that is, the start address of the data block to be deleted. When the address becomes equal, the block deletion is completed, and the block deletion subroutine ends.

As described above, the block is deleted in step 142 of FIG. 4, the status of the moving range is reset in step 194, and ZZ is entered.

Figure 19 Enter step 195 from ZZ and CRT device
Set the address LHA(1) of the first data of DP to register P.
1 and enters the display subroutine to rewrite the contents of the memory M in FIG. That is, the read character codes are sequentially read out and stored in the memory M10 from address LHA(1) of the display head data, thereby displaying them on the CRT device DP. As a result, the data within the range defined by the ``movement range'' is stored in the transfer buffer, deleted from the original data, and deleted from the CRT screen.

Next, move the cursor to the desired destination and press the "Move destination" key KB4 on the keyboard 5.
The process moves to step 197 (FIG. 4), and the destination address is stored in step 198 of FIG.
Next, in steps 199-202, the data stored in the moving buffer is inserted into a desired position.

The block insertion step 202 is exactly the same as described above. Next, go to ZZ and make a new display on the CRT in the same way as when entering from step 194 above.

The block transfer has been performed above, but the data in the transfer buffer is saved even after the transfer, so by placing the cursor at the desired position again and pressing the "Transfer destination" key KB4, the same data can be transferred. can be copied and inserted.

[Effects] As detailed above, according to the present invention, a desired character string can be specified by specifying the beginning and end, and the specified character string can be stored. It is now possible to provide a character processing device that can quickly insert the designated character string every time an instruction is given to insert the specified character string into a desired insertion location in a document.

According to the present invention, it is possible to specify a desired character string in the document being created, and the desired main character string can be inserted each time an instruction for insertion is given at a desired position in the document. It has now become possible to provide a character processing device with very good operability, which allows documents to be created while duplicating desired character strings in the document.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a character processing device according to the present invention, and FIG. 2 is a memory shown in FIG. 1.
A detailed diagram of the RAM, FIG. 3 is an explanatory diagram of the moving buffer MB shown in FIG. 2, and FIGS. 4 to 20 are diagrams explaining the control procedure. KB3...Movement range key, KB4...Movement destination key, ROM...Control memory, RAM...Memory.

Claims (1)

[Scope of Claims] 1. Data storage means for storing a data string representing a document; during creation of the document, the beginning and end of a desired part of the data string within the data string stored in the data storage means; specifying means for specifying the desired partial data string by specifying; storage means for storing the partial data string specified by the specifying means; specifying by the specifying means; an instruction means for instructing an insertion destination of the partial data string stored in the storage means in the data string, and for instructing that the partial data string stored in the storage means be inserted into the insertion destination; and an insertion control means for inserting the part of the data string at an insertion position in the data string corresponding to the arbitrary insertion destination each time an insertion instruction is given to an arbitrary insertion destination by the means. Characteristic character processing device.