JPH0778798B2 - Character processing method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a character processing device capable of storing a plurality of blocks of data representing a plurality of character strings in association with each other.

[Prior Art] Conventionally, there has not been a character processing device capable of storing a plurality of blocks of data representing a plurality of character strings in association with each other.

Further, there is a drawback that a character processing device capable of editing cannot be expected.

[Object] In view of the above points, an object of the present invention is to specify a part of a character string of a desired arbitrary length in a document stored in the first storage unit, thereby enabling the partial character It is possible to store a column in the second storage means and manage the unused area in the first storage means that changes accordingly, and further, based on an instruction of transfer to a desired position in the document, A desired variable amount of character string can be transferred into the document, the unused area that changes accordingly can be further managed, and the creation of the document can be performed by copying the desired character string in the document. Another object of the present invention is to provide a character processing method that can be performed while maintaining the unused area of the storage means.

[Example] An example according to the present invention will be described below.

FIG. 1 is a block diagram of a character processing device according to the present invention. In the figure, the CPU is a microprocessor, which performs arithmetic operations and logical judgments. AB is an address bus and transfers a signal indicating a control target. DB is a data bus that transfers various data and is a bidirectional bus. CB is a control bus that applies control signals to various control targets.

KB is a keyboard, key KB1 to enter characters, functions and modes, space key KB to enter a space
2, move range key KB3 to move the entered text,
And a destination key KB4 or the like for inserting a sentence to be moved.

KBC is a keyboard controller, which encodes data input from the keyboard KB and sends an interrupt signal to the control bus CB. DPC is a CRT controller, which controls the CRT device DP, the character generator CG, the refresh memory M, and the refresh memory controller MC3. The CRT device DP can display characters, symbols, pictures and the like. The character generator CG outputs a desired character / symbol pattern by inputting a code such as a character code / symbol code and a line address of the character / symbol pattern. The character / symbol pattern is formed in a matrix, and the character / symbol pattern is output by changing the row address. The refresh memory R stores the character / symbol code displayed on the CRT device DP and repeatedly outputs the character / symbol code under the control of the CRT controller DPC. The refresh memory controller MC3 controls the refresh cycle of the refresh memory R and the writing and reading of data from the microprocessor CPU according to the instruction of the CRT controller DPC. The ROM is a control memory that stores various processing procedures, the control procedures shown in FIGS. 4 to 20, and kanji information.

The processing procedure stored by the ROM controller MC1 is read out from the control memory ROM. RAM is a random access memory and is used for temporary storage of various data.

FIG. 2 further explains the main part of the memory RAM.
RSR is the movement range status register, SAR is the movement range start address register, EAR is the movement range end address register, MB is the movement buffer, IDB is the input data buffer, U
B is an unused buffer, P1 to P4 are parameter registers, CR
Is a cursor register, N is a register, FDRP is the first data record pointer, LDRP is the last data record pointer, FBRP is the first unused record pointer, LBRP is the last unused record pointer, FTBRP is the first movement record pointer, and LTBRP is the last. It has a move record pointer and the like, and further has the illustrated register group.

The block transfer buffer MB that stores the above-mentioned transfer target text has a structure as shown in FIG. 3, and this structure has the same structure as the input data buffer IDB that stores the input data, and is unused. The buffer UB has a similar structure. Transfer buffer MB, input data buffer
Each of the IDB and the unused buffer UB is made up of one or a plurality of records shown in FIG. 3, and the number of records is increased or decreased as necessary as described later.

B1 is a memory location that stores the start address of the record that is connected before this record, B2 is a memory location that stores the start address of the record that is connected after this record, and B3 is valid in this record. It is a memory location that stores the length of data. The data stored in the record is up to 28 words, and is sequentially filled from the position of the memory location B4.
This is what is commonly called a list structure.

The connection of a plurality of records is as described above, but the addresses of the first record connected before a certain record and the last record connected after a certain record are designated by various pointers. That is, in this case, the first record of the moving buffer MB is stored in the pointer FTBRP, and the last record thereof is stored in the pointer LTBRP. Similarly, the head data record pointer of the input data buffer IDB is stored in the pointer FDRP, the tail data recorder pointer thereof is stored in the pointer LDRP, and the record of the unused buffer UB is stored in the pointer FBRP and the pointer LBRP, respectively.

The memory RAM is written and read by the RAM controller MC2. MD is a magnetic disk device, which stores kanji information in a format described later. The magnetic disk device MD is controlled by the magnetic disk controller MDD.

A printer P records information such as kanji information, katakana, and hiragana, and is controlled by the printer controller PD.

The operation of the embodiment configured as described above will be described in detail below.

The character processing device is activated by operating the keyboard KB. When the keyboard KB is operated, the interrupt signal generated from the keyboard KB is transmitted to the microprocessor CPU, which causes the microprocessor C to operate.
The control procedure in the control memory ROM is called via the PU, and each control is performed according to the control procedure.

The object of the present invention is achieved by the control procedure stored in the first illustrated memory ROM. When various inputs are made from the keyboard KB, the interrupt is applied and the ROM is ROM
Control is transferred to the program area stored in it. This control program is shown in the flow chart of FIG. 4 and subsequent figures, and will be described in order below.

In the flow chart of FIG. 4, various processing routines in the word processor are omitted and shown as various word processor processing routines 20 in order to make the block transfer function of the present invention particularly clear. When moving the block, first use the cursor displayed on the CRT device DP, which is one of the processing functions of the word processor,
Position the cursor at the beginning of the block of the text you want to move. The data such as the text to move the block is already entered in the input data buffer IDB.
It is what is displayed on the RT device DP.

As described above, when the cursor is at the beginning of the data of the text or the like to be moved, press the "Movement range" key KB3 on the keyboard KB to enter step 21 in the flow shown in FIG. The CPU determines YES (displayed as Y in the flow), and proceeds to step 22.
In step 22, the above-mentioned key "Movement range" key KB3
Is already pressed by checking the movement range status register MRSR in the first memory RAM shown in the figure. In this case, the movement range status register MRSR has been set. Since this is not the case, the status is not within the movement range, and the routine proceeds to NO (displayed as N in the flow) and proceeds to step 23. Step
Since the "moving range" key KB3 is pressed for the first time in 23, the moving range status is set in the moving range status register MRSR. Next, in step 24, the address data in the register CR of the memory RAM that stores the data shown at the above-mentioned cursor position is stored in the range start address register SAR in the memory RAM, and the next key input standby state is set. .

The cursor position and the memory corresponding to this cursor position
It is natural in the word processor using the CRT device DP for display that the address of the data in the RAM is detected in the various word processor processing routines 20 when the cursor is moved, etc. Is omitted.

Next, move the cursor to the final position of the data such as the text you want to move, and press the key "Move range" KB3 again in this state, and go to step 22 via step 21 as in the case above. Test if there is status of incoming movement range. The microprocessor CPU examines the register MRSR. In this case, since YES has already been set in step 23, the YES branch is selected and step 25 is entered.

At step 25, the address data of the register CR corresponding to the cursor position at the end of the range is set to the end-of-range address register EAR. At the next step 26, the parameter register of the subroutine is used to clear the storage area for temporarily storing the data for moving the block.
Set P1. That is, by setting the register P1 to 2, clearing of the block moving buffer MB is specified as described later.

Since the transfer buffer MB has the above-described structure, each record of the transfer buffer MB is cleared by the procedure shown in FIG. That is, since the register P1 is set to 2 in step 26, the operations following step 41 are performed after steps 39 and 40. Step 41 tests whether or not the contents of the above-mentioned buffer buffer pointer FTBRP for moving the head, that is, the contents of the address next to the head address of the record for moving the head, that is, the head address of the record connected to this record is zero.

That is, the contents shown in FIG. 3 memory location B2 are being tested.

When the content written in the memory location B1 in FIG. 3 is 0, it indicates that it is the first record of data or the like, and that there is no record that follows it. Similarly, if B2 contains 0, it means that there is no record connected to this record, that is, the last record.

Note that in the flow and the like described here, what is indicated by (XX) indicates the contents of the address "XX". For example, in step 41, the contents of the pointer FTBRP (address data) I'm testing if the content is zero. If there is no next record, the result in step 41 is YES, so the process moves to step 42 and 0 is written in the address +2 of the content of the pointer FTBRP to return from this subroutine.

In the flow etc., the notation (XX) → YY means to put the contents of address XX in address YY.

On the other hand, if there is a record following the first record of the transfer buffer MB in step 41, that is, ((FTBRP) +
1) If ≠ 0, move to step 43 and set 1 at the end of the unused record, the second word of the record, that is, the content of LBRP.
The contents of the first address +1 of the first record of the moving buffer MB, that is, (FTBRP) +1, are put in the address added with. In other words, the second record of the moving buffer MB is designated as the record following the last record of the unused record.

Step 44 is the end record pointer LB of the unused record
Enter the address of the last record of the transfer buffer MB in RP. Next, in steps 45 and 46, 0 is written in the second and third words of the first record of the moving buffer MB. Step 47 is the record pointer for moving the beginning of the moving buffer MB.
The contents of FTBRP are written to the end move record pointer LTBRP, and the subroutine for clearing the move buffer MB is completed.

Then, the data of the input data buffer IDB indicated by the range stored in steps 24 and 25 is inserted into the moving buffer MB by steps 48, 49, 50 and 51 of FIG. More specifically, the range start address, the range end address, and the insertion destination address are entered in the parameter registers P1, P2, and P3, respectively, and the block insertion subroutine 51 is entered.

This subroutine is shown in FIG. 6, and in steps 52 to 54, the contents of the registers P1 to P3 are stored in the register SF.
Put it in A, SLA, IA, save the parameters, and
At, the start address of the source range is placed in register SCA. Next, in steps 56 and 57, the data insertion step 5
Set 8 parameters and insert 1 data. The data insertion is shown in FIG. 7, and in steps 59 and 60, the register P1 or the address of the data to be inserted is stored in the register SDA, and the register P2 or the insertion destination address is stored in the register DA. In step 61, the address of the insertion destination of the register DA and the IF in hexadecimal notation, that is, 0111111 according to bit notation, is taken, that is, in other words,
Only the 5th bit is extruded from the 1st word (16bits) LSB (least signature bit) side, and then 3 is subtracted from the extruded result and stored in the register DP. The meaning of this step is to store in the register DP the record of the data, that is, the data portion of the record of the type shown in FIG. 3, that is, the number of the 28th word to be inserted starting from the illustrated location B4.

Next, in step 62, the AND address of the insertion destination, that is, the contents of register DA and FFEO in hexadecimal notation
Store in RA. This is to store the head address of the record of the address of the insertion destination in the register RA, and thereby store the address of B1 shown in FIG. 3 in the register RA. In the flow, in steps 61, 62, etc. above (XXX
X) 16 indicates that XXXX is in hexadecimal notation.

Next, in step 63, it is checked whether or not the content of RA + 2, that is, the data length of the record is smaller than 28. If the length is less than 28, this indicates that there is an empty space in this record, so the data after the data of the address of the insertion destination is shifted to the right by one word in the form of FIG. That is, the final address of the word group to be shifted to the register P1, the final address of the word group after the shift to the register P2, and the word length to be shifted to the register P3 are set, and transfer is performed by the step 67. Step
As will be described in detail with reference to 67, as shown in FIG. 8, first, the register N is set to 0 at step 68, and when the content of the register N becomes the above-mentioned register P3, that is, the word length at step 69, this sub-routine is finished. Until step 70 shifts. When this transfer step 67 ends, the word length of the data of this record is then incremented by step 72. Next, in step 73, the data to be inserted, that is, the content of the register SDA is put into the address of the insertion destination, that is, the register DA, and the data transfer is completed. On the other hand, if the data word length of this record is 28 or more at step 63, it means that there is no space in this record, so first test at step 74 whether the inserted portion is the start address of this record, That is, it is tested whether or not the register DP is 1, and if it is not 1, the process moves to to newly install a register. In FIG. 9, steps 75-78
The contents of the current head unused record pointer FTBRP are registered in the register NEWRP, the address of the record following the current record is registered in the register CNRP, the address of the record next to the current head unused record is registered in the register CNBRP, and the length of the current data record is recorded. Save to register CRL. Then step 7
Change the connection of new record and the connection of unused record by 9 to 84. In step 79, the contents of the first unused record pointer CNBRP are set to the second unused record.
Change to the record address. Next, the step 80 puts 0 into the head address of the record indicated by the newly shown head unused record pointer FBRP. Next step
At step 81, the contents stored at step 75 are put into the second word of the current record, that is, the word indicating the address of the succeeding record. Next, in step 82, the content of the register NEWRP is put into the address of the content of the register CNRP saved in step 76. Then in step 83 (NEWRP) +1
Put the contents of register CNRP at the address indicated by. In step 84, the register RA is put in the address indicated by the contents of the register NEWRP to complete the merging of new records and the change of connection of unused records.

Then, in steps 85 to 88, the data from the address to be inserted to the end of the record is transferred to the new record. The transfer routine is shown in FIG. 8 as described above. In step 89, the record length of the record in which the data is inserted is changed to a new one. That is, the place to insert the data, that is, the contents of the register DP
Enter at the address indicated by RA + 2. At step 90, the data length of the new record is set to the transferred data length. Moving to the next step, the data to be inserted in step 73 shown in FIG. 7 is placed in the address indicated by the register DA and the data insertion routine is ended. In step 74, if the register DP, that is, the insertion position is the first word of the data portion of the record, the operation moves to AL, that is, FIG. Ask for an address. In detail, the step
The data scanner of 95 is a parameter, the register P1 is the scan start address, the register P2 is the scan length of the data, the register P3 is the scan end address, the register P4 is the scan direction, 0 is the forward direction, 1'indicates the opposite direction. Register P2 and register P3
Is used exclusively, and when it is not used, if 0 is entered, the answer will be entered when the data scanner 95 is completed. For example, in this example, P1 = D according to steps 91 to 94.
Since A, P2 = 1, P3 = 0, P4 = 1 are specified, the register P3 has the address of the position skipped from the register P1 (register DA) to the register P2 (1 word) in the direction indicated by the register P4, that is, in the reverse direction. The data scanner 95 outputs. More specifically, the registers P1 to P4 are saved in steps 96 to 99 in FIG.
Store in BA, CSL, CSEA, CSD. In steps 100 and 101, set register SCA to the contents of register CSBA,
Set the register DSC to 0 and set the initial value.

Next, when the register CSL is 0 or less, that is, the scan length is 0 or less in step 102, the register CSEA, that is, the scan final address is checked in step 103.
If this is also 0 or less, the parameter is defective and this subroutine is terminated. In other cases, move to and start skiyan. In FIG. 12, the start address of the record of the current address in the scan is registered in step 104.
Store in SRA. Next, at step 105, SCA + 1-2
Store CSD in register SCA, that is, if register CSD is 0, that is, forward scan, count up register SCA, and if register SCA is 1, that is, reverse direction, count down (in this example, count down). Become.).

Next, at step 106, the content of the register SCA counted up or down is smaller than SRA + 3, that is, the third
Explaining with reference to the figure, it is checked whether the address is in the address B1, B2, B3, B4 shown in the record, and if it is not within this period, the process proceeds to step 108. This is SCA
≤SRA + (SRA + 2) "3, that is, whether the content of the register SCA is within an address of the final data of the record starting with the content of the register SRA. YE
If it is S, the process proceeds to step 109 and the register DSC that counts the length of the scan is incremented. Then step 1
In 10 it is checking whether the register CSL is 0 or less. That is, when the content of the register CSL is greater than 0, it is indicated that the scan length is specified as described above. Therefore, the process moves to step 111, the register DSC is compared with the register CSL, and the register DSC is the register CSL. If it is smaller, the same routine as above is repeatedly executed from AM again, and when DSC = CSL, step 112 is entered. At step 112, the contents of register P3 are changed to register S
Store in CA. That is, this subroutine is skipped with the register P3 as the current address.

On the other hand, if CSL ≦ 0 in step 110, that is, if the scan length is not specified, step 113 compares whether the register SCA and the register CSEA are equal, that is, the current address and the scan final address are compared and equal. Stores the register P2 in the register DSC in step 114, that is, sets the value counted up at the time of scanning to the end of this subroutine.

On the other hand, if SCA≤SRA + 3 in step 106, the process moves to step 115 to test whether (SRA + 1-CSD) is 0 or not. That is, step 115 is checking whether the record to be skipped next is 0, and when the record to be skipped next is 0, that is, when there is no record following the current record, the process proceeds to step 116 and CSL≤0. If it is, CSD-1 is stored in P3 at step 117, and if CSL> 0, then at step 118 P2 = DSC is set and this subroutine is finished. If it is found in step 115 that there is a record to be skipped next, it is transferred to step 119, SRA is set to (SRA + 1-CSD), and SCA is set to SRA in step 120.
+ 4 + CSD × [(SRA + 2)] That is, SCA is SRA + 4 when CSD (scan direction) is 0, and when CSD is 1, SRA + 4 + CSD × [(SRA + 2)].

In this formula as well as in other cases (SRA + 2) is SRA + 2
It shows the contents of. After completion of the above steps, the process returns to step 105 and the same steps as above are repeated. If NO in step 108, step 119 is entered and the same step as above is executed. When the data scanner subroutine of FIG. 10 is completed as described above, step 120 is entered next. In Step 120, P3 and (FFE
O) The AND of 16 is taken and stored in the register PR. That is, when the address to be inserted is the head of the data portion of this record, the address of the previous record is stored in the register PR. Then, at step 121, register PR
Check the data length of the record shown in, ie (PR + 2)
If ≧ 29 can be checked and YES is determined, there is no free address to be inserted here. Therefore, the above steps are similarly executed. In the case of NO, the data to be pushed to step 122, that is, (SDA), is written in P3 + 1, that is, the address next to the address of P3 obtained in the data scan step 95. Next, at step 123, the data length of this record is incremented, the data insertion subroutine is ended, and step 58 of FIG. 6 is completed.

Then, in steps 124 to 128, the address of the data next to the address of the register SCA is obtained. The data scanner of step 128 is exactly the same as that described with reference to FIG. Therefore, in the data scan step 128, the next address is placed in the register P3. Next, in step 129, the SCA and SLA, that is, the register for storing the address obtained in the data scanner step 128 in step 130 if the address of the source data for data insertion executed in step 58 and the final address of block insertion are compared. Put the contents of P3 into the current value register NR and complete the block insertion. If NO in step 129, the contents of P3 are stored in the register SCA by step 131 and transferred to step 132, and it is checked whether the data inserted in step 58 is a character code. If YES, step 133 displays the CRT display. After incrementing the cursor position,
If NO, move to step 134 immediately. Steps 134-138
Then, the address of the next insertion destination is obtained. As a result, that is, the contents of the register P3 are stored in IA in step 139, the process returns to step 56 and the above-mentioned routine is repeated. When the block insertion process shown in FIG.
Enter 140 steps. Steps 140-142 delete the source data of the data inserted by step 51, i.e. the blocks bounded by steps 24 and 25. More specifically, in step 140, the content of the register P1 is set as the start address of the data to be deleted, and the final address of the data to be deleted is set in P2. Then move to step 142, that is, enter step 143 of FIG. Steps 143 to 144 save the parameters of the registers P1 and P2 in the registers DLFA and DLLA, respectively, and the contents of the register DLCA in DLLA. In this block deletion, the last data of the block to be deleted is traced back to the top data in order. The contents of the register DLLA that stores the final address of the block to be deleted are stored in the register DLCA in step 145, the data of the address indicated by the register DLCA is deleted in step 146 and thereafter, and the data immediately before the register DLCA is searched. The block is deleted by deleting again. More specifically, in step 146, P
1 = DLCA is set and the data deletion subroutine 147 is entered. Step 147 is illustrated in FIG. Step 148 saves the address of the data to be deleted in register SDLA,
The record address of the data address to be deleted in 9 is stored in the register SDRA. Next, in step 150, it is tested whether the data length of this record is 1 or less, and if it is not 1 or less, step 151 is entered. In step 151, it is checked whether the contents of the register SDLA is the address of the data at the end of the record, that is, SDLA ≧ SDLRA + (SDLRA
If +2) +3, step 152 is entered and the data length of this record is decremented.

Next, in step 153, the register SDLA is also decremented, and the process proceeds to FIG. 16. In steps 154 to 157, the address of the next data of the current register SDLA is obtained, and in step 159, P2 = P3 is set, and this subroutine is ended. If NO in step 151, the parameters of the reverse transfer step 163 are specified in steps 160 to 162. That is, the register P1 is the transfer source start address, the register P2 is the transfer destination start address, and the register P3 is the transfer length. The transfer length is transferred to the transfer destination in order from the start of the data to be transferred.
More specifically, in step 15 of FIG.
= 0, next, in step 165, the register N and the register P3 are compared, that is, the transfer length is compared, and steps 166 and 167 are repeatedly transferred until they become equal. When they become equal, this reverse transfer routine is ended and step 168 in FIG. 14 is entered. At step 168, the data length of this record is decremented, and then at step 168 ', P2 = SDLA is set and the data deletion subroutine is skipped. Also, if the data length of this record is 1 in step 150, it is entered, and in step 169 of FIG. 17, it is tested whether this record is the last record of the data record, that is, the content of the end data record pointer, and it is not the last record. In case of SDLR ≠ (LDRP), this record is deleted in steps 170 to 177. In detail, step
At 170, the content of the unused record pointer LBRP at the end is saved as the content of the register LBR1, and at the address indicated by (SDLRA + 1) in step 171, that is, at the head address of the record following the record to be deleted, the register is stored.
Enter the address indicated by SDLRA, that is, the start address of the record preceding the record to be deleted. Next step
In (172), (SDLRA + 1) is put in the address indicated by (SDLRA) +1, that is, the head address of the next succeeding record is put in the second word of the preceding succeeding record. Next, in step 173, SDLRA is put in the address indicated by (LBRP) +1, that is, the record to be deleted is put in the string of unused records. Next, at step 174, the second word of the record to be deleted is set to 0.
End unused record pointer LBRP in step 175
Into the register SDRRA, that is, the address of the record to be deleted. Next, at step 176, the content of the register P2 is set to the address containing the data following the deleted data. Then, in step 177, the record deleted in step 177, that is, the address stored in the trailing unused record pointer LBRP is set to the address stored in step 170 and the data deletion subroutine is terminated. If YES in step 169, that is, if the record to be deleted is the end data record,
Move to AJ and delete this record by steps 178 to 186 in FIG. More specifically, in steps 178 and 179, the addresses indicated by the end data record pointer LDRP and the end unused record pointer LBRP are stored in the registers LDR1 and LBR1, respectively. In step 180, the end address of the record preceding the record to be deleted, that is, the content of the register LDR1 is put in the end data record pointer LDRP, and then in step 181 the LDR1 stored in the end unused record pointer LBRP in step 178 is stored.
That is, the start address of the record to be deleted is entered. Next, at step 182, 0 is put in the address indicated by (LDRP) +1. Then in step 183 the register LDR1
Insert LBR1 at the address indicated by. Then step 184
In, the contents of the register LDR1 are put into the address indicated by LBR1 + 1.

Next, at step 185, 0 is added to the (LDRP) +1 address.
Put in. Next, in step 186, the register P2 is set to -1.
Indicates that the current cursor position is the final position of the record. Thus, the data at the address specified by register P1 is deleted by the above data deletion routine, and the register
The work of putting the address of the next data of the above deleted data into P2 is completed. Next, in step 187, the above-mentioned register P2 is set to the contents of the register DLCA, and next, in steps 188 to 193
Causes the contents of register DLCA to be changed to the address of the data immediately before the data currently indicated by DLCA. That is, the address of the previous data is registered by the data scanner described above.
It is returned to P3, and the contents of the register DLCA are set in step 193. Next, in step 194, the contents of the register DLCA are equal to the register DLFA saved in step 143, that is, the start address of the data block to be deleted.
146 to 193 are repeated, and if they are equal, it means that the block deletion is completed, so the block deletion subroutine is ended.

As described above, the block of the step 142 shown in FIG. 4 is deleted, the status of the movement range is reset by the step 194, and the step ZZ is entered.

From ZZ in FIG. 19, the step 195 is entered, the address LHA (1) of the head data of the CRT device DP is stored in the register P1, the display subroutine is entered, and the contents of the memory M in FIG. 1 are newly rewritten. That is, the read character code is sequentially read from the address LHA (1) of the display start data in the memory M
By putting in 10, it is displayed on the CRT device DP. As a result, the data within the range defined by the "moving range" is stored in the moving buffer, deleted from the original data, and deleted from the CRT screen.

Next, bring the cursor to the desired destination and press the keyboard 5
When you press the "Move to" key above, step 197 (4th
Then, the address of the destination is stored by step 198 in FIG. Next, in steps 199 to 202, the data stored in the moving buffer is inserted into a desired position.

The block insertion step 202 is exactly the same as described above. Then move to ZZ, and make a new display on the CRT, just as when entering from step 194 above.

The block transfer was performed as above, but since the data in the transfer buffer is saved even after the transfer, move the cursor to the desired position again and press the "transfer destination" key to copy the same data. Can be duplicated and inserted.

[Effect] As described above in detail, according to the present invention, by designating a partial character string of a desired arbitrary length in the document stored in the first storage means, the partial character It is possible to store a column in the second storage means and manage the unused area in the first storage means that changes accordingly, and further, based on an instruction of transfer to a desired position in the document, A desired variable amount of character string can be transferred into the document, the unused area that changes accordingly can be further managed, and the creation of the document can be performed by copying the desired character string in the document. However, it is possible to provide a character processing method that can be performed while maintaining the unused area of the storage unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a character processing device according to the present invention, FIG. 2 is a detailed diagram of the memory RAM shown in FIG. 1, and FIG. 3 is an explanatory diagram of a transfer buffer MB shown in FIG. 4 to 20 are diagrams for explaining the control procedure. KB3 ... Move range key KB4 ... Move destination key ROM ... Control memory RAM ... Memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsumi Masaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Hideshi Ichimura 3-30-2 Shimomaruko, Ota-ku, Tokyo Kya Non-Incorporated (56) Reference JP 54-56726 (JP, A) JP 54-44442 (JP, A) Information Processing Society of Japan "Electronic Computer Handbook" (SHO 41-5-25) Ohmsha , P .; 7-23 ~ 7-25

Claims (1)

[Claims] 1. A first and a second for storing document data.
In the character processing device having the data storage means, a character processing method for editing document data stored in the first data storage means based on an unused area on the first data storage means, When a partial data string of a desired arbitrary length is specified in the document data stored in the first data storage means, the specified partial data string is replaced with the first data. Transferring from the storage means to the second data storage means for storage, and adding the stored area of the transferred partial data string to the unused area in the first data storage means; Each time the transfer destination in the document data stored in the first data storage unit is designated for the partial data string stored in the second data storage unit, the first data storage unit smell An area for storing the part of the data string is reserved at a transfer destination designated by the unused area, and the part of the data string stored in the second data storage means is allocated to the reserved area. Is transferred and stored, and the secured area is deleted from the unused area in the first data storage means.