JPS6326888B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control control circuit that feeds back an output state to an input.

Conventionally, as shown in FIG. 1, in a system in which the input signal converter 3, memory 1', and output signal converter 4 are used to cause the memory 1' to perform a logic circuit operation to control equipment, the system is as shown in FIG. When the input signal X ₀ is turned on, the output Y ₀ ' is turned on, the input signal Y ₀ is turned on, and this state is maintained. The logic circuit becomes as shown in Figure 3, and the first The output Y ₀ ' of the output signal converter 4 shown in the figure is input to the input signal converter 3.
Must be externally connected to AC 100V or 200V,
Another problem was that the efficiency deteriorated because one input and one output signal converter for converting the DC 24V or 12V input and output signals to the IC signal level were used for this feedback signal.

The present invention has been provided in view of the above-mentioned points, and it is possible to program a memory with data that causes the address input and data output of a memory such as ROM or RAM to operate as the input/output of a logic circuit. Configuring a memory section in which at least one data output is fed back to an address input,
This is provided for the purpose of facilitating the construction of a control circuit that maintains that an input signal is hot.

Embodiments of the present invention will be described in detail below with reference to the drawings. In the figure, 1 is a memory such as ROM or RAM, and this memory 1 has a large number of address inputs (A ₀ to An) and data outputs (D ₀ to Dn), of which the data output D ₀ is connected to the address input A ₀ We are giving feedback to
2 is a memory section, and the data output D ₀ of the memory 1 is
This block is attached to a patterned board connected to the address input _A0 . Reference numeral 3 denotes an input signal converter that receives input from controlled equipment having different signal levels.The signal level from this input signal converter 3 is the same signal level as the signal level of the memory 1, and the output of the input signal converter 3 is They are connected to the address inputs (A ₁ to An) of the memory 1 on a one-to-one basis, respectively. Reference numeral 4 denotes an output signal converter that outputs to controlled devices having different signal levels, and the signal level on the input side of this output signal converter 4 is the same as the signal level of the data output (D ₁ to Dn) of the memory 1. , data output of output signal converter 4 and memory 1 (D ₁ to Dn)
are connected on a one-to-one basis.

Now, in the circuit shown in Figure 2, the input signal X ₀
When on, the input signal X ₁ is off, _the output Y ₀ ' is on, and even when _the input signal
and the input signal Y ₀ are OR-combined, so the input signal
The output Y ₀ ' remains on due to Y ₀ . After that, when input signal X ₁ turns on, the inverted signal of input signal X ₁ is ANDed with the OR result of input signals X ₀ and Y ₀ , so output Y ₀ ' turns off, and input signals X ₀ and Y ₀ turn off. Therefore, even if input signal X ₁ turns off again _, the AND result of the OR result of input signals X _{0 and} Y ₀ and the inverted signal of input signal Hold. If a lamp 5 is connected in parallel with this output Y' ₀ , control will be performed such that when the input signal X ₀ is turned on, the lamp 5 will turn on, and when the input signal X ₁ is turned on, the lamp 5 will turn off. be able to.

In order to perform the above operation with the circuit shown in FIG. 4, the input signals X ₀ and X ₁ shown in FIG _. Input signal X ₀ to address input
Input the input signal _X1 to _A2 . Also, as described above, the data output D ₀ of the memory 1 is connected to the address input A ₀ . Here, input the address of memory 1
A ₂ is “0” and address input A ₀ or A ₁ is “1”
and when address inputs A ₀ and A ₁ are both “1”, data outputs D ₀ and D ₁ are “1”, and for other address inputs A ₀ , A ₁ , and A ₂ , all are “0”. When data is written, the memory section 2 operates in the same way as a logic circuit as shown in FIG. The lamp 5 is connected to the output of the output signal converter 4 to which the data output D ₁ is connected. _{Here ,} if the input signal
D ₀ and D ₁ become “1” and data output of memory 1 D ₁
This causes the external lamp 5 to light up. At the same time, data output _D0 is connected to address input _A0 , so even if input signal _X0 is turned off and address input _A1 becomes "0", address input _A0 is "1", so data is output D ₀ and D ₁ remain at "1", and lamp 5 continues to light up. Next, when the input signal X ₁ turns on, the address input A ₂ becomes "1", and at this time, the external lamp 5 turns off because "0" is programmed in the data outputs D ₀ and D ₁ of the memory 1. do. After that, even if _the input signal X ₁ is turned off and _{the address input A 2 becomes} " ₀ ", the input signal 1 address input A ₀ is “0”
Then, the data outputs D ₀ and D ₁ hold “0” and the second
It operates as shown in the figure.

As described above, the present invention includes forming a memory section on a patterned substrate into blocks in which at least one data output of a preprogrammed memory is fed back to an address input of the memory, and a feedback signal is fed back to the address input of the memory. A program is written in the memory to hold the output from the at least one data output when predetermined data including the data is input, and an input signal converter input to the memory section and an output signal converter output from the memory section are written in the memory. Since the signal lines are formed in a one-to-one correspondence with each other, when controlling the output state by feedback to the input, there is no need for external connections between circuits with different signal levels as in the past. As with the present invention, the device can be efficiently controlled without using the input/output conversion section for this feedback signal, and the memory section can be formed as a block on a patterned substrate. Therefore, it is possible to easily form a memory section having a logic circuit. In addition, the circuit changes depending on the data written to the memory, and the fed-back address input becomes an AND input or
OR input, NOT input, or not used. Moreover, the number of connections to feed back to memory address input is not only one, but also has the effect of allowing multiple connections, and these data This has the advantage that it can be freely changed depending on the contents, and furthermore, it does not require a control circuit such as a clock or a signal, and the logic circuit can be constructed simply using memory. Furthermore, by writing in the memory a program that holds the output from the at least one data output when predetermined data including a feedback signal is input to the address input, the feedback signal can be input to the address input. When predetermined data including data is input, the output from the data output can be held, and therefore, for example, it is possible to configure an important holding circuit in a sequence control circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional control circuit, Figure 2 is a circuit diagram of an example of a control circuit, and Figure 3 is a circuit diagram of an example of a conventional control circuit.
4 is a circuit diagram of a control circuit according to an embodiment of the present invention, and FIG. 5 is a logic circuit diagram in FIG. 2, in which 1 is a memory, 2 is a memory section,
3 is an input signal converter, 4 is an output signal converter, A is an address input, and D is a data output.

Claims (1)

[Claims] 1. In a control circuit configured to treat address input and data output of a memory such as ROM or RAM as input and output of a logic circuit, and to feed back the output state to the input, at least one data output of a pre-programmed memory is configured. A memory portion fed back to the address input of the memory is formed as a block on a patterned substrate, and when predetermined data including a feedback signal is input to the address input, an output from the at least one data output is output. A control characterized in that a program to be held is written in the memory, and signal lines between an input signal converter input to the memory section and an output signal converter output from the memory section are formed in a one-to-one correspondence. circuit.