JPS63268663A - Thermal head substrate and manufacture thereof - Google Patents

Thermal head substrate and manufacture thereof

Info

Publication number
JPS63268663A
JPS63268663A JP10507587A JP10507587A JPS63268663A JP S63268663 A JPS63268663 A JP S63268663A JP 10507587 A JP10507587 A JP 10507587A JP 10507587 A JP10507587 A JP 10507587A JP S63268663 A JPS63268663 A JP S63268663A
Authority
JP
Japan
Prior art keywords
layer
plating
heating resistor
thermal head
base metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10507587A
Other languages
Japanese (ja)
Inventor
Choei Sugitani
杉谷 長英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP10507587A priority Critical patent/JPS63268663A/en
Publication of JPS63268663A publication Critical patent/JPS63268663A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/335Structure of thermal heads

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To lower the resistance of a conductor, improve the ununiformity of printed density, reduce etching time and obtain a high pattern accuracy, by composing an electrode conductor layer of an undercoat metallic layer provided on a heat generating resistor layer for Cu plating and a plated Cu layer provided on the undercoat metallic layer. CONSTITUTION:A common electrode body, a ground terminal and an external connection terminal part are provided by sequentially providing a plate Cu layer 41, a plated Cu layer 42 and a plated Ni layer 5 on an insulating thin film layer (Ta2O5 layer) 2 and a heat generating resistor layer 3 which are provided on a glazed alumina ceramic substrate 1. A heat generating resistor layer 6 is protected by an abrasion-resistant layer 7, and the parts exclusive of a bonding part for mounting a driving IC and an external connection terminal are protected by an insulating resin. The plated Cu layer 42 has a thickness of about 20mum, so that a difference in voltage drop based on a difference in circuit resistance is small even when a large current is passed at the time of operating a thermal head, and a uniform printed density can be ensured.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁基板上に発熱抵抗体や該発熱抵抗体に接
続する配線パターンが膜技術により形成されたサーマル
ヘッド基板およびその製造方法に関し、特にIs導体パ
ターンを有するサーマルヘッド基板およびそのIyJ造
方決方法する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a thermal head substrate in which a heating resistor and a wiring pattern connected to the heating resistor are formed on an insulating substrate by film technology, and a method for manufacturing the same. In particular, the present invention describes a thermal head substrate having an Is conductor pattern and a method for manufacturing the IyJ.

〔従来の技術〕[Conventional technology]

従来、この種のサーマルヘッド基板では、印字を行なう
場合、例えばB−4サイズ、ドツト密度8ドツト/履、
1ライン4分割印字方式のときは共通電極体に最大2O
A前後の電流を供給する必要があり、導体抵抗による電
圧降下が問題となる。
Conventionally, when printing with this type of thermal head substrate, for example, B-4 size, dot density of 8 dots/lead,
When using the 1-line 4-division printing method, maximum 2O is applied to the common electrode body.
It is necessary to supply a current around A, and voltage drop due to conductor resistance becomes a problem.

すなわら、サーマルヘッドの印字位置が電流供給点から
離れるほど発熱抵抗体に印加される電圧が低くなり発熱
量がそれだけ減少するため印字濃度が薄くなる。このよ
うな印字濃度むらを改善するため、従来のり−マルヘッ
ド基板では、共通電極体、駆動用ICグラウンド端子、
および外部接続端子に金や銀等の厚膜が用いられるが、
またはる体層を厚くしている。
In other words, the farther the printing position of the thermal head is from the current supply point, the lower the voltage applied to the heating resistor and the lower the amount of heat generated, resulting in a thinner printing density. In order to improve such print density unevenness, conventional paper head substrates have a common electrode body, a driving IC ground terminal,
And thick films such as gold and silver are used for external connection terminals,
It has thickened body layers.

第7図は前者の例の導体配置を示す部分平面図、第8図
は第7図のA−A断面矢視図である。
FIG. 7 is a partial plan view showing the conductor arrangement of the former example, and FIG. 8 is a cross-sectional view taken along the line AA in FIG. 7.

第7図に示すように発熱抵抗体21をはさんで一方に共
通電極体2o1が、他方に個別電極体202があり、発
熱抵抗体21に印字用の電力を供給する。共通電極体2
o1においてはグレーズドアルミナセラミック基゛板1
の上に金や銀等の厚lIBが形成され、さらにその上に
絶縁体層2、発熱抵抗体図3を介してAj!導体導体配
属2層9成されて、厚膜8とM導体配線層8とで電流を
導通する。
As shown in FIG. 7, there is a common electrode body 2o1 on one side of the heating resistor 21, and an individual electrode body 202 on the other side, and power for printing is supplied to the heating resistor 21. Common electrode body 2
In o1, glazed alumina ceramic substrate 1
A thick layer of gold, silver, etc. is formed on top of the insulating layer 2 and the heating resistor shown in FIG. Two conductor layers 9 are formed to conduct current between the thick film 8 and the M conductor wiring layer 8.

外部接続端子22においては金の厚膜Sがそのまま圧着
接続端子として用いられる。グラウンド端子23には駆
動用1cが搭載される。
In the external connection terminal 22, the thick gold film S is used as it is as a crimp connection terminal. A drive 1c is mounted on the ground terminal 23.

(発明が解決しようとする問題点) 、上述した従来のサーマルヘッド基板は、前者の厚膜を
用いるものは、金や銀等の厚膜を用いているので、基板
そのもののイニシャルコストが高く、また、厚膜上蔽後
工稈のエツチング時に厚膜を保護するための絶縁体層が
形成されているので、共通電極体と駆動用ICグラウン
ド端子ではそのままでは厚膜と配線導体層との間の電気
の導通が得られず、別途の手段により厚膜と配線導体層
とを接続する必要があり、さらに経時的に厚膜が酸化す
るため信頼性が低いという欠点がある。
(Problems to be Solved by the Invention) In the conventional thermal head substrates described above, the former uses a thick film of gold, silver, etc., so the initial cost of the substrate itself is high; In addition, since an insulating layer is formed to protect the thick film during etching of the culm after covering the thick film, the common electrode body and driving IC ground terminal cannot be directly connected between the thick film and the wiring conductor layer. Electrical continuity cannot be obtained, it is necessary to connect the thick film and the wiring conductor layer by a separate means, and furthermore, the thick film oxidizes over time, resulting in low reliability.

また、後者の導体層を厚くする方法は、成膜装置の設備
能力上からも非経済的であり、また、高いドツト密度が
要求きれる場合、パターン形成のときの導体層エツチン
グが膜厚が厚いためサイドエツチングが激しくて所望の
パターンが冑られないという欠点がある。
In addition, the latter method of increasing the thickness of the conductor layer is uneconomical in terms of the equipment capacity of the film forming equipment, and if a high dot density is required, the conductor layer must be etched to a large thickness during pattern formation. Therefore, side etching is severe and the desired pattern cannot be etched.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のサーマルヘッド基板は、その電極導電体層が、
発熱抵抗体図上に成膜されたCuめっきをするための下
地金1iAW1と、該下地金1!!層上に形成されたC
uめっぎ層とより構成されている。
In the thermal head substrate of the present invention, the electrode conductor layer is
The base metal 1iAW1 for Cu plating formed on the heating resistor diagram, and the base metal 1! ! C formed on the layer
It is composed of a U-metal layer.

また、その製造方法のうち特許請求の範囲第2項に記載
の方法は、前記発熱抵抗体図を形成した債、その上面に
スパッタリング法によりCuめっき川下地金R層を形成
する工程と、次に、前記発熱抵抗体図およ゛びCuめっ
き用下地金属層に配線パターンを形成後、該パターンの
うち、発熱抵抗体となるべき部分をホトレジスト等でマ
スクし、共通電極体となるべき部分を電流供給源として
、電解Cuめっき法によりCuめっき用下地金属層上に
所定の厚さまでCuめっきを行う工程を含む。
Further, among the manufacturing methods, the method described in claim 2 includes the steps of: forming a Cu-plated base metal R layer on the bond on which the heat generating resistor diagram is formed by sputtering method; After forming a wiring pattern on the heating resistor diagram and the base metal layer for Cu plating, mask the part of the pattern that will become the heating resistor with photoresist or the like, and mask the part that will become the common electrode body. The method includes a step of plating Cu to a predetermined thickness on a base metal layer for Cu plating by using an electrolytic Cu plating method using as a current supply source.

また、製造方法のうち、特許請求の範囲第3項に記載の
方法は、前記発熱抵抗体図を形成した後、その上面にス
パッタリング法によりCuめっき川下地金a層を形成す
る工程と、次に、前記発熱抵抗体図およびCuめっき川
下地金IK居に配線パターンを形成後、基板全面にCu
めっきを施し、さらに、共通電極体となるべき部分以外
の部分にマスクを施して、共通電極体となるべき部分に
Cuめっきを施す工程と、次に、前記マスクを除去した
後、基板全面にNiめつきを施す工程と、次に、発熱抵
抗体となるべき部分のNiめつき層とCLIめつき層を
、エツチング法により、すべて除去する工程を含んでい
る。
Further, among the manufacturing methods, the method according to claim 3 includes the steps of forming the heating resistor diagram and then forming a Cu-plated base metal a layer on the upper surface thereof by sputtering method; After forming a wiring pattern on the heating resistor diagram and the Cu-plated base metal IK layer, Cu is applied to the entire surface of the board.
Plating is applied, and further, a mask is applied to the parts other than the part to become the common electrode body, and Cu plating is applied to the part to be the common electrode body. Next, after removing the mask, the entire surface of the substrate is The process includes a step of applying Ni plating, and then a step of completely removing the Ni plating layer and CLI plating layer in the portion that will become the heating resistor by etching.

〔作用〕[Effect]

このように、電極体をすべてCuめつき層で構成し、か
つその厚さを部分毎に所定のTi流密度に応じる厚みと
することにより、印字部1夷むらが改善される。
In this way, by forming the entire electrode body with a Cu plating layer and setting the thickness of each portion to a thickness that corresponds to a predetermined Ti flow density, unevenness in printed portion 1 can be improved.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明のサーマルヘッド基板の一実施例の断面
図、第2図ないし第5図は第1図のサーマルヘッド基板
の製造方法のうち、特許請求の範囲第2項の一実施例を
工程順に説明するための仕l)基板断面図である。
FIG. 1 is a cross-sectional view of an embodiment of the thermal head substrate of the present invention, and FIGS. 2 to 5 are an embodiment of the method of manufacturing the thermal head substrate of FIG. 1 according to claim 2. FIG. 1) is a cross-sectional view of a substrate for explaining the step-by-step process.

次に、第2図ないし第5図について製造工程を工程順に
説明する。
Next, the manufacturing process will be explained in the order of steps with reference to FIGS. 2 to 5.

(1)下地処理と発熱抵抗体図および下層導体層の成膜
工程(第2図) グレーズドアルミナセラミック基板1上のグレーズ層を
エツチング工程のとき保護するための絶縁i11層(T
a205 li! ) 2を約3000転成にスパッタ
リング法により成膜し、その上に発熱抵抗体図3を形成
した後、さらにCu導体11!41を同様にスパッタリ
ング法により約数100人厚転成膜して下層導体層とす
る。
(1) Base treatment, heating resistor diagram, and lower conductor layer film formation process (Figure 2) An insulating i11 layer (T
a205 li! ) 2 was formed into a film with a thickness of about 3,000 layers by sputtering, and after forming the heating resistor shown in FIG. Use as a conductor layer.

(2)導体配線パターン形成工程A(第3図)次に、C
u導体B41に対し、公知のホトレジスト処理技術によ
り沃素・沃化カリウムのエッチャントを用いてエツチン
グを施し、続いて発熱抵抗体図3に対して同様に、フッ
R−硝酸系のエッチ11ントを用いてエツチングを施し
て配線パターンを形成する。
(2) Conductor wiring pattern forming step A (Fig. 3) Next, C
The u-conductor B41 is etched using an iodine/potassium iodide etchant using a known photoresist processing technique, and then the heating resistor shown in FIG. Then etching is performed to form a wiring pattern.

一般にCu導体層は、エツチングの際、サイドエツチン
グが激しくてパターン精度が悪いが、本実施例の場合、
Cu導体層の厚さは数100〜1000人程度であり、
エツチング時間が短いためサイドエツチング量はわずか
で良好なパターン精度が得られる。
Generally, when etching a Cu conductor layer, side etching is severe and pattern accuracy is poor, but in this example,
The thickness of the Cu conductor layer is about several 100 to 1000 layers,
Since the etching time is short, the amount of side etching is small and good pattern accuracy can be obtained.

(3)導体配線パターン形成工Pi!B(第4図)次に
、同様のホトレジスト処理技術により発熱抵抗体部分の
Cu39体層41をエツチングして発熱抵抗体6を形成
する。
(3) Conductor wiring pattern forming work Pi! B (FIG. 4) Next, the Cu39 layer 41 in the heating resistor portion is etched using the same photoresist processing technique to form the heating resistor 6.

(4)電極体形成工程(第5図) 次に、発熱抵抗体6をホトレジスト等でマスキングし、
cu、1体層41の共通電極体部を電流供給源として、
公知の電解Cuめっき法によりCu導体層41上にCu
めつき層42を共通電極体部で約20*)1になるよう
に施す。この場合、Cu導体層41のうちの個別電極体
部では、共通電極体部との間の発熱抵抗体が存在するた
め、Cuめつぎ層42厚さは数1000人〜数趨となる
。さらにその上に、Cuの酸化を防止する目的でNiめ
つき層5(約1000〜2000人)を施すことにより
上層導体層を形成する。
(4) Electrode body forming step (Fig. 5) Next, the heating resistor 6 is masked with photoresist or the like,
cu, the common electrode body of the single body layer 41 as a current supply source,
Cu is deposited on the Cu conductor layer 41 by a known electrolytic Cu plating method.
A plating layer 42 is applied to the common electrode body in an amount of about 20*)1. In this case, since there is a heating resistor between the individual electrode body part of the Cu conductor layer 41 and the common electrode body part, the thickness of the Cu abutment layer 42 ranges from several thousand layers to several thousand. Furthermore, an upper conductor layer is formed by applying a Ni plating layer 5 (approximately 1000 to 2000 layers) for the purpose of preventing oxidation of Cu.

(5)仕上工程(第1図) 次に、ICと個別電極体との接続が、ハンダバンプ接続
で、かつ外部接続端子部の端子接続方法が半田付の場合
は、上述した工程で目的に適合した構成となり得るが、
ICと個別電極体との接続がワイヤーボンディング法で
あったり外部端子の接続方法が圧着である場合は、該当
部分の阻めっぎM5上にAuめっきを施す。この後、発
熱抵抗体6を耐摩耗117でカバーし、IC搭載のため
のボンディング部分と外部接続端子を除いた部分を絶縁
樹脂(不図示)でコーティングすれば第1図に示す所望
のサーマルヘッド基板ができあがる。なお、本実施例に
おいては、下層導体層はCuでなくともよ(、Cuめっ
きされやすい金属であればよい。
(5) Finishing process (Figure 1) Next, if the connection between the IC and the individual electrode body is a solder bump connection, and the terminal connection method of the external connection terminal section is soldering, the above process will meet the purpose. However,
If the IC and the individual electrode body are connected by wire bonding or the external terminal is connected by crimp, Au plating is applied on the blocking plate M5 of the corresponding part. After that, the heating resistor 6 is covered with a wear-resistant material 117, and the parts other than the bonding part for mounting the IC and the external connection terminals are coated with an insulating resin (not shown) to form the desired thermal head as shown in Fig. 1. The board is completed. Note that in this embodiment, the lower conductor layer does not need to be made of Cu (it may be any metal that is easily plated with Cu).

第6図は本発明のサーマルヘッド基板の製造方法のうち
の特許請求の範囲第3項の一実施例を示す図である。
FIG. 6 is a diagram showing an embodiment of claim 3 of the method for manufacturing a thermal head substrate of the present invention.

上述した実施例の工程(2)(第3図)の次に、Cuめ
っき層42を基板全面に1〜3趨程度施し、さらに共通
電極体部以外の部分をマスキングし、共通電極体部にC
uめつきを20伽程度形成する(第6図)。次にマスキ
ングを剥離し、基板金部に限めっきを施し、さらに発熱
抵抗体6の部分の限層とCu13をエツチングして除去
して第5図に示す構成とする。
Next to step (2) (FIG. 3) of the above-mentioned embodiment, a Cu plating layer 42 is applied in one to three layers over the entire surface of the substrate, and the parts other than the common electrode body are masked, and the common electrode body is coated with a Cu plating layer 42. C
Form about 20 U marks (Figure 6). Next, the masking is removed, limited plating is applied to the metal portion of the substrate, and furthermore, the limited layer and Cu 13 in the portion of the heating resistor 6 are etched and removed, resulting in the structure shown in FIG.

前実施例で−は共通電極体部を電流供給源どし、個別電
極体部には、発熱抵抗体6を介してCuめっきしている
が、発熱抵抗体6の抵抗値により個別stm体上のCu
めつき11542の厚さは変化し、抵抗値が高いと個別
電極体には全くめつきされない場合もありうる。しかし
本実施例では発熱抵抗体6を形成する前にCuめつきを
行うので個別電極体上のCuめつき厚を自由にiqmで
きるという利点を右している。
In the previous embodiment, the common electrode body is used as the current supply source, and the individual electrode bodies are plated with Cu via the heat generating resistor 6. However, depending on the resistance value of the heat generating resistor 6, of Cu
The thickness of the plating 11542 varies, and if the resistance is high, the individual electrode body may not be plated at all. However, in this embodiment, since Cu plating is performed before forming the heating resistor 6, there is an advantage that the Cu plating thickness on the individual electrode bodies can be freely adjusted in iqm.

次に、上述した2つの実施例のいずれかにより製造され
た本発明のサーマルヘッド基板の一実施例を第1図を参
照して説明する。
Next, an embodiment of the thermal head substrate of the present invention manufactured by either of the above two embodiments will be described with reference to FIG.

本実施例は上述した製造方法より明らかなように、共通
電極体とグラウンド端子および外部接続端子部分を、グ
レーズドアルミナセラミック基板1の上に形成された絶
縁性1膜II (TazOs層)2、発熱抵抗体図3の
上に、Cuめつぎ層41とCuめっきlll!42とN
iめつき層5を順次めっきすることにより、それぞれ形
成したものである。なお、発熱抵抗体6は耐摩耗M7で
、また駆動用IC搭載のためのボンディング部分と外部
接続端子を除く部分は絶縁樹脂で、それぞれ保護されて
いる。このように形成されたCuめっき層42は約20
鳩の厚みを有しているため、サーマルヘッド動作時に大
電流が流れても回路抵抗差に基づ(電圧降下差が小さく
て、印字*r*むらを防止することができる。
As is clear from the manufacturing method described above, in this embodiment, the common electrode body, the ground terminal, and the external connection terminal portion are connected to an insulating film II (TazOs layer) 2 formed on a glazed alumina ceramic substrate 1, and a heat generating layer. On top of the resistor shown in Figure 3, there is a Cu patch layer 41 and Cu plating! 42 and N
These are formed by sequentially plating the i-plated layers 5. The heating resistor 6 is made of wear-resistant M7, and the parts other than the bonding part for mounting the driving IC and the external connection terminals are protected by insulating resin. The Cu plating layer 42 thus formed has a thickness of about 20
Because it has the same thickness, even if a large current flows during the operation of the thermal head, the difference in voltage drop is small based on the difference in circuit resistance, and printing *r* unevenness can be prevented.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、電極導電体層を2層構造
とするため、まずCuめっきされやすい下地金属層を発
熱抵抗体図上に積層し、次にその上に電界Cuめっきを
施して上部のCuめっき層を形成したもので、共通導体
部等の比較的大きな電流が流れて導体抵抗による電圧降
下が問題となる部分にCuめっきを厚く施すことにより
、導体抵抗を下げ印?園度むらを改善することができ、
またエツチング0IIIが短いため高いパターン11度
を得ることができる効果がある。
As explained above, in the present invention, in order to make the electrode conductor layer have a two-layer structure, first a base metal layer that is easily plated with Cu is laminated on the heating resistor diagram, and then electric field Cu plating is applied thereon. A Cu plating layer is formed on the upper part, and the conductor resistance is lowered by applying thick Cu plating to areas such as the common conductor where a relatively large current flows and voltage drop due to conductor resistance is a problem. It is possible to improve the unevenness of the garden temperature,
Furthermore, since the etching 0III is short, there is an effect that a high pattern of 11 degrees can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のサーマルヘッド基板の一実施例の断面
図、第2図ないし第5図は第1図のサーマルヘッド基板
の製造方法のうち特許請求の範囲(2)項の一実施例を
工程順に説明するための仕掛基板断面図、第6図は同様
に、特許請求の範囲(3)項の一実施例を説明するため
−の仕掛基板断面図、第7図はサーマルヘッド基板の従
来例の導体配置を示す部分平面図、第8図は第7図のA
−A断面矢視図である。 1・・・グレーズドアルミナセラミック基板、2・・・
絶縁性薄膜層、 3・・・発熱抵抗体図、 41・・・Cu導体層、。 42・・・Cuめつき層、 5・・・Niめつき隅、 6・・・発熱抵抗体、 7・・・耐摩耗層。 第1図 第2図 第3図 第4図 第5図 第7図
FIG. 1 is a sectional view of an embodiment of the thermal head substrate of the present invention, and FIGS. 2 to 5 are an embodiment of the method of manufacturing the thermal head substrate of FIG. 1 in claim (2). Similarly, FIG. 6 is a cross-sectional view of the in-process board for explaining an embodiment of claim (3), and FIG. 7 is a cross-sectional view of the in-process board for explaining the process order. A partial plan view showing the conductor arrangement of the conventional example, FIG. 8 is A of FIG.
-A cross-sectional view taken along arrows. 1... Glazed alumina ceramic substrate, 2...
Insulating thin film layer, 3... Heat generating resistor diagram, 41... Cu conductor layer. 42...Cu plating layer, 5...Ni plating corner, 6...heating resistor, 7...wear resistant layer. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7

Claims (1)

【特許請求の範囲】 1、絶縁基板上に積層された発熱抵抗体層および電極導
電体層に配線パターンが形成されたサーマルヘッド基板
において、 前記電極導電体層が、前記発熱抵坑体層上に成膜された
Cuめっきをするための下地金属層と、該下地金属層上
に形成されたCuめっき層とよりなることを特徴とする
サーマルヘッド基板。 2、絶縁基板上に積層された発熱抵抗体図および電極導
電体層に配線パターンが形成され、前記電極導電体層が
、前記発熱抵抗体層上に成膜されたCuめっきをするた
めの下地金属層と、該下地金属層上に形成されたCuめ
っき層とよりなるサーマルヘッド基板の製造方法におい
て、 前記発熱抵抗体層を形成した後、その上面にスパッタリ
ング法によりCuめっき用下地金属層を形成する工程と
、 次に、前記発熱抵抗体層およびCuめっき用下地金属層
に配線パターンを形成後、該パターンのうち、発熱抵抗
体となるべき部分をホトレジスト等でマスクし、共通電
極体となるべき部分を電流供給源として、電解Cuめっ
き法によりCuめっき用下地金属層上に所定の厚さまで
Cuめっきを行う工程を含むことを特徴とするサーマル
ヘッド基板の製造方法。 3、絶縁基板上に積層された発熱抵抗体層および電極導
電体層に配線パターンが形成され、前記電極導電体層が
、前記発熱抵抗体層上に成膜されたCuめっきをするた
めの下地金属層と、該下地金属層上に形成されたCuめ
っき層とよりなるサーマルヘッド基板の製造方法におい
て、 前記発熱抵抗体層を形成した後、その上面にスパッタリ
ング法によりCuめっき用下地金属層を形成する工程と
、 次に、前記発熱抵抗体層およびCuめっき用下地金属層
に配線パターンを形成後、基板全面にCuめっきを施し
、さらに、共通電極体となるべき部分以外の部分にマス
クを施して、共通電極体となるべき部分にCuめっきを
施す工程と、 次に、前記マスクを除去した後、基板全面にNiめつき
を施す工程と、 次に、発熱抵抗体となるべき部分のNiめっき層とCu
めっき層を、エッチング法により、すべて除除去する工
程を含むことを特徴とするサーマルヘッド基板の製造方
法。
[Scope of Claims] 1. A thermal head substrate in which a wiring pattern is formed on a heating resistor layer and an electrode conductor layer laminated on an insulating substrate, wherein the electrode conductor layer is formed on the heating resistor layer. 1. A thermal head substrate comprising: a base metal layer for Cu plating formed on the base metal layer; and a Cu plating layer formed on the base metal layer. 2. A wiring pattern is formed on a heating resistor diagram and an electrode conductor layer laminated on an insulating substrate, and the electrode conductor layer is a base for Cu plating formed on the heating resistor layer. In a method for manufacturing a thermal head substrate comprising a metal layer and a Cu plating layer formed on the base metal layer, after forming the heating resistor layer, a base metal layer for Cu plating is formed on the upper surface by sputtering. Next, after forming a wiring pattern on the heat generating resistor layer and the base metal layer for Cu plating, the part of the pattern that should become the heat generating resistor is masked with photoresist or the like, and a common electrode body is formed. 1. A method for manufacturing a thermal head substrate, comprising the step of plating Cu to a predetermined thickness on a base metal layer for Cu plating by electrolytic Cu plating using the desired portion as a current supply source. 3. A wiring pattern is formed on the heating resistor layer and the electrode conductor layer laminated on the insulating substrate, and the electrode conductor layer is a base for Cu plating formed on the heating resistor layer. In a method for manufacturing a thermal head substrate comprising a metal layer and a Cu plating layer formed on the base metal layer, after forming the heating resistor layer, a base metal layer for Cu plating is formed on the upper surface by sputtering. Next, after forming a wiring pattern on the heating resistor layer and the base metal layer for Cu plating, Cu plating is applied to the entire surface of the substrate, and further, a mask is applied to the parts other than the part to become the common electrode body. Then, after removing the mask, applying Ni plating to the entire surface of the substrate, and then applying Cu plating to the part to become the heating resistor. Ni plating layer and Cu
A method for manufacturing a thermal head substrate, comprising the step of completely removing a plating layer by an etching method.
JP10507587A 1987-04-27 1987-04-27 Thermal head substrate and manufacture thereof Pending JPS63268663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10507587A JPS63268663A (en) 1987-04-27 1987-04-27 Thermal head substrate and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10507587A JPS63268663A (en) 1987-04-27 1987-04-27 Thermal head substrate and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS63268663A true JPS63268663A (en) 1988-11-07

Family

ID=14397820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10507587A Pending JPS63268663A (en) 1987-04-27 1987-04-27 Thermal head substrate and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS63268663A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008433A (en) * 1988-05-18 1991-04-16 Marion Laboratories, Inc. 2-hydroxy-3-(4-methoxyphenyl)-3-(2-aminophenylthio)propionic acid, 8'-phenylmenthyl ester, especially for diltiazem
JPH0390169U (en) * 1989-12-26 1991-09-13

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008433A (en) * 1988-05-18 1991-04-16 Marion Laboratories, Inc. 2-hydroxy-3-(4-methoxyphenyl)-3-(2-aminophenylthio)propionic acid, 8'-phenylmenthyl ester, especially for diltiazem
JPH0390169U (en) * 1989-12-26 1991-09-13

Similar Documents

Publication Publication Date Title
US4446355A (en) Crossover construction of thermal-head and method of manufacturing same
JP2554358B2 (en) Wiring board and method for manufacturing wiring board
JPS63268663A (en) Thermal head substrate and manufacture thereof
JP2717200B2 (en) Method of forming overlay plating on electronic component mounting substrate
JPH03189170A (en) Thermal head and its manufacture
JP3042682B2 (en) Thermal head and method of manufacturing thermal head
JP3172623B2 (en) Thermal head
JPH0439064A (en) Thermal head
JPH04278542A (en) Semiconductor device and manufacture thereof
JPS6347164A (en) Substrate for thermal print head and manufacture therefor
JPH02179765A (en) Thermal head substrate
JPS63128954A (en) Thermal head substrate and manufacture thereof
JP2616571B2 (en) Method for manufacturing semiconductor device
JPS61182964A (en) Thermal head
JPH01275068A (en) Thermal head substrate
JPH05229160A (en) Thermal head
JP3323140B2 (en) Chip resistor
JP2582999Y2 (en) Thermal head
JPH01103458A (en) Thick-film type thermal head
JPS6394861A (en) Thermal head and manufacture thereof
JP3180980B2 (en) Manufacturing method of thermal head
JPH03124458A (en) Printing head
JPH0637152A (en) Manufacture of semiconductor device and semiconductor device
JPH08255969A (en) Printed-circuit board device
JPH0230554A (en) Thermal head and production thereof