JPS63268263A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63268263A JPS63268263A JP10241187A JP10241187A JPS63268263A JP S63268263 A JPS63268263 A JP S63268263A JP 10241187 A JP10241187 A JP 10241187A JP 10241187 A JP10241187 A JP 10241187A JP S63268263 A JPS63268263 A JP S63268263A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- resistance
- oxide film
- semiconductor substrate
- impurity layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 238000009966 trimming Methods 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000000992 sputter etching Methods 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に高い抵抗を有する半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having high resistance.
従来、半導体装置に使用している高抵抗は、半導体基板
と導電型の異なる不純物をイオン注入もしくは熱拡散を
使って表面に拡散し形成した不純物領域や多結晶半導体
層に不純物を導入したもの等からなる。Conventionally, high resistances used in semiconductor devices are produced by impurity regions formed by diffusing impurities of a conductivity type different from that of the semiconductor substrate into the surface using ion implantation or thermal diffusion, or by introducing impurities into a polycrystalline semiconductor layer. Consisting of
＝１−
〔発明が解決しようとする問題点〕
上述した従来の半導体装置の高抵抗は、一方ではイオン
注入したりあるいは熱拡散して形成するが、その時の抵
抗値は〔（抵抗領域のシート抵抗ρ５）×（抵抗領域の
長さ）／（抵抗領域の幅）〕で得られるので、高抵抗を
高精度（例えば±３０％以内）で安定して得る為には抵
抗幅をあまり狭くできないため広い面積が必要となり、
集積度の向上の大きな障害となっていた。=1- [Problem to be solved by the invention] The high resistance of the conventional semiconductor device described above is formed by ion implantation or thermal diffusion, but the resistance value at that time is Resistance ρ5) × (length of resistance region) / (width of resistance region)] Therefore, in order to stably obtain high resistance with high precision (for example, within ±30%), the resistance width cannot be made too narrow. Therefore, a large area is required,
This was a major obstacle to increasing the degree of integration.
他方、不純物を含んだ多結晶半導体層を高抵抗とする場
合にも、上述の拡散による高抵抗よりも比較的小さな面
積にはできるものの、抵抗値の精度は非常に悪く±５０
％〜±２００％以上にもばらついて高精度の高抵抗には
使えないという欠点がある。On the other hand, even if a polycrystalline semiconductor layer containing impurities is made to have a high resistance, the area can be made relatively smaller than the above-mentioned high resistance due to diffusion, but the accuracy of the resistance value is very poor and is within ±50
It has the disadvantage that it cannot be used for high-precision, high-resistance applications because it varies by more than % to ±200%.
本発明の半導体装置は、−導電型の半導体基板表面に設
けた溝の表面に形成した反対導電型の不純物層からなる
抵抗を有して成る。The semiconductor device of the present invention includes a resistor made of an impurity layer of an opposite conductivity type formed on the surface of a groove provided in a semiconductor substrate surface of a -conductivity type.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
この実施例は、Ｎ型の半導体基板１表面に形成した溝表
面にＰ型の不純物層からなる抵抗領域２を設け、溝表面
に酸化膜３を設けた後溝を充填するノンドープの多結晶
シリコン層４を設け、この溝に直角に交わる他のトリミ
ング用溝を設け、半導体基板１表面にＰ型の不純物層か
らなるコンタクト領域５を設け、更にコンタクト用窓を
有する酸化膜６で覆いその上にＡＪ？配線８ａ及び８ｂ
を設けている。In this embodiment, a resistance region 2 made of a P-type impurity layer is provided on the surface of a groove formed on the surface of an N-type semiconductor substrate 1, an oxide film 3 is provided on the groove surface, and then non-doped polycrystalline silicon is used to fill the groove. A layer 4 is provided, another trimming groove perpendicular to this groove is provided, a contact region 5 made of a P-type impurity layer is provided on the surface of the semiconductor substrate 1, and further covered with an oxide film 6 having a contact window. ni AJ? Wiring 8a and 8b
has been established.
第２図（ａ）及び（ｂ）はそれぞれ本発明の半導体装置
の製造方法の一実施例を説明するための平面図及びＡ−
Ａ′線断面図である。FIGS. 2(a) and 2(b) are a plan view and a-
It is a sectional view taken along the line A'.
この実施例は、先ず、Ｎ型の半導体基板１表面に溝を形
成し溝表面に熱拡散によりＰ型の不純物層からなる抵抗
領域２を形成する。次に、溝表面に酸化膜３を形成した
後溝内をノンドープの多結晶シリコン層４で充填する。In this embodiment, first, a groove is formed on the surface of an N-type semiconductor substrate 1, and a resistance region 2 made of a P-type impurity layer is formed on the groove surface by thermal diffusion. Next, after forming an oxide film 3 on the groove surface, the inside of the groove is filled with a non-doped polycrystalline silicon layer 4.
次に、表面に抵抗領域２を形成した溝に直交するトリミ
ング溝７をイオンエツチングにより形成し抵抗値を所定
の値にトリミングした後トリミング溝７表面に酸化膜を
形成すると共にノンドープの多結晶シリコン層で充填す
る。次に、Ｐ型の不純物層からなるコンタクト領域５を
半導体基板１表面に形成した後酸化膜６で覆い更にコン
タクト用窓を開口する。最後に、Ａ！配線８ａ及び８ｂ
を形成すれば、第１図に示す半導体装置ができる。Next, a trimming groove 7 perpendicular to the groove in which the resistance region 2 was formed on the surface is formed by ion etching, and after trimming the resistance value to a predetermined value, an oxide film is formed on the surface of the trimming groove 7, and non-doped polycrystalline silicon is formed. Fill with layers. Next, a contact region 5 made of a P-type impurity layer is formed on the surface of the semiconductor substrate 1, and then covered with an oxide film 6 and a contact window is opened. Finally, A! Wiring 8a and 8b
By forming this, the semiconductor device shown in FIG. 1 can be obtained.
第３図は本発明の第２の実施例の断面図である。FIG. 3 is a sectional view of a second embodiment of the invention.
この実施例ば面方位（１００）のＮ型の半導体基板１′
表面に結晶軸依存性の異方性エツチング等により形成し
なＶ形の溝を設け、溝側面にＰ型の不純物層からなる抵
抗領域２′を設け、溝側面に酸化膜３′を形成した後溝
を充填するノンドープの多結晶シリコン層４′を設け、
第１の実施例同様、トリミング用溝を形成して抵抗値を
所定の値にした後トリミング用溝表面を酸化膜で覆いか
つノンドープの多結晶シリコン層で充填し、更にＰ型の
コンタクト領域５′、コンタクト用窓を備えた酸化膜６
′及びＡ！配線８ｂ’を順次設けている。In this example, an N-type semiconductor substrate 1' with a plane orientation (100)
A V-shaped groove was formed on the surface by crystal axis-dependent anisotropic etching, a resistance region 2' made of a P-type impurity layer was formed on the side surface of the groove, and an oxide film 3' was formed on the side surface of the groove. A non-doped polycrystalline silicon layer 4' is provided to fill the rear groove,
As in the first embodiment, after forming a trimming groove and setting the resistance value to a predetermined value, the surface of the trimming groove is covered with an oxide film and filled with a non-doped polycrystalline silicon layer, and then a P-type contact region 5 is formed. ', oxide film 6 with contact window
' and A! Wiring lines 8b' are sequentially provided.
以上説明したように本発明は、−導電型の半導体基板表
面に形成した溝表面の反対導電型の不純物層を抵抗領域
とすることにより、従来技術による抵抗よりも面積が１
／２〜１／４程度と小さくできると共に高抵抗の精度が
従来±５０％〜±２００％であったものが±３０％程度
に改善できるという効果がある。As explained above, the present invention has an area smaller than that of the conventional resistor by using the impurity layer of the opposite conductivity type on the surface of the groove formed on the surface of the -conductivity type semiconductor substrate as the resistance region.
It has the effect that it can be made as small as about /2 to 1/4, and that the precision of high resistance can be improved from the conventional ±50% to ±200% to about ±30%.
また、本発明による抵抗を直列に接続することにより、
従来拡散抵抗では不可能であったＩＭΩ前後の超高抵抗
が実現できて、集積回路の性能が飛躍的に向上するとい
う効果もある。Moreover, by connecting the resistors according to the present invention in series,
It is possible to achieve an extremely high resistance of around IMΩ, which was impossible with conventional diffused resistors, and has the effect of dramatically improving the performance of integrated circuits.
第１図は本発明の第１の実施例の断面図、第２図（ａ）
及び（ｂ）は本発明の半導体装置の製＝５−
遣方法の一実施例を説明するための平面図及びＡ−Ａ’
線断面図、第３図は本発明の第２の実施例の断面図であ
る。
１．１′・・・半導体基板、２，２′・・・抵抗領域、
３．３′・・・酸化膜、４．４′・・・多結晶シリコン
層、５．５′・・・コンタクト領域、６．６′・・・酸
化膜、７−）リミング用溝、８ａ、８ａ’ 、 ８ｂ。
８ｂ’・・・Ａ！配線。
−６＝Fig. 1 is a sectional view of the first embodiment of the present invention, Fig. 2(a)
and (b) is a plan view and A-A' for explaining one embodiment of the manufacturing method of the semiconductor device of the present invention.
Line sectional view, FIG. 3 is a sectional view of a second embodiment of the present invention. 1.1'...Semiconductor substrate, 2,2'...Resistance region,
3.3'... Oxide film, 4.4'... Polycrystalline silicon layer, 5.5'... Contact region, 6.6'... Oxide film, 7-) Rimming groove, 8a , 8a', 8b. 8b'...A! wiring. −6=
Claims (1)
反対導電型の不純物層からなる抵抗を有する半導体装置
。A semiconductor device having a resistance made of an impurity layer of an opposite conductivity type formed on the surface of a groove provided in the surface of a semiconductor substrate of one conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10241187A JPS63268263A (en) | 1987-04-24 | 1987-04-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10241187A JPS63268263A (en) | 1987-04-24 | 1987-04-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63268263A true JPS63268263A (en) | 1988-11-04 |
Family
ID=14326697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10241187A Pending JPS63268263A (en) | 1987-04-24 | 1987-04-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63268263A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100621764B1 (en) * | 2000-07-05 | 2006-09-07 | 삼성전자주식회사 | method for forming load resistors of the semiconductor device |
| DE10112783B4 (en) * | 2000-03-16 | 2011-02-24 | DENSO CORPORATION, Kariya-shi | Semiconductor device having a power MOSFET and a resistance element |
-
1987
- 1987-04-24 JP JP10241187A patent/JPS63268263A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10112783B4 (en) * | 2000-03-16 | 2011-02-24 | DENSO CORPORATION, Kariya-shi | Semiconductor device having a power MOSFET and a resistance element |
| KR100621764B1 (en) * | 2000-07-05 | 2006-09-07 | 삼성전자주식회사 | method for forming load resistors of the semiconductor device |
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