JPS63268015A - Power source and driving circuit for computer - Google Patents

Abstract

PURPOSE:To decrease the power consumption by actuating a clock oscillating circuit of a high frequency only in a fast processing state. CONSTITUTION:When a presetting state of a resetting circuit 8 is released, a crystal oscillator 22 is actuated. Thus the circuit 8 counts the prescribed number of pulses of the oscillator 22 and sets the output of the oscillator 22 at L. Thus the resetting state of a clock selecting circuit 7 is released and a clock signal of a low frequency is sent to a CPU 9 from a NAND gate 5 as a system clock. Simultaneously, a clock signal of an L level is also applied to a reset input R of the CPU 9. Thus the CPU 9 is ready to start and a computer is actuated by a system clock of a low frequency. In a fast processing state a crystal oscillator 23 starts its oscillation for output of a signal of a high frequency. Then the oscillator 23 is driven again at a low frequency when a fast processing action is over.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a microcomputer having a plurality of oscillation circuits.

<Prior art> Conventionally, in order to minimize power consumption during processing in a microcomputer, a high voltage is applied to the CPU while the CPU of the microcomputer is performing high-speed processing such as data processing, and By driving at a high frequency and applying a low voltage to the CPU in situations that do not require high-speed processing such as input state detection, and driving at a low frequency, power consumption during low-speed processing is reduced. For example, a similar method has been proposed in Japanese Patent Application Laid-Open No. 60-207916.

However, in order to reduce the frequency to a low frequency, this conventional device divides the output from a high frequency oscillator using a microcomputer built-in frequency divider to form a low frequency signal. The oscillator itself operates at a high frequency, so it is necessary to continue supplying a high voltage even during low-speed processing as well as during high-speed processing, and the power consumption of this oscillator is There are also major drawbacks during processing.

On the other hand, in recent years, a microcomputer has been proposed that has multiple oscillators that generate low-frequency and high-frequency outputs, and when operating at a low frequency drive (for example, 32KH2), this computer uses a low voltage (for example, 3V). ) to a high voltage (for example, 5 V), and is configured to be driven at a high voltage when driving at a high frequency (for example, 8 MHz).

Therefore, in this type of computer, an oscillator that outputs a low-frequency signal can be selected during low-speed processing, and the oscillator can be driven with a low voltage, thereby reducing power consumption in the oscillator during low-speed processing.

However, this type of computer is configured so that all oscillators are activated upon reset, and the mode is shifted to high-frequency drive mode after the reset is released. The structure is such that a high voltage is applied to the oscillator while the oscillator is held in that state, and low frequency driving at low voltage is not possible from the initial stage of driving.

Purpose of the present invention: The present invention improves the conventional example, operates only a low frequency oscillation circuit during reset, and operates the microcomputer at a low frequency and at a low voltage even after the reset is released. The purpose is to provide a computer that consumes less current during reset.

<Embodiment> FIG. 1 is a circuit diagram showing an embodiment of a computer of the present invention. In the figure, reference numerals 1 to 11 indicate circuit units constituting a microcomputer-A. 1 is a D-type flip-flop (hereinafter abbreviated as DF/F), and its output is 2, which will be described later.
1 power supply circuit. 2 and 3 are DF/F,
Its outputs are connected to the input terminals of Nandt gates 5 and 6, respectively.

4 is a DF/F, the output of which is connected to the select terminal of the system clock selection circuit 7.

5.6 is a Nandt gate, and crystal oscillators 22 and 23, which will be described later, are connected to its input terminal and output terminal, respectively, to form an oscillation circuit. On/off is controlled.

Reference numeral 7 denotes a system clock selection circuit which selects the output of the Nant gate 5 or the Nant gate 6 according to the output of the DF/F 4 and outputs it as a system clock.

8 is a reset circuit for setting the circuit of microcomputer-A to an initial state, 9 is a CPU, and 10 is a ROM.

11 is a RAM, which communicates with the CPU 9 via a data bus and an address bus, respectively.

20 is a battery that is a power source, and 21 is a built-in DC/DC converter.
), and supplies a high voltage (for example, 5V) when the input CNT is at a "low" level.

The crystal oscillator 22 is a low frequency (for example, 32 KHz) oscillator, and the crystal oscillator 23 is a high frequency (for example, 8 MHz) oscillator.
There is an oscillator. C is a capacitor, R is a resistor, and these constitute a delay circuit that delays the input to the reset circuit 8. D is a diode, and the diode D is for quickly discharging the charge stored in the capacitor C when the battery 2o is removed.

Next, the operation of the present invention according to the above configuration will be explained.

At the initial stage when the battery 20 is set, the D of the power supply circuit 21 is
Since the C/DC converter is inactive, power supply circuit 2
1 outputs the voltage of the battery 20 as it is and supplies the battery voltage to the power supply terminal VCC of the microcomputer-A.

On the other hand, capacitor 〇 is charged by battery 2° via resistor R. When the voltage of capacitor 〇 is below a predetermined voltage, the reset circuit 8 connected to it outputs a “high” level, and the “high” level is the set and reset terminal S and R of DF/Fl~4. DF/Fl, 2 connected to the reset circuit 8 is set and the output Q is “
The DF/Fs 3 and 4 are reset to output a "low" level to the output Q.

In addition, the CPU 9 is also reset because the "high" level is manually applied to the reset human power R, and the outputs Co-C5, Do-D3 are "
Furthermore, since the output of DF/Fl is set to a "high" level as described above, the input CNT of the power supply circuit 21 connected to the output terminal PO becomes a "high" level, and the DC/Fl output becomes a "high" level. The DC converter does not operate and outputs a low voltage (3v) of the battery voltage.

Furthermore, since the output of DF/F2 is "high" level and the output of FF/3 is "low" level, Nant gate 5 is enabled and Nant gate 6 is disabled, and the 32KHz crystal oscillation connected to Nant gate 5 is activated. The 8 MHz crystal oscillator 23 connected to the Nandt gate 6 has stopped oscillating.

Also, since the output of D/FF4 is at "low" level, the clock selection circuit 7 selects the input φ1 and selects 3KHz, which is the output of the Nantes gate 5. Since a "high" level is being applied, output of the system clock is prohibited in this state.

Charging of the capacitor 0 progresses from the above state, and when the voltage reaches a predetermined voltage, the reset state of the reset circuit 8 is released. Further, the reset circuit 8 has a built-in counter, and starts a counting operation when the reset state is released. As mentioned above, the crystal oscillator 22 is in an oscillating state at this time, and oscillation pulses are being output from the Nant gate 5. Therefore, after the reset is released, the reset circuit 8 counts the pulses by a predetermined number (for example, 256 pulses) and calculates the number of pulses. Output “
The reset of the clock selection circuit 7 is released and the low frequency signal from the Nantes gate 5, which is being supplied to the input φ1, is shifted from the "high" level to the "low" level.
It is transmitted to CPU9 as the system clock to U9. At the same time, a "low" level is also applied to the reset input R of the CPU 9, so that the CPU 9 is enabled to operate, and the computer operates with the low frequency system clock.

In this manner, in this embodiment, the computer is driven at low frequency and low voltage after being reset.

Next, the operation during high-speed processing will be explained. For high-speed processing, the output is from the CPU9. A "low" level is output to the output C8, and a latch pulse is output to the output C8. Note that this transition to high-speed processing is executed by program processing in the ROM10 by operating an external operation member (not shown), or transition to high-speed processing is performed according to a program during a sequence of program processing.

The output of CFI09 above. Since the "low" level from C8 and the latch pulse from output C8 are supplied to DF/Fl, the Q output of DF/Fl shifts to "low" level,
The power supply circuit 21 responds to the “low” level by turning on the internal DC.
/Activate the DC converter.

As a result, the power supply circuit 21 outputs a high voltage (5V) obtained by boosting the voltage of the battery 20, and the high voltage is supplied to the power supply terminal VCC of the computer A.

The power supply circuit 21 is configured to output a signal VH ("high" level) during high voltage operation, and is inputted to the computer A via the vo multiplication signal terminal P1, and the computer A responds to the vH multiplication signal. Then, the output D2 of the CPU 9 outputs a "high" level, the output C2 outputs a latch pulse, and the Q output of the DF/F3 becomes a "high" level. With this, the Nant gate 6 is enabled, and the oscillator 23
starts oscillating, and a high frequency signal of 8 MHz is output from the Nandt gate 6.

Further, after the CPU 9 sets the Q output of the DF/F3 to the "high" level, the CPU 9 sets the Q output of the DF/F3 to the "high" level until the oscillation of the oscillator stabilizes (for example, the L
OOm s) After waiting, it outputs a “high” level to output D3 and a latch pulse to output C3, and the Q of DF/F4 is output.
Makes the output “high” level. Q output of the DF/F4 (
Since the clock selection circuit 7 selects the input φ2 in response to the "high" level), the high frequency signal from the Nant gate 6 is supplied as the system clock. Frequency drive is provided.

Also, in order to shift from high-speed processing to low-speed processing, the CPU
9 output. outputs a “high” level from Co, and outputs a latch pulse from Co to make the Q output of DF/Fl a “high” level, and at the same time outputs a “low” level from the output D2 of the CPU 9.
In addition, a latch pulse is output from C2, and “ is output from output D3.
By outputting a latch pulse at low level from C3 to disable the oscillator 23, and then selecting the input φ1 in the selection circuit 7, a low voltage, low frequency driving state is achieved.

In addition to setting the power supply battery, the above reset operation may also be performed by providing a power supply switch for the battery 20 and turning on the switch to perform the above reset operation. Operation begins with low frequency and low voltage driving.

In addition, in the embodiment, the oscillator 22 is activated and the oscillator 23 is inactivated during reset, but both oscillators are inactivated during reset, and oscillator 2 is activated when the reset is canceled.
Only 2 may be in operation.

Furthermore, although a crystal oscillator is used as the oscillator in this example,
The present invention is not limited to this; a ceramic oscillator, a CR oscillator, etc. may be used, and an oscillator that outputs pulses may be connected.

Effect> As explained above, in the present invention, in a microcomputer having low frequency, high frequency, and multiple oscillation circuits,
By setting the system operating clock to a low frequency after reset, there is no need to apply high voltage to the microcomputer from the beginning, and current consumption can be reduced by not operating the high frequency oscillation circuit during reset. It became.

For this reason, in devices that use batteries, such as cameras, portable word processors, and calculators, there is no need to apply high voltage to the microcomputer when batteries are inserted, and only when high-speed processing is required, for example, DC
Since all that is required is to operate the /DC converter and apply a high voltage to the microcomputer, it has become possible to simplify the configuration of a system using this microcomputer.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a computer according to the present invention. 1 to 4...D-type flip-flop 5.6...Nant gate 7...Clock selection circuit 8...Reset circuit 9...CPU 20...Power supply circuit 22, 23...Crystal oscillation Child

Claims (1)

[Claims] A first oscillation circuit that outputs a low frequency clock pulse, a second oscillation circuit that outputs a high frequency clock pulse, a selection circuit that selects the clock pulse of the first or second oscillation circuit as the operating clock, and a high voltage or In a power supply and drive circuit for a computer that includes a power supply circuit that supplies a low voltage as an operating voltage and selects high and low clock pulses and high and low voltages to perform high-speed or low-speed processing operations, the selection circuit generates a first oscillation. When the clock pulse from the circuit is selected as the operating clock, the second
A control circuit is provided that disables the oscillation circuit of the computer, and the control circuit and the power supply circuit are made to respond to a reset circuit that resets the computer, and the control circuit is activated during the initial operation after the reset circuit releases the reset. A power supply and drive circuit for a computer, characterized in that the power supply circuit outputs a low voltage.