JPS63265632A - Manufacture of laminated sheet - Google Patents
Manufacture of laminated sheetInfo
- Publication number
- JPS63265632A JPS63265632A JP62007087A JP708787A JPS63265632A JP S63265632 A JPS63265632 A JP S63265632A JP 62007087 A JP62007087 A JP 62007087A JP 708787 A JP708787 A JP 708787A JP S63265632 A JPS63265632 A JP S63265632A
- Authority
- JP
- Japan
- Prior art keywords
- base material
- prepreg
- thickness
- resin
- conductor layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000463 material Substances 0.000 claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 36
- 238000000465 moulding Methods 0.000 claims description 13
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 abstract description 28
- 239000011347 resin Substances 0.000 abstract description 28
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 230000003746 surface roughness Effects 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 239000011889 copper foil Substances 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 4
- 229920005992 thermoplastic resin Polymers 0.000 abstract description 3
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 239000002657 fibrous material Substances 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 238000007711 solidification Methods 0.000 abstract 1
- 230000008023 solidification Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 239000004744 fabric Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 210000004709 eyebrow Anatomy 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- -1 fluororesin Polymers 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000123 paper Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000012209 synthetic fiber Substances 0.000 description 1
- 229920002994 synthetic fiber Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
Landscapes
- Laminated Bodies (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明は、積層板の製法に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a method for manufacturing a laminate.
プリント板用の積層板は、現在多くの0AIl器に使用
されており、高密度化のために多層板へと移行してきた
。Laminated boards for printed boards are currently used in many OAIl devices, and there has been a shift to multilayer boards for higher density.
現状では、0.20Wmきざみの層間厚み(導体層と導
体層との間の間隔)を出すには、0.10m厚のプリプ
レグを複数枚組み合わせている。このため、必要なプリ
プレグの枚数が多くなり、コストが高くなるという問題
が生じている。材料の使用量を減らすことが緊急の課題
である。Currently, in order to obtain interlayer thicknesses (intervals between conductor layers) in steps of 0.20 Wm, a plurality of prepregs each having a thickness of 0.10 m are combined. For this reason, the problem arises that the number of required prepregs increases and the cost increases. There is an urgent need to reduce the amount of materials used.
しかし、この課題を解決できても、他の不都合が生じる
ことは好ましくない、たとえば、積層板に電子部品など
を実装する場合に、積層板を半田浴に浮かべたり、浸漬
したりするので、半田耐熱性が悪化しないようにする必
要がある。また、高密度化を図るためには、回路パター
ンもファイン化する必要がある。この要求に答えるには
、積層板の表面粗度が優れていることが必要である。However, even if this problem can be solved, it is undesirable to have other inconveniences.For example, when mounting electronic components on a laminate, the laminate is floated or immersed in a solder bath, so it is not desirable to solder the laminate. It is necessary to prevent heat resistance from deteriorating. Furthermore, in order to achieve higher density, it is necessary to make the circuit pattern finer. To meet this requirement, it is necessary that the surface roughness of the laminate be excellent.
この発明は、以上のことに鑑みて、半田耐熱性および表
面平滑性に優れた積層板を安価に作ることができる積層
板の製法を提供することを目的とする。In view of the above, an object of the present invention is to provide a method for manufacturing a laminate that can inexpensively produce a laminate with excellent solder heat resistance and surface smoothness.
材料の使用量削減を図るため、発明者らは、従来のよう
な薄物(0,10m厚)プリプレグを複数枚組み合わせ
るのではなく、所望の眉間厚み(たとえば、0.20m
きざみ)を1枚で満足するようなプリプレグを使用すれ
ば良いと考えて、研究を進めた。In order to reduce the amount of material used, the inventors did not combine multiple sheets of thin prepreg (0.10 m thick) as in the past, but instead created a material with a desired glabellar thickness (for example, 0.20 m thick).
We proceeded with our research with the idea that we should use a prepreg that satisfies the above requirements with just one sheet.
ところが、従来のプリプレグよりも厚いプリプレグを用
いて積層板、特に多層板を製造すると、■半田耐熱性が
悪い、■表面粗度が悪い、の2つの問題が生じた。However, when producing a laminate, especially a multilayer board, using a prepreg thicker than conventional prepreg, two problems arose: (1) poor solder heat resistance, and (2) poor surface roughness.
前記■による実際問題は、積層板に電子部品を半田実装
する際に、積層板に眉間剥離が生じることである。厚い
プリプレグは、その基材も厚いため、樹脂の基材への含
浸性が悪くなる。このような厚いプリプレグを多層板に
用いると、成形後、プリプレグの基材が内層回路やその
基板と直接接触してしまい、両者の間に接着に必要な樹
脂が存在しなく−なることがある。このため、半田浴(
温度が、たとえば、260℃)のような熱衝撃には耐え
切れず、眉間剥離を生じる。また、樹脂の基材への含浸
が充分ではないため、基材中に空気(エアー)が残るこ
とがあり、この空気が熱膨張するとフクレなどの原因と
なる。The practical problem caused by the above item (2) is that when electronic components are soldered onto the laminate, peeling occurs between the eyebrows of the laminate. Since the base material of thick prepreg is also thick, impregnation of the resin into the base material becomes poor. When such thick prepreg is used in a multilayer board, the base material of the prepreg comes into direct contact with the inner layer circuit and its substrate after molding, and the resin necessary for adhesion may not exist between the two. . For this reason, solder bath (
It cannot withstand a thermal shock at a temperature of, for example, 260° C., resulting in peeling between the eyebrows. Furthermore, since the resin is not sufficiently impregnated into the base material, air may remain in the base material, and when this air expands thermally, it causes blisters.
上記■による実際問題は、表面粗度が4μm以下でない
とファインパターンが作製できず、多層板に必要な高密
度パターンの作製が不可能となることである。基材の厚
みを厚くするために、太い糸を織り上げたりすることに
なり、基材表面の凸凹が大きくなる。それに加えて、所
望の眉間厚み(たとえば、0.20m)を得るのにその
厚み(たとえば、0.20m1m)の基材を使用した場
合には、それ相当の樹脂量しかなく、基材の凸凹が表面
に現れやすくなる。The practical problem with (2) above is that unless the surface roughness is 4 μm or less, a fine pattern cannot be produced, and it becomes impossible to produce a high-density pattern required for a multilayer board. In order to increase the thickness of the base material, thick threads must be woven, which increases the unevenness of the base material surface. In addition, if a base material of that thickness (for example, 0.20 m1m) is used to obtain the desired glabellar thickness (for example, 0.20 m), there will be only a corresponding amount of resin, and the unevenness of the base material becomes more likely to appear on the surface.
これら2つの問題を解決すべく研究した結果、必要とす
る眉間厚みより5μm以上薄い基材を用い、所望層間厚
みに必要な樹脂量を含浸させることにより、従来の薄物
プリプレグで達成しうる半田耐熱性および表面平滑性を
備えることを見い出した。As a result of research aimed at solving these two problems, we found that by using a base material that is at least 5 μm thinner than the required glabellar thickness and impregnating it with the amount of resin necessary for the desired interlayer thickness, it is possible to achieve solder heat resistance with conventional thin prepreg. It has been found that the material has excellent properties of hardness and surface smoothness.
したがって、この発明は、接着層を兼ねた絶縁層の形成
のためのプリプレグを導体層と導体層との間に介在させ
て積層成形を行う積層板の製法において、前記プリプレ
グとして、その基材の厚みが前記導体層と導体層との間
の所望厚みよりも5μm以上薄いものを用いることを特
徴とする積層板の製法を要旨とする。Therefore, the present invention provides a method for manufacturing a laminate in which a prepreg for forming an insulating layer that also serves as an adhesive layer is interposed between conductor layers and laminated. The gist of the present invention is a method for manufacturing a laminate, characterized in that the thickness is 5 μm or more thinner than the desired thickness between the conductor layers.
以下に、この発明の詳細な説明する。The present invention will be explained in detail below.
接着層を兼ねた絶縁層の形成のためのプリプレグは、樹
脂が基材に含浸され、固化または半硬化されてなるもの
である。プリプレグは、その全体の厚みが0.2鶴以上
であることが望ましい、プリプレグが0.2鶴よりも薄
いと、導体層間の絶縁性の保証ができにくくなるからで
ある。A prepreg for forming an insulating layer that also serves as an adhesive layer is obtained by impregnating a base material with a resin and solidifying or semi-curing the prepreg. It is desirable that the prepreg has a total thickness of 0.2 mm or more, because if the prepreg is thinner than 0.2 mm, it becomes difficult to guarantee the insulation between the conductor layers.
前記基材としては、前記導体層と導体層との間の所望厚
みよりも5μm以上薄いものを用いる。The base material used is one that is 5 μm or more thinner than the desired thickness between the conductor layers.
このような基材に、樹脂分が従来のプリプレグと同程度
となるように樹脂を含浸させると、基材が薄い分だけ表
面の樹脂層が厚くなる。この樹脂層は、前記所望厚みと
基材の厚みとの差を埋めて、基材と導体層とを接着させ
るとともに、基材表面の凸凹を平坦化させる。樹脂層は
、基材の両面に均等な厚みで形成されているのが好まし
いが、両面で厚みが均等でなくてもよい、前記基材の厚
みが、前記所望厚みよりも5μm以上薄くないと、基材
表面に付着している樹脂層が薄すぎて、接着に必要な樹
脂が介在しないことがあり、また、表面粗度が悪くなる
。導体層と導体層との間の所望厚みが、たとえば、0.
20mである場合、基材の厚みは0.195m以下であ
る。この場合、基材の厚みは、0.18〜0.1951
)mの範囲が好ましい。When such a base material is impregnated with a resin so that the resin content is the same as that of a conventional prepreg, the resin layer on the surface becomes thicker as the base material is thinner. This resin layer fills the difference between the desired thickness and the thickness of the base material, adheres the base material and the conductor layer, and flattens the unevenness on the surface of the base material. The resin layer is preferably formed with a uniform thickness on both sides of the base material, but the thickness does not have to be uniform on both sides, as long as the thickness of the base material is not less than 5 μm thinner than the desired thickness. In some cases, the resin layer attached to the surface of the base material is so thin that the resin necessary for adhesion is not present, and the surface roughness becomes poor. If the desired thickness between the conductor layers is, for example, 0.
In the case of 20 m, the thickness of the base material is 0.195 m or less. In this case, the thickness of the base material is 0.18 to 0.1951
) m range is preferred.
また、導体層と導体層との間の所望厚みが、0.25鰭
である場合、基材の厚みは0.245℃m以下であり、
導体層と導体層との間の所望厚みが、0.39 amで
ある場合、基材の厚みは0.2951)n以下である。Further, when the desired thickness between the conductor layers is 0.25 fin, the thickness of the base material is 0.245 °C m or less,
If the desired thickness between the conductor layers is 0.39 am, then the thickness of the substrate is less than or equal to 0.2951)n.
前記基材は、繊維質のものが用いられる。繊維質基材と
しては特に限定はないが、たとえば、ガラス布、紙、合
成繊維布、天然繊維布などが挙げられる。布は織布でも
よく、不織布でもよい。繊維質基材に含浸される樹脂と
しては、特に限定はなく、熱可塑性樹脂および熱硬化性
樹脂のいずれでもよい。また、含浸される樹脂は、他の
物質、たとえば、架橋性を有する物質、硬化剤、硬化促
進剤、充填材などの1種またはそれ以上を必要に応じて
含んでいてもよい。前記熱可塑性樹脂には特に限定はな
く、たとえば、ポリフェニレンオキサイド、フッ素樹脂
などが挙げられる。前記熱硬化性樹脂には特に限定はな
く、たとえば、エポキシ樹脂、フッ素樹脂、ポリイミド
樹脂などが挙げられる。The base material used is fibrous. The fibrous base material is not particularly limited, but examples thereof include glass cloth, paper, synthetic fiber cloth, and natural fiber cloth. The cloth may be woven or non-woven. The resin impregnated into the fibrous base material is not particularly limited, and may be either a thermoplastic resin or a thermosetting resin. Further, the resin to be impregnated may contain one or more other substances, such as a crosslinkable substance, a curing agent, a curing accelerator, and a filler, as necessary. The thermoplastic resin is not particularly limited, and examples thereof include polyphenylene oxide, fluororesin, and the like. The thermosetting resin is not particularly limited, and examples thereof include epoxy resin, fluororesin, polyimide resin, and the like.
導体層は、銅箔などの金属箔、絶縁基板に形成された回
路(いわゆる内層材)などであるが、これらに限定する
ものではない。The conductor layer may be a metal foil such as a copper foil, a circuit formed on an insulating substrate (so-called inner layer material), but is not limited to these.
この発明に使用されるプリプレグは、所望層間厚みより
も5μm以上薄い厚みを持つ基材が用いられているので
、成形後、層間厚みと基材の厚みとの差の部分には確実
に樹脂層が形成される。このため、基材と、導体層また
はその導体層の基板(内層材、外層材など)などとの間
に樹脂が確実に介在するようになり、半田耐熱性を向上
させることができるとともに表面粗度も4μm以下にす
ることができる。また、導体層が回路である場合には、
回路間の空隙も埋めることができる。プリプレグとして
、その全体の厚みが0.2 w以上であるものを用いれ
ば、導体層間の絶縁が確実になるまた、従来のプリプレ
グを用いた成形では、プリプレグ中の樹脂を絞り出す必
要があり、成形圧力が、たとえば、40kg/cd程度
と高かった。このため、導体層、特に回路が成形圧力で
ずれたりしていた。しかし、この発明にかかる製法では
、上記のようなプリプレグを用いるので、樹脂を絞り出
す程度が小さくてすみ、成形圧力を低く (たとえば、
約4分の1.10kg/−程度)することが可能である
。このため、この発明にかかる製法によれば、回路のず
れを防ぐことができ、ファインパターンであっても対応
できる。特に、積層板を多層板としたときに、その精度
を高めることができる。The prepreg used in this invention uses a base material that is 5 μm or more thinner than the desired interlayer thickness, so after molding, the resin layer is reliably applied to the difference between the interlayer thickness and the base material thickness. is formed. Therefore, the resin is reliably interposed between the base material and the conductor layer or the substrate of the conductor layer (inner layer material, outer layer material, etc.), which improves soldering heat resistance and improves surface roughness. The thickness can also be reduced to 4 μm or less. Also, if the conductor layer is a circuit,
It can also fill gaps between circuits. If a prepreg with a total thickness of 0.2 W or more is used, the insulation between the conductor layers will be ensured.In addition, in conventional molding using prepreg, it is necessary to squeeze out the resin in the prepreg, making the molding process difficult. The pressure was high, for example, about 40 kg/cd. For this reason, the conductor layer, especially the circuit, has been displaced by the molding pressure. However, in the manufacturing method according to the present invention, since the above-mentioned prepreg is used, the extent of squeezing out the resin is small, and the molding pressure is low (for example,
(approximately 1/4 of 1.10 kg/-). Therefore, according to the manufacturing method according to the present invention, it is possible to prevent circuit misalignment, and even fine patterns can be handled. In particular, when the laminate is made into a multilayer board, the accuracy can be improved.
以下、実施例および比較例を挙げてこの発明をさらに詳
しく説明するが、この発明は下記実施例に限定されない
。EXAMPLES Hereinafter, this invention will be explained in more detail with reference to Examples and Comparative Examples, but this invention is not limited to the following Examples.
(実施例1〜4)
第1表に示す厚みのガラス布に樹脂を含浸させ、同表に
示すようなプリプレグをつくった。このプリプレグを用
い、第1図にみるように、銅箔1、プリプレグ2、内層
回路板3、プリプレグ2および銅箔lの順に積層し、下
記の成形条件で成形して、それぞれ層間厚み0.2nタ
イプ、0.25mmタイプ、0.3mタイプの積層板を
得た。内層回路板3は、厚み1.0fiの絶縁基板4と
その両面に形成された厚み70μmの内層回路(導体層
)5゜5からなっていた。この内層回路5は、厚み70
μmの金属の薄層をエツチングして、格子状のシールド
パターンとして形成された。(Examples 1 to 4) Glass cloths having the thicknesses shown in Table 1 were impregnated with resin to produce prepregs as shown in Table 1. Using this prepreg, as shown in FIG. 1, copper foil 1, prepreg 2, inner layer circuit board 3, prepreg 2, and copper foil 1 are laminated in this order, and molded under the following molding conditions, each with an interlayer thickness of 0. Laminated plates of 2n type, 0.25 mm type, and 0.3 m type were obtained. The inner layer circuit board 3 consisted of an insulating substrate 4 with a thickness of 1.0 fi and inner layer circuits (conductor layers) 5.5 with a thickness of 70 μm formed on both sides of the insulating substrate 4. This inner layer circuit 5 has a thickness of 70
A thin layer of .mu.m metal was etched to form a grid-like shield pattern.
く成形条件〉
温度;120℃で30分間、つぎに170℃で70分間
。Molding conditions> Temperature: 120°C for 30 minutes, then 170°C for 70 minutes.
圧力;4kg/cnlで10分間、つぎに40kg/c
alで終了まで。Pressure: 4kg/cnl for 10 minutes, then 40kg/cnl
until the end with al.
(比較例1〜3)
第1表に示す厚みのガラス布に樹脂を含浸させ、同表に
示すようなプリプレグをつくった。実施例1においてプ
リプレグ2を用いる代わりにこのプリプレグを用いた以
外は、実施例1と同様にして、それぞれ層間厚み0.2
tmタイプ、0.25mタイプ、0.3mタイプの積
層板を得た。(Comparative Examples 1 to 3) Glass cloths having the thicknesses shown in Table 1 were impregnated with resin to produce prepregs as shown in Table 1. In the same manner as in Example 1 except that this prepreg was used instead of prepreg 2 in Example 1, the interlayer thickness was 0.2.
Laminated plates of tm type, 0.25m type, and 0.3m type were obtained.
これら実施例1〜4および比較例1〜3で得られた各積
層板の特性の測定結果を第1表に示したなお、ガラス布
の厚みは、JIS−R−3420により測定した。また
、半田耐熱性は、260℃の半田に20秒間浸漬し、フ
クレまたはハガレの有(×)無(OK)で評価した。The measurement results of the characteristics of each laminate obtained in Examples 1 to 4 and Comparative Examples 1 to 3 are shown in Table 1. The thickness of the glass cloth was measured according to JIS-R-3420. Furthermore, the solder heat resistance was evaluated by immersing it in solder at 260° C. for 20 seconds and evaluating the presence (x) and absence (OK) of blistering or peeling.
第1表から明らかなように、層間厚み0.2fiタイプ
、0.25mタイプ、0.3mタイプとも実施例は比較
例よりも、耐熱性および表面平滑性が優れている。As is clear from Table 1, the examples are superior in heat resistance and surface smoothness to the comparative examples in all of the 0.2 fi type, 0.25 m type, and 0.3 m interlayer thickness types.
なお、上記実施例では、比較例と同じ成形圧力であった
が、この発明にかかる積層板の製法によれば、従来より
もはるかに低い成形圧力で成形することができる。たと
えば゛、約1/4.10kg/i程度の成形圧力で成形
することができる。In the above example, the molding pressure was the same as that of the comparative example, but according to the method for manufacturing a laminate according to the present invention, molding can be performed at a much lower molding pressure than conventionally. For example, it can be molded at a molding pressure of about 1/4.10 kg/i.
この発明にかかる積層板の製法は、以上にみてきたよう
に、プリプレグとして、その基材の厚みが導体層と導体
層との間の所望厚みよりも5μm以上薄いものを用いる
ので、半田耐熱性および表面平滑性に優れた積層板を得
ることができるとともに、眉間のプリプレグが1枚です
むので、必要なプリプレグの枚数を減らすことができ、
安価に構成することができる。As described above, the method for producing a laminate according to the present invention uses a prepreg whose base material is 5 μm or more thinner than the desired thickness between the conductor layers, so that it has good soldering heat resistance. It is possible to obtain a laminate with excellent surface smoothness, and since only one prepreg is required between the eyebrows, the number of required prepregs can be reduced.
It can be constructed at low cost.
第1図は積層板の構成を分解してあられす側面図である
。
2・・・プリプレグFIG. 1 is an exploded side view of the structure of the laminate. 2...Prepreg
Claims (2)
を導体層と導体層との間に介在させて積層成形を行う積
層板の製法において、前記プリプレグとして、その基材
の厚みが前記導体層と導体層との間の所望厚みよりも5
μm以上薄いものを用いることを特徴とする積層板の製
法。(1) In a method for manufacturing a laminate in which a prepreg for forming an insulating layer that also serves as an adhesive layer is interposed between conductive layers and laminated molding is performed, the thickness of the base material of the prepreg is 5 than the desired thickness between the conductor layers
A method for manufacturing a laminate, characterized by using a material thinner than μm.
許請求の範囲第1項記載の積層板の製法。(2) The method for manufacturing a laminate according to claim 1, wherein the entire thickness of the prepreg is 0.2 mm or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62007087A JPS63265632A (en) | 1986-12-15 | 1987-01-14 | Manufacture of laminated sheet |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29958086 | 1986-12-15 | ||
JP61-299580 | 1986-12-15 | ||
JP62007087A JPS63265632A (en) | 1986-12-15 | 1987-01-14 | Manufacture of laminated sheet |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63265632A true JPS63265632A (en) | 1988-11-02 |
Family
ID=26341343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62007087A Pending JPS63265632A (en) | 1986-12-15 | 1987-01-14 | Manufacture of laminated sheet |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63265632A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59155192A (en) * | 1983-02-23 | 1984-09-04 | 日本電気株式会社 | Method of producing multilayer printed circuit board |
JPS59208897A (en) * | 1983-05-13 | 1984-11-27 | 日本電気株式会社 | Method of producing multilayer printed circuit board |
-
1987
- 1987-01-14 JP JP62007087A patent/JPS63265632A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59155192A (en) * | 1983-02-23 | 1984-09-04 | 日本電気株式会社 | Method of producing multilayer printed circuit board |
JPS59208897A (en) * | 1983-05-13 | 1984-11-27 | 日本電気株式会社 | Method of producing multilayer printed circuit board |
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