JPS63265421A - Manufacture of semiconductor single crystal layer - Google Patents

Manufacture of semiconductor single crystal layer

Info

Publication number
JPS63265421A
JPS63265421A JP9873387A JP9873387A JPS63265421A JP S63265421 A JPS63265421 A JP S63265421A JP 9873387 A JP9873387 A JP 9873387A JP 9873387 A JP9873387 A JP 9873387A JP S63265421 A JPS63265421 A JP S63265421A
Authority
JP
Japan
Prior art keywords
scanning
single crystal
crystal layer
semiconductor
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9873387A
Other languages
Japanese (ja)
Other versions
JPH0793263B2 (en
Inventor
Masahito Kenmochi
剣持 雅人
Tomoyasu Inoue
井上 知泰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP62098733A priority Critical patent/JPH0793263B2/en
Publication of JPS63265421A publication Critical patent/JPS63265421A/en
Publication of JPH0793263B2 publication Critical patent/JPH0793263B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To equalize the annealing temperature of the surface of a sample while forming a semiconductor single crystal layer having excellent and uniform crystalline characteristics onto an insulating substrate by assigning at least one of the positions of scanning and scanning speed at every scanning line of beams so that annealing temperatures at each position of scanning of beams applied onto the sample are kept constant. CONSTITUTION:The detecting signal of a temperature sensor 15 is transmitted to a computer 16. Information such as the order of the scanning of beams, scanning speed at every position of scanning, etc., is sent to a buffer memory 17 from the computer 16, and stored temporarily to the memory. The buffer memory 17 removes the delay of the transfer time, and the memory information of the memory 17 is transmitted to an X deflection driver 18 and a Y deflection driver 19. The upper section of a sample 12 is scanned with electron beams by an X deflection coil 13 and a Y deflection coil 14. An annealing region A is annealed by the scanning of approximately twenty beams, scanning speed (v) is kept constant, and the positions of scanning are determined at every other beam. Electron beams are deflected at high speed in the direction that they cross at right angles with the direction of scanning, and changed into quasi linear beams. The effect of remaining heat is reduced by the scanning, thus improving the uniformity of a surface temperature.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、絶縁基板上に半導体単結晶層を製造する方法
に係わり、特に電子ビームアニール法を利用した半導体
単結晶層の製造方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor single crystal layer on an insulating substrate, and particularly relates to a method for manufacturing a semiconductor single crystal layer using an electron beam annealing method. Relating to a manufacturing method.

(従来の技術) 近年、絶縁膜上にシリコン単結晶層を形成する、所謂S
 OI (Silicon On In5ulator
)技術のりコン酸化膜やシリコン窒化膜等の絶縁膜を介
して多結晶若しくは非晶質のシリコン薄膜を堆積する。
(Prior art) In recent years, so-called S
OI (Silicon On In5ulator)
) Technique A polycrystalline or amorphous silicon thin film is deposited via an insulating film such as a silicon oxide film or a silicon nitride film.

そして、このシリコン薄膜を電子ビームやレーザビーム
等のエネルギービームを用いて溶融争再結晶化(ビーム
アニール)させ、シリコン単結晶層を成長させている。
Then, this silicon thin film is melt-recrystallized (beam annealed) using an energy beam such as an electron beam or a laser beam to grow a silicon single crystal layer.

電子ビームアニール法を利用した再結晶化工程について
、第11図を参照して簡単に説明する。
The recrystallization process using the electron beam annealing method will be briefly explained with reference to FIG.

再結晶化すべき領域Aを電子ビームの走査によりアニー
ルするのであるが、まず電子ビームを■の位置でX方向
に走査し、次いで電子ビームをY方向にビーム幅相当分
だけ移動しこの位置■でビームをX方向に走査する。さ
らに、ビームをY方向にビーム幅相当分だけ移動し、同
様にこの位置■でビームをX方向に走査する。これを繰
返すことによって、アニールすべき領域Aの全面が溶融
・再結晶化されることになる。
The region A to be recrystallized is annealed by scanning the electron beam. First, the electron beam is scanned in the X direction at the position (■), then the electron beam is moved in the Y direction by an amount equivalent to the beam width, and at this position (■) Scan the beam in the X direction. Further, the beam is moved in the Y direction by an amount equivalent to the beam width, and the beam is similarly scanned in the X direction at this position (2). By repeating this process, the entire area A to be annealed is melted and recrystallized.

しかしながら、この種の方法にあっては、次のような間
°題があった。即ち、電子ビームを走査しビームの走査
回数が増える程、余熱効果の影響によってアニール温度
が高くなり、ビームの照射初期領域と照射後期領域とで
は第12図に示す如く温度分布が異なったものとなる。
However, this type of method has the following problems. In other words, as the electron beam is scanned and the number of beam scans increases, the annealing temperature increases due to the influence of the residual heat effect, and the temperature distribution is different between the early beam irradiation area and the late irradiation area, as shown in Figure 12. Become.

このため、対象試料表面の全面均一アニールが不可能と
なり、大面積で且つ良質なシリコン結晶層を成長させる
ことは困難であった。また、上記余熱効果による影響で
、ビーム照射初期においてはビーム強度が溶融に不十分
となるにも拘らず、照射後期においては溶融過多となる
虞れもあった。
For this reason, uniform annealing of the entire surface of the target sample was impossible, and it was difficult to grow a large-area, high-quality silicon crystal layer. Further, due to the above-mentioned residual heat effect, although the beam intensity is insufficient for melting in the early stage of beam irradiation, there is a risk that excessive melting will occur in the latter stage of irradiation.

(発明が解決しようとする問題点) このようは従来、電子ビームを用いて半導体薄膜を単結
晶化する際には、ビーム走査初期領域と走査後期領域と
で余熱効果の違いに起因する試料表面のアニール温度の
不均一性の問題があり、これが大面積で良質の半導体単
結晶層の成長を妨げる大きな要因となっていた。
(Problem to be Solved by the Invention) Conventionally, when single-crystallizing a semiconductor thin film using an electron beam, the sample surface There is a problem of non-uniformity in the annealing temperature, which has been a major factor hindering the growth of high-quality semiconductor single crystal layers over large areas.

本発明は上記事情を考慮してなされたもので、その目的
とするところは、−試料表面のアニール温−万弘を促供
することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to improve the annealing temperature of the sample surface.

【発明の構成] (問題点を解決するための手段) 本発明の骨子は、試料上に照射する電子ビームの走査方
法を改良し、ビーム照射領域の全域を均一に溶融・再結
晶化することにある。
[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to improve the scanning method of the electron beam irradiated onto the sample and uniformly melt and recrystallize the entire beam irradiation area. It is in.

即ち本発明は、絶縁性基板上に形成された多結晶若しく
は非晶質の半導体薄膜に、電子ビームを照射すると共に
走査して該薄膜を溶融・再結晶化する半導体単結晶層の
製造方法において、前記ビームの各走査位置におけるア
ニール温度が一定となるように、該ビームの各走査線毎
に走査位置及び走査速度の少なくとも一方を指定するよ
うにした方法である。
That is, the present invention provides a method for manufacturing a semiconductor single crystal layer in which a polycrystalline or amorphous semiconductor thin film formed on an insulating substrate is irradiated with an electron beam and scanned to melt and recrystallize the thin film. In this method, at least one of a scanning position and a scanning speed is specified for each scanning line of the beam so that the annealing temperature at each scanning position of the beam is constant.

(作用) 本発明によれば、ビームの各走査線毎の走査速度を可変
としたり、或いは走査する位置を適宜選択することによ
り、ビーム走査初期領域と走査後期領域とにおける余熱
温度の影響を小さくすることができる。つまり、試料表
面上のアニール時1ψj−声度分布が位置によらず均一
となるよう、再結ビーム走査位置(走査順序)を選択す
る手段の一例としては、ビームの照射位置に注目し余熱
効果の影響を受けない程遠く離れた走査位置毎にビーム
走査を行い、離れた領域毎に再結晶化する。
(Function) According to the present invention, by varying the scanning speed of each scanning line of the beam or by appropriately selecting the scanning position, the influence of residual heat temperature in the early beam scanning area and the late scanning area can be reduced. can do. In other words, one way to select the recombinant beam scanning position (scanning order) so that the 1ψj-vocality distribution during annealing on the sample surface is uniform regardless of the position is to focus on the beam irradiation position and take into consideration the residual heat effect. Beam scanning is performed at each scanning position that is far enough away to be unaffected by the effects of the beam, and recrystallization is performed at each distant area.

つまり、ビーム走査を少なくとも1本の走査線間隔を保
ちながら行うようにすればよい。これにより、第n番目
の照射位置においては第n−1番目の照射による余熱効
果を著しく低減することが可能である。また、ビーム走
査速度を可変する手段の一例としては、ビーム走査初期
領域よりも走査後期領域の方で走査速度が速くなるよう
にすればよい。
In other words, beam scanning may be performed while maintaining an interval of at least one scanning line. Thereby, it is possible to significantly reduce the residual heat effect caused by the (n-1)th irradiation at the nth irradiation position. Further, as an example of means for varying the beam scanning speed, the scanning speed may be set to be faster in the late beam scanning region than in the early beam scanning region.

(実施例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第1図は本発明の一実施例方法に使用した電子ビームア
ニール装置を示す概略構成図である。図中10は電子銃
であり、この電子銃10から放射された電子ビームはレ
ンズ11に尖り集束されてらにビームをY方向に高速偏
向するための偏向板、(図示せず)等が設置されている
FIG. 1 is a schematic diagram showing an electron beam annealing apparatus used in an embodiment of the present invention. In the figure, 10 is an electron gun, and the electron beam emitted from the electron gun 10 is sharply focused by a lens 11, and a deflection plate (not shown), etc. is installed to deflect the beam at high speed in the Y direction. ing.

、:、゛温度センサ15の検出信号は計算機16に送出
されている。計算機16からは、ビームの走査順序及び
各走査位置毎の走査速度等の情報がバッファメモリ17
に与えられ、このメモリに一時記憶されている。バッフ
ァメモリ17はビーム走査時におけるデータの転送時間
の遅れをなくすものであり、その記憶情報はX偏向ドラ
イバ18及びY偏向ドライバ19に与えられる。そして
、X偏向コイル13及びY偏向コイル14により電子ビ
ームが試料12上で走査されるものとなっている。
, :, ``The detection signal of the temperature sensor 15 is sent to the computer 16. From the computer 16, information such as the beam scanning order and the scanning speed for each scanning position is stored in the buffer memory 17.
and is temporarily stored in this memory. The buffer memory 17 eliminates delays in data transfer time during beam scanning, and its stored information is given to the X deflection driver 18 and the Y deflection driver 19. The electron beam is scanned over the sample 12 by the X deflection coil 13 and the Y deflection coil 14.

次に、上記装置を用いた半導体単結晶層の製造方法につ
いて説明する。
Next, a method for manufacturing a semiconductor single crystal layer using the above apparatus will be described.

試料としては、第2図に示す如く絶縁性基板上に多結晶
シリコン薄膜を形成したものを用いた。
The sample used was a polycrystalline silicon thin film formed on an insulating substrate as shown in FIG.

即ち、単結晶SL基板21上に絶縁膜22として5i0
2膜を形成し、この絶縁膜22の一部にシードとなる開
口部23を形成する。その後、全面溶融・再結晶化を行
う。
That is, 5i0 is used as the insulating film 22 on the single crystal SL substrate 21.
Two films are formed, and an opening 23 serving as a seed is formed in a part of this insulating film 22. After that, the entire surface is melted and recrystallized.

第3図はアニールすべき領域及びビーム走査位置を示す
模式図である。アニール領域Aは20本のビーム走査に
よりアニールされるものとし、X方向のビーム走査位置
をY方向に沿って■、■、〜。
FIG. 3 is a schematic diagram showing the area to be annealed and the beam scanning position. It is assumed that the annealing region A is annealed by scanning with 20 beams, and the beam scanning positions in the X direction are set as ■, ■, ~ along the Y direction.

とする。shall be.

ビームの走査順序及び走査速度を第5図に示す。The beam scanning order and scanning speed are shown in FIG.

この例では、走査速度Vは一定(v g =100ma
/s)とし、走査位置を1本おきにした。電子ビームの
加速電圧はl0KV、ビーム電流は41^でビームを走
査方向と直交する方向に高速偏向し疑似線状化したビー
ムを用いた。この走査により、余熱効果が著しく減少し
、第4図に示す如く表面温度の均一性が向上した。また
、再結晶化層の均一性は向上し、表面の凹凸がO,lu
m以下の平坦性を持つようになった。
In this example, the scanning speed V is constant (v g =100 ma
/s), and the scanning position was set to every other line. The acceleration voltage of the electron beam was 10 KV, the beam current was 41^, and the beam was deflected at high speed in a direction perpendicular to the scanning direction to form a pseudo-linear beam. This scanning significantly reduced the residual heat effect and improved the uniformity of the surface temperature as shown in FIG. In addition, the uniformity of the recrystallized layer is improved, and the surface irregularities are reduced to O, lu
It now has a flatness of less than m.

また、第6図に示す如く、2本或いはそれ以上の間隔を
おいてビームを走査した場合、より有効に余熱効果を低
減することができた。さらに、走査位置をデータとして
蓄えておくことが可能なこ慮した再結晶化を行うことが
できた。
Furthermore, as shown in FIG. 6, when two or more beams were scanned at an interval, the residual heat effect could be reduced more effectively. Furthermore, we were able to perform recrystallization taking into account the possibility of storing scanning positions as data.

本発明者等の実験によれば、試料基板温度800℃、電
子ビームの加速電圧10KV、エミッション電流4mA
 +走査線を1■ピツチで20本、走査位置は第7図に
示す順序で走査したところ、8 mmX 20avの均
一な単結晶層を得ることができた。この実験からも、走
査位置の走査順序を決めることの重要性及びその有用性
が明白である。
According to experiments conducted by the present inventors, the sample substrate temperature was 800°C, the electron beam acceleration voltage was 10 KV, and the emission current was 4 mA.
When 20 + scanning lines were scanned at 1 inch pitch and the scanning positions were scanned in the order shown in FIG. 7, a uniform single crystal layer of 8 mm x 20 av could be obtained. From this experiment as well, the importance and usefulness of determining the scanning order of scanning positions is clear.

また、走査線1本毎にブランキングを行い、ブランキン
グの時間間隔を走査線毎に決めて、再結晶化する実験も
行った。ブランキングは、走査電極に電圧をかけること
によりビームを試料からはずすことにより行っている。
We also conducted an experiment in which blanking was performed for each scanning line, the blanking time interval was determined for each scanning line, and recrystallization was performed. Blanking is performed by removing the beam from the sample by applying a voltage to the scanning electrode.

また、走査順序は従来方法と同様とし、走査速度を可変
にする方法もある。本発明者等の実験によれば、第8図
に示す如く走査速度を30〜1100a/sの範囲でv
lからv2゜までの速度が徐々に変化するようにさせた
ところ、均一な大面積単結晶化層が得られた。これは、
余熱効果の影響が大とである。
There is also a method in which the scanning order is the same as in the conventional method and the scanning speed is variable. According to experiments conducted by the present inventors, as shown in FIG.
When the speed was gradually changed from l to v2°, a uniform large-area single crystal layer was obtained. this is,
The residual heat effect has a large influence.

また、走査位置と走査順序及び走査速度を同時に変化さ
せてもよい。第9図に示す如く各走査線の間隔は少なく
とも1本の間隔を持ち、走査速度も30〜100IIJ
Il/sの範囲で変化させ、且つ適宜ブランキングを行
った。電子ビームは加速電圧10KV。
Furthermore, the scanning position, scanning order, and scanning speed may be changed simultaneously. As shown in FIG. 9, each scanning line has at least one interval, and the scanning speed is 30 to 100 IIJ.
It was varied within a range of Il/s, and blanking was performed as appropriate. The electron beam has an accelerating voltage of 10KV.

ビーム電流4mAで、高速偏向により疑似線状化したビ
ームを用いた。試料基板温度は600℃に加熱して実験
を行った。この方法により表面の均一な単結晶化層が得
られ、表面凹凸は500Å以下の平坦性を得た。また、
これにより移動度も 400・d/vs以下となり、従
来に比べて格段に優れた単結晶化層を得ることができた
A beam made pseudo-linear by high-speed deflection was used at a beam current of 4 mA. The experiment was conducted with the sample substrate heated to 600°C. By this method, a single crystallized layer with a uniform surface was obtained, and the surface unevenness was flat with a surface roughness of 500 Å or less. Also,
As a result, the mobility was also reduced to 400·d/vs or less, making it possible to obtain a single crystallized layer that was significantly superior to the conventional method.

かくして本実施例方法によれば、走査速度及び走査順序
等を適宜選択することにより、余熱効果の影響を著しく
小さくすることができ、均一な溶融φ再結晶化を行うこ
とができる。従って、絶縁膜上に大面積且つ良質な再結
晶化層を得ることが可能となり、3次元ICや積層構造
素子の実現に極めて有効である。また、電子ビームアニ
ール装るものではない。例えば、前記疑似線状ビームの
代りには、スポット(点状)ビーム或いは線状のビーム
を用いてもよい。また、半導体薄膜は多結晶シリコンに
限るものではなく、非晶質シリコンを用いることもでき
る。さらに、シリコンの代りにゲルマニウム、ガリウム
・砒素、インジウム・リン等の半導体を用いることも可
能である。
Thus, according to the method of this embodiment, by appropriately selecting the scanning speed, scanning order, etc., the influence of the residual heat effect can be significantly reduced, and uniform molten φ recrystallization can be performed. Therefore, it is possible to obtain a large-area, high-quality recrystallized layer on the insulating film, which is extremely effective for realizing three-dimensional ICs and laminated structure elements. Furthermore, it is not intended to be an electron beam annealing process. For example, instead of the pseudo-linear beam, a spot beam or a linear beam may be used. Further, the semiconductor thin film is not limited to polycrystalline silicon, but amorphous silicon can also be used. Furthermore, it is also possible to use semiconductors such as germanium, gallium/arsenic, indium/phosphide, etc. instead of silicon.

また、実施例では余熱効果の低減をはかっているが、こ
れとは逆に余熱効果を積極的に用いることも可能である
。この場合、比較的速い走査速度で照射領域のうち第1
0図に示す如くm本(2≦m)の走査線上を照射し基板
温度を上げて均一にした後、再度具なる走査線上も含め
てビーム照射し直すことも、走査速度及び走査順序を可
変とすることにより可能なことである。また、ビームの
走査順序及び走査速度は予め定めておく必要はなく、試
料表面の温度を検出する温度センサの検出信号に基づい
て、アニール温度が一定となるように自動制御するよう
にしてもよい。
Further, although the embodiment aims to reduce the residual heat effect, it is also possible to actively use the residual heat effect on the contrary. In this case, the first part of the irradiation area is scanned at a relatively fast scanning speed.
As shown in Figure 0, it is also possible to irradiate m scanning lines (2≦m) to raise the substrate temperature and make it uniform, and then irradiate the beam again, including the specific scanning lines, by changing the scanning speed and scanning order. This is possible by doing so. Furthermore, the beam scanning order and scanning speed do not need to be determined in advance, and may be automatically controlled so that the annealing temperature is constant based on a detection signal from a temperature sensor that detects the temperature of the sample surface. .

となるものである。さらに、単結晶以外に非晶質シリコ
ン層、大粒径多結晶シリコン層等の結晶性の異なる領域
を作成する場合にも適用可能である。
This is the result. Furthermore, it is also applicable to the case of creating regions with different crystallinity, such as an amorphous silicon layer, a large-grain polycrystalline silicon layer, etc. other than a single crystal.

その他、本発明の要旨を逸脱しない範囲で、種々変形し
て実施することができる。
In addition, various modifications can be made without departing from the gist of the present invention.

【発明の効果〕【Effect of the invention〕

以上詳述したように本発明によれば、電子ビームの走査
位置或いは走査速度を任意に可変制御することにより、
試料の表面のアニール温度分布の均一化をはかることが
でき、絶縁性基板上に形成する半導体単結晶層の結晶特
性の向上及び大面積化をはかることができる。
As detailed above, according to the present invention, by arbitrarily variably controlling the scanning position or scanning speed of the electron beam,
It is possible to make the annealing temperature distribution uniform on the surface of the sample, and it is possible to improve the crystal properties and enlarge the area of the semiconductor single crystal layer formed on the insulating substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第9図は本発明の一実施例方法を説明するた
めのもので第1図は同実施例方法に使用した電子ビーム
アニール装置を示す概略構成図、第2図はアニールする
試料の概略構造を示す断面図、第3図はアニール領域と
ビーム走査位置との関係を示す模式図、第4図は走査位
置に対するアニール温度分布を示す特性図、第5図乃至
第9図+1 は、そ1れぞれビーム走査順序及び各走査位置に対す”
−す るビ1.−ム走査速度を示す模式図、第10図は変形例
を説明するためのものでビーム走査順序及び各走査位置
に対するビーム走査速度を示す模式図、第11図及び第
12図は従来の問題点を説明するためのもので、第11
図はアニール領域とビーム走査位置との関係を示す模式
図、第12図は走査位置に対するアニール温度分布を示
す特性図である。 10・・・電子銃、11・・・集束レンズ、12・・・
試料、13・・・X偏向コイル、14・・・Y偏向コイ
ル、15・・・温度センサ、16・・・計算機、17・
・・バッファメモリ、18・・・X偏向ドライバ、19
・・・Y偏向ドライバ、21・・・Si基板、22・・
・絶縁膜、23・・・開口、24・・・多結晶Si膜、
25・・・保護膜、26・・・電子ビーム。 出願人 工業技術院長 飯塚 幸三 第1図 第2図 第3図 走表位!□ 第4図 第5図   第6図   第7図 第8図   19図   第10因 業月図 172図
1 to 9 are for explaining a method according to an embodiment of the present invention. FIG. 1 is a schematic configuration diagram showing an electron beam annealing apparatus used in the method of the embodiment, and FIG. 2 is a sample to be annealed. Figure 3 is a schematic diagram showing the relationship between the annealing region and the beam scanning position, Figure 4 is a characteristic diagram showing the annealing temperature distribution with respect to the scanning position, Figures 5 to 9 +1 are , respectively for the beam scanning order and each scanning position.
-B1. 10 is a schematic diagram showing the beam scanning speed for each scanning position, and FIG. 10 is a schematic diagram showing the beam scanning order and beam scanning speed for each scanning position. This is to explain the 11th
The figure is a schematic diagram showing the relationship between the annealing region and the beam scanning position, and FIG. 12 is a characteristic diagram showing the annealing temperature distribution with respect to the scanning position. 10... Electron gun, 11... Focusing lens, 12...
Sample, 13...X deflection coil, 14...Y deflection coil, 15...temperature sensor, 16...computer, 17.
...Buffer memory, 18...X deflection driver, 19
...Y deflection driver, 21...Si substrate, 22...
- Insulating film, 23... opening, 24... polycrystalline Si film,
25...Protective film, 26...Electron beam. Applicant Kozo Iizuka, Director of the Agency of Industrial Science and Technology Figure 1 Figure 2 Figure 3 Running position! □ Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 19 Figure 10 Figure 172

Claims (8)

【特許請求の範囲】[Claims] (1)絶縁性基板上に形成された多結晶若しくは非晶質
の半導体薄膜に、電子ビームを照射すると共に走査して
該薄膜を溶融・再結晶化する半導体単結晶層の製造方法
において、前記ビームの各走査位置におけるアニール温
度が一定となるように、該ビーム各走査線毎に走査位置
及び走査速度の少なくとも一方を指定することを特徴と
する半導体単結晶層の製造方法。
(1) A method for manufacturing a semiconductor single crystal layer, in which a polycrystalline or amorphous semiconductor thin film formed on an insulating substrate is irradiated with an electron beam and scanned to melt and recrystallize the thin film. A method for manufacturing a semiconductor single crystal layer, comprising specifying at least one of a scanning position and a scanning speed for each scanning line of the beam so that the annealing temperature at each scanning position of the beam is constant.
(2)前記走査位置を指定する手段は、少なくとも1本
の走査線間隔をおいてビーム走査することである特許請
求の範囲第1項記載の半導体単結晶層の製造方法。
(2) The method for manufacturing a semiconductor single crystal layer according to claim 1, wherein the means for specifying the scanning position is scanning the beam with an interval of at least one scanning line.
(3)前記走査速度を指定する手段は、ビーム走査の初
期時よりもビーム走査の後期時の方でビーム走査速度を
速くすることである特許請求の範囲第1項記載の半導体
単結晶層の製造方法。
(3) The semiconductor single crystal layer according to claim 1, wherein the means for specifying the scanning speed is to make the beam scanning speed faster in a later period of beam scanning than in an initial period of beam scanning. Production method.
(4)前記電子ビームの走査位置及び走査速度は、予め
メモリに記憶された情報に基づいて決定されることを特
徴とする特許請求の範囲第1項、第2項又は第3項記載
の半導体単結晶層の製造方法。
(4) The semiconductor according to claim 1, 2, or 3, wherein the scanning position and scanning speed of the electron beam are determined based on information stored in a memory in advance. Method for manufacturing single crystal layers.
(5)前記電子ビームの走査位置及び走査速度は、前記
半導体薄膜の温度を検出し、この検出温度に基づいて自
動制御されることを特徴とする特許請求の範囲第1項記
載の半導体単結晶層の製造方法。
(5) The semiconductor single crystal according to claim 1, wherein the scanning position and scanning speed of the electron beam are automatically controlled based on the detected temperature by detecting the temperature of the semiconductor thin film. Method of manufacturing layers.
(6)前記電子ビームの照射による半導体薄膜の再結晶
時に、同じ位置を2度以上繰返し走査可能としたことを
特徴とする特許請求の範囲第1項記載の半導体単結晶層
の製造方法。
(6) The method for manufacturing a semiconductor single crystal layer according to claim 1, wherein the same position can be repeatedly scanned twice or more during recrystallization of the semiconductor thin film by irradiation with the electron beam.
(7)前記電子ビームの照射による半導体薄膜の再結晶
時に、1回の再結晶時において、1走査終了毎にブラン
キング走査を行うことを特徴とする特許請求の範囲第1
項記載の半導体単結晶層の製造方法。
(7) When recrystallizing the semiconductor thin film by irradiating the electron beam, a blanking scan is performed every time one scan is completed during one recrystallization.
A method for manufacturing a semiconductor single crystal layer as described in 1.
(8)前記絶縁性基板として、単結晶半導体基板上に絶
縁膜を堆積したものを用いたこと特徴とする特許請求の
範囲第1項記載の半導体単結晶層の製造方法。
(8) The method for manufacturing a semiconductor single crystal layer according to claim 1, wherein the insulating substrate is a single crystal semiconductor substrate on which an insulating film is deposited.
JP62098733A 1987-04-23 1987-04-23 Method for manufacturing semiconductor single crystal layer Expired - Lifetime JPH0793263B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62098733A JPH0793263B2 (en) 1987-04-23 1987-04-23 Method for manufacturing semiconductor single crystal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62098733A JPH0793263B2 (en) 1987-04-23 1987-04-23 Method for manufacturing semiconductor single crystal layer

Publications (2)

Publication Number Publication Date
JPS63265421A true JPS63265421A (en) 1988-11-01
JPH0793263B2 JPH0793263B2 (en) 1995-10-09

Family

ID=14227712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62098733A Expired - Lifetime JPH0793263B2 (en) 1987-04-23 1987-04-23 Method for manufacturing semiconductor single crystal layer

Country Status (1)

Country Link
JP (1) JPH0793263B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745920A (en) * 1980-09-02 1982-03-16 Fujitsu Ltd Forming method for semiconductor single crystal by energy beam emission
JPS584257A (en) * 1981-06-30 1983-01-11 Toshiba Corp Scanning-type electron-beam annealing device
JPS60152020A (en) * 1984-01-19 1985-08-10 Fujitsu Ltd Annealing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745920A (en) * 1980-09-02 1982-03-16 Fujitsu Ltd Forming method for semiconductor single crystal by energy beam emission
JPS584257A (en) * 1981-06-30 1983-01-11 Toshiba Corp Scanning-type electron-beam annealing device
JPS60152020A (en) * 1984-01-19 1985-08-10 Fujitsu Ltd Annealing method

Also Published As

Publication number Publication date
JPH0793263B2 (en) 1995-10-09

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