JPS6326473B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for modulating a runlength limited code.
In particular, it is intended to reduce the DC component of the modulated digital signal.

The run-length limit code modulation method is based on the minimum inversion interval between two data transitions for “0” or “1” data.
This is intended to increase recording efficiency by increasing Tmin and to shorten the maximum inversion interval Tmax to facilitate self-clocking on the receiving (reproducing) side.

Furthermore, when modulating a digital signal, it is required to reduce the DC component (including low frequency component) of the modulated digital signal. One of the reasons for this is that in the case of magnetic recording and reproduction, the magnetic head integrates to obtain the reproduced waveform due to its differential response, but the original DC component is lost due to the integration, and the reproduced waveform is This is because it is not possible to determine a reference level when supplying data to a slicer to separate data. In reality, the reproduction signal is processed by a clamp circuit, making the reproduction circuit complex. In addition, during magnetic recording using a rotating magnetic head, the DC component is not transmitted because the data is transmitted through a rotating transformer, resulting in positive/negative asymmetry during recording and distortion, so it is still preferable to have a small DC component. . The above-mentioned problems caused by DC components are not limited to magnetic recording and reproduction;
This also occurs in rotating disks with optical reading. In addition, in such a rotating disk playback device, bits (indentations) corresponding to "0" or "1" of the digital signal are formed on the specular reflective surface, and are read by a laser beam focused on the reflective surface. ing. Using multiple sensors placed close to each other to read this,
Tracking information and focusing information can be obtained by calculating the outputs of a plurality of sensors. If the digital signal recorded on the rotating disk does not have a DC component,
Tracking information and focusing information can be obtained by supplying the outputs of the plurality of sensors described above to a low-pass filter and directly calculating the outputs. However, if the recorded digital signal has a DC component, the tracking information and focusing information obtained may be inaccurate, and peak detection must be performed independently for each sensor output. However, there is a disadvantage that the circuit scale of the reproduction system becomes large.

First, for the purpose of reducing the DC component, MM
(Modified Miller) code, ZM (Zero
Modulation) codes have been proposed. With these modulation methods, when recording with the NRNI method, the minimum magnetization reversal interval Tmin is 1T and the recording efficiency (Tmin/T) is 1, which is better than the recording efficiency of 0.5 in the case of PE (Phase Encoding), but The disadvantage is that the recording efficiency is lower than that of the run-length limited code.

The present invention has the advantage that run-length limited codes have high recording efficiency.
This paper aims to propose a run-length limited code modulation method that can reduce the DC component.

An embodiment of the present invention will be described below. A recording modulation system having the configuration shown in FIG. 1 is used for a recording system of a magnetic recording/reproducing machine or a master recording system for a rotating disk. In Figure 1, 1
indicates an input terminal to which input data is supplied, and 2
a to 2d are different combinations of 2 bits, i.e.
00, 01, 10, 11, redundant bit generator is shown, 3
A to 3d show multiplexers for adding redundant bits to each block of input data. The input data is processed so that a plurality of bits constitute one block, and the first two bits in each block are made data blank, so that redundant bits can be added thereto. Multiplexer 3a
3d select redundant bits from the redundant bit generators 2a to 2d during this data blank period and add them to the input bits. The number of bits in one block is determined by considering both the frequency of the low frequency component to be reduced and the redundancy. The number of redundant bits varies depending on the modulation method employed, but at least 2 bits are required.

Outputs containing redundant bits from multiplexers 3a-3d are input to run-length limited code modulators 4a-4d, and their modulated outputs are input to buffer memories 5a-5d and digital sum counters 6a-6d. The modulators 4a to 4d are
The specific configuration differs depending on the modulation method. However, in general, a combinational circuit (logic circuit, ROM, etc.) indicated by 11 in FIG.
It consists of registers 2 and 13, and input data appearing from register 12 and register 1.
By processing the previous modulation data appearing from 3 in the combinational circuit 11, "0" or "1" is generated.
is done to limit the number of consecutive The buffer memories 5a to 5d are for delaying the modulated data series for one block period required to detect the accumulated value of the digital sum, and the outputs of the buffer memories 5a to 5d are sent to the multiplexer 7.
is used as the input. In addition, the digital sum counter 6a
~6d is for accumulating the digital sum of modulated data from the beginning. The digital sum of the modulated data is set to 0 when a transition occurs in the center of the bit cell with respect to a bit cell of width T of the input data, and 1 when no transition occurs in the bit cell and is at a high level. If no transition occurs and the level is low, it is set to -1. The digital sum counters 6a to 6d are configured to perform an addition operation when the digital sum is 1, and perform a subtraction operation when it is -1.

The outputs of the digital sum counters 6a to 6d are supplied to a comparator circuit 8. The comparator circuit 8 detects the digital sum counter 6a to 6d whose accumulated value of digital sum is closest to 0 at the timing of the end of one block, controls the multiplexer 7, and controls the accumulated value of this digital sum. takes out the modulation data that is closest to 0 and leads it to the output terminal 9. At the same time, the contents of the registers 13 (see FIG. 2) of the modulators 4a to 4d are changed to the modulation data selected as output. Therefore, the modulator 4a
The contents of the registers 13 of 4d to 4d are supplied to the multiplexer 10, which, like the multiplexer 7, is controlled by the output of the comparison circuit 8, and the modulation data selected by the multiplexer 10 is sent to each modulator 4a to 4d. The register 13 is loaded.

The modulated data obtained at the output terminal 9 is recorded on a magnetic tape or the like. The configuration for reproducing and demodulating such modulated data is hardly complicated. In other words, it is sufficient to supply the modulated data to the demodulator and treat the two bits at the head of each block of the demodulated output as redundant bits so as to be ignored.

The applicant previously proposed this as one of the run-length limited codes (Tmin=1.5T,
The present invention will be further explained in detail by taking as an example the case where Tmax=4T).

In this modulation method, first, when a bit of input data of a binary code changes from a second value to a first value, it is inverted at a first reference point of a bit cell of the input data. In the following description, the first value is taken as a high level (“1”), the second value is taken as a low level (“0”), the first reference point of the bit cell is taken as its center,
The second reference point is the boundary. However, these relationships are completely equivalent even if they are replaced. The above conversion rule is similar to NRZI, so it is not sufficient to use it alone.As is clear from the case where “1” is continuous, (Tmin=
T), and if "0" continues, Tmax is obviously not limited. Therefore,
When “1” is continuous, the above conversion rule is modified to be (Tmin=1.5T), and when “0” is continuous, this conversion rule is modified to be (Tmax=1.5T).
4T).

Each of Figures 3 and 4 shows the conversion rules, and the time charts included in each figure show the input data and the converted transmission waveform, and the converted data is "1". It is assumed that an inversion occurs at the leading edge of the 0.5T bit cell in the case of 0.5T. Of course,
In the case of "1", inversion may occur at the trailing edge.

As shown in FIG. 3A, in the case of input data of 010, inversion occurs at the center of "1" as described above. When there are two consecutive “1”s, that is, 0110, an inversion occurs at the center of the first “1” and an inversion occurs at the boundary after the next “1” as shown in Figure 3B. let At this time, the reversal interval is 1.5T (=
Tmin). Even when 01110 and three "1"s occur in succession, as shown in FIG. 3C, an inversion occurs at the center of the first "1" and an inversion occurs at the boundary after the last "1". In this case, the reversal interval is
It becomes 2.5T. In addition, when there are four or more consecutive "1" bits, the consecutive bits are divided into two bits at the boundary of the bit cell, and if there is a remainder as a result of this division, the consecutive "1" bits are separated. The 5 bits before the first “0” bit after the
Separate the bit and the following two bits by a boundary,
Causes the inversion to occur at the boundary after this break.

As shown in Figure 3D, Figure 3F, Figure 3H, and Figure 3J, it is possible to divide every 2 bits without any remainder so that 4, 6, 8, or 10 "1"s are consecutive. If possible, the inversion interval for the first 2 bits will be 1.5T, and all other 2 bits will be
In terms of bits, this is 2T. Also, as shown in Figure 3E, if there are five consecutive 1's, they are divided into 3 bits and the following 2 bits according to the above rules, and the inversion interval of the first 3 bits is set. 2.5T, and the inversion interval of the latter 2-bit unit becomes 2T. Furthermore, as shown in Figure 3G, Figure I, and Figure K, respectively, 7 pieces, 9 pieces, and
If there are 11 consecutive "1's", there will be a remainder when dividing in units of 2 bits, so the 5 bits before the first "0" bit are divided into 3 bits and the following 2 bits. Separate at boundaries and cause inversion at each subsequent boundary.

As above, the minimum reversal interval Tmin is set to 1.5T.
It can be done. Furthermore, the maximum reversal interval that appears when "1"s occur continuously is 3T. What should be noted here is that an inversion interval of 3T (or 2.5T) occurs for the previous 3 bits of the last (or all) 5 bits in the continuous "1" bit pattern, so the 3T The reversal interval after (or 2.5T) is always 2T. Next “0”
A conversion rule applied to a continuous pattern, that is, a rule that can limit the maximum inversion interval Tmax to 4T, will be explained with reference to FIG. 01 and 001 as shown in Figure 4A and Figure 4C
If the previous two bits are 01, an inversion occurs at the center of "1", as understood from the above explanation.
In addition, as shown in Figure 4B and Figure 4D, 01 and
If the two bits before 001 are 11, an inversion occurs at the boundary after the "1". 4E and below show the transmission waveform when the two bits before the consecutive "0" are 01, and the transmission waveform when the two bits are 11 are shown with broken lines.

If two or more consecutive “0”s occur, the bit cells are inverted at a boundary that satisfies the fact that they are 3T or more from the previous inversion, for example 3T, and 1.5T or more from the center of the first “1” that appears after. It is done so as to cause As shown in Figure 4E, “0”
When there are three successive numbers, the above condition is not satisfied, so a reversal occurs at the center of "1", and the reversal interval 4T at this time becomes the maximum reversal interval Tmax, and
It is only in this case that Tmax occurs. Fourth
As shown in Figure F, Figure G, and Figure H, if there are 4, 5, and 6 consecutive 0's, the above condition is satisfied and 3.5T (or 3T) is reached from the previous reversal. The reversal occurs at a distance of . Also, Figure 4 I
As shown in , if there are 7 consecutive “0”s,
A reversal occurs once at an interval of 3.5T (or 3T), and a reversal occurs at a position of 3T from this intermediate reversal. “0” is
In the case of 15 consecutive pieces, as shown in Figure 4 J,
Four degrees of reversal will occur during the succession.
Furthermore, as shown in FIGS. 4K and 4L, respectively,
When 16 and 17 "0"s occur consecutively, a 5 degree reversal occurs during the succession.

As explained above, no matter how many “0”s are in a row,
The maximum reversal interval Tmax will be limited to 4T. As can be seen from FIG. 4, even when "0"s occur continuously, 3T appears as an inversion interval, similar to when "1s" occur continuously. Therefore, when decoding, it seems impossible to distinguish between continuous "0" and continuous "1". but,
A reversal interval of 2T never appears after the reversal interval of 3T that occurs in the case of continuous “0”, and other reversal intervals of 1.5T, 2.5T, 3T, 3.5T appear, whereas ``3T that occurs in the case of continuous
After a reversal interval of , a reversal interval of 2T always appears as mentioned above. This difference can be used for decoding.

In this way, the minimum reversal interval is 1.5T,
Binary codes can be converted so that the maximum inversion interval is 4T. The recording efficiency of this modulation method is (1.5T/T)=1.5. Therefore, the recording efficiency is superior to the ZM code and MM code, which have been proposed for the purpose of reducing DC components.

How the DC component is reduced when the modulators 4a to 4d in one embodiment of the present invention use the above modulation method will be explained with reference to FIG. In the example shown in FIG. 5, the number of bits in one block is 18, the input data of one block is 16 bits, for example 1010101110111100, and the 4 bits of input data of the previous block are 1101. Two redundant bits each of 00, 01, 10, and 11 are added to the boundaries between these two blocks, and the modulators 4a to 4a.
4d, the modulation data obtained by supplying the modulated data to FIG. 5A to FIG. 5D are shown, respectively. It is clear from the above conversion rules that such modulated data can be obtained. For each bit cell of input data, 0 when a transition occurs at the center of the bit cell;
Since the digital sum is defined as -1 when this is a low level and +1 when this is a high level, the fifth
The digital sum of one block shown in each of Figures A to D is +3, -1, -1, -2. Now, assuming that the cumulative value of the digital sum up to the previous block is +4, the cumulative value of the digital sum at the end of one block will be +7, +3, +3, and +2, respectively. Therefore, the cumulative value of the digital sum of the modulated data obtained by adding 11 as a redundant bit to the input data is closest to 0 compared to other modulated data. This is detected by the comparator circuit 8, and the modulated data shown in FIG. At the same time, the modulation data shown in FIG. 5D stored in the register of the modulator 4d is transferred to the multiplexer 10.
and loaded into the registers of modulators 4a, 4b, 4c.

As understood from the above description, according to the present invention, the digital sum of modulated data obtained at the output terminal 9 can be made as close to 0 as possible, and the DC component included in the modulated data can be reduced. . Therefore, as mentioned at the beginning, it is easy to determine the reference level for separating the reproduced data, and it is also possible to reduce distortion when transmitting through a rotating transformer. Sometimes it becomes easier to obtain tracking and focusing information.

Furthermore, in the present invention, since redundant bits are added to the input data to reduce the DC component before modulation, the minimum inversion interval Tmin of the modulated data obtained as output is the same as that of the run-length limited code ( In the above example, Tmin=
1.5T). Therefore, the advantage of high recording efficiency is not lost in any way. Furthermore, in the present invention, although the configuration on the modulation side is complicated, the configuration on the demodulation side is hardly complicated. Therefore, the present invention can be applied to a recording/reproducing system using a rotating disk. suitable.

The present invention can be similarly applied to the 3PM system. As shown in Figure 6, the 3PM method converts a 3-bit data word into a 6-bit code word, and converts adjacent "1"s into 6-bit code words.
The conversion is performed so that at least two "0"s are present between the two. In the 3PM method, the minimum reversal interval Tmin and maximum reversal interval Tmax are (Tmin=
1.5T) (Tmax=6T). In addition, in the conversion rule shown in FIG. 6, if the value becomes 101 at the boundary between two code words, it is converted to become 010.

The present invention can also be applied to such a 3PM system. As in the case of Fig. 5, one block is made up of 18 bits, and the input data of one block is made 16 bits such as 1010100110010000, and redundant bits of 00, 01, 10, and 11 are added to this to create 3PM.
The modulation data obtained by performing modulation of
The figures are shown in D of the same figure. In the 3PM system, one block containing redundant bits is divided into three bits from the beginning, and code conversion is performed based on the conversion rules shown in FIG. Now, assume that the cumulative value of the digital sum up to the previous block (the last 4 bits are 1101) is +4. Since the digital sums of each block in FIGS. 7A to 7D are +5, -5, +2, and -5, the cumulative values of the digital sums detected at the end of this one block are -9 and -9, respectively. -1, +6, -1. Therefore, one of the modulated data shown in FIG. 7B or FIG. 7D where this becomes -1 is selected by the multiplexer 7 and output. At the same time, the selected modulation data is loaded into the registers of the modulators 4a to 4d.

In this way, even when the present invention is applied to the 3PM system, the DC component can be reduced. Of course, Tmin and Tmax of the 3PM method are equal to the original ones. Unlike the 3PM method, 4 bits are converted to 12 bits, and at least 5 “0”s are inserted between adjacent “1”s.
The present invention can also be applied to a modulation method such as (Tmin=2T, Tmax=8.33T).

In addition, as another example of a configuration for detecting the accumulated value of the digital sum that is closest to 0, it is assumed that the digital sum counters 6a to 6d in FIG. 1 detect the digital sum for each block, and the output An arrangement can be made in which a digital sum counter for detecting the cumulative value of the digital sum is provided at the terminal 9, and a block of digital sums having a different polarity and the closest absolute value to the cumulative value of the digital sum counter is detected. Also,
If the number of redundant bits is three or more, the DC component can be reduced more reliably.

Furthermore, as a run length limited code,
Similar to the previous example, (Tmin=1.5T,
The applicant has also proposed one in which Tmax=4.5T). In this modulation method, when the bit of input data of binary code changes from "0" to "1",
Invert the input data at the center of the bit cell, and if the input data includes a pattern of consecutive "1" bits, convert these consecutive bits into 2 or 3 bits.
Each bit is divided at the boundary of the bit cell mentioned above, and an inversion is caused at the boundary after this division, and when the input data includes a pattern of consecutive "0" bits, 3.5T (however, T The inversion is caused at a boundary that satisfies the condition that is longer than the bit cell period of the input data and that it is 1.5T or more away from the center of the first "1" that appears later.

The present invention can be applied to such run-length limited codes in exactly the same way.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a configuration used to implement the present invention, FIG. 2 is a block diagram used to explain a modulator, and FIGS. 3 and 4 are run length limit diagrams to which the present invention can be applied. FIG. 5 is a schematic diagram used to explain the rules for converting the ID code, FIG. 5 is a schematic diagram used to explain the case where the present invention is applied to this run-length limited code, and FIG. FIG. 7 is a schematic diagram used to explain the application of the present invention to the 3PM system. 1 is an input terminal, 2a to 2d are redundant bit generators, 3a to 3d, 7, and 10 are multiplexers, 4
a to 4d are modulators, and 6a to 6d are digital sum counters.

Claims (1)

[Claims] 1. A plurality of redundant bits each consisting of 2 or more bits and having different combinations are prepared, and each of the plurality of redundant bits is applied to one block of data consisting of a predetermined number of bits. 1. A run-length limited code modulation method, characterized in that modulation is performed after the modulation is performed, and the one whose cumulative value of digital sum is closest to zero is selectively outputted from among the respective modulated outputs.