JP3668982B2 - Data demodulator - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a data demodulating device and a data demodulating method for demodulating input data from data modulated by run length modulation or the like and having synchronization data inserted therein, and an optical recording medium using these data demodulating device and data demodulating method TECHNICAL FIELD
[0002]
[Prior art]
When data is recorded on a recording medium such as a magnetic disk, the input data is modulated (encoded) and recorded in order to improve the error rate. As the encoding method, for example, a run length modulation method (run length encoding method) disclosed in Japanese Patent Publication No. 63-7051 (corresponding US Pat. No. 4,413,251) is known. Yes.
This run-length modulation method is called run-length limited (1, 7) modulation (hereinafter referred to as “RLL (1, 7) encoding”), The number of consecutive numerical values 0 in the data is limited to a range of 1 to 7, and 2-bit input data is encoded into 3-bit encoded data.
[0003]
RLL (1, 7) encoding generates encoded data by sequentially performing a predetermined logical operation on input data of 2 bits for each encoding period and state data indicating the state of the previous period. To do.
The encoded data in each encoding period of the encoded data sequence sequentially encoded by RLL (1, 7) encoding is encoded data after 2 encoding periods of 3 bits, 1 encoding period of 3 bits. Demodulation (decoding) is performed by performing a predetermined logical operation on the later encoded data and 1-bit encoded data of the encoding cycle.
[0004]
  that's allIn the encoded data by the described RLL (1, 7) encoding, the propagation of data error due to random noise is as small as 5 bits or less.
  Furthermore, RLL (1, 7) encoding and decoding of encoded data by RLL (1, 7) encoding (RLL (1, 7) decoding) require hardware necessary for executing these. It is extremely simple and is suitable for high-speed encoding operation and high-speed decoding operation.
[0005]
[Problems to be solved by the invention]
  However, in order to decode the encoded data encoded by the RLL (1, 7) encoding, not only the encoded data of the encoding period but also the encoded data of the encoding period after the encoding period Must be used.
  This means that decoding cannot be performed unless there is further known data (additional data) after the last encoded data.
  That is, additional data is required between the synchronous data and the encoded data, and the recording capacity of the recording medium required for recording the additional data cannot be ignored.
  On the other hand, when the encoded data is recorded on a recording medium such as a magneto-optical disk, the synchronization data (resynchronization data) necessary for taking the timing when demodulating the encoded data is inserted into the encoded data. It is necessary to keep. Although this synchronization data depends on the recording format of the recording medium, for example, 1 byte is required for 20 bytes of encoded data as a value before encoding.In addition to the first synchronous data before the encoded data, re-encoded data similar to the synchronous data is inserted for each predetermined encoded data, for example, a timing shift occurs in the middle of the encoded data. However, the subsequent encoded data can be normally encoded.
[0006]
  The present invention has been made in view of the above-described problems of the prior art, and the encoded data encoded by a method in which encoded data of a plurality of encoding periods such as run-length encoding have a predetermined relationship is used. Insert sync dataDeDataCan be demodulated accurately and effectively with a simple circuit configurationAn object of the present invention is to provide a data demodulating device, a data demodulating method, and a data reproducing device using the same.
  The present invention also provides a data demodulating apparatus and a data demodulating method capable of effectively using a storage area of a recording medium without using additional data between encoded data and synchronous data, and using the same An object is to provide a data reproducing apparatus.
[0007]
  According to a first aspect of the present invention, synchronizationsignalTo the modulated data generated by RLL (1, 7) modulation of the original data to be modulated except forsignalRLL (1, 7) is demodulated to insert the data insertedsignalA data demodulator for demodulating original data excluding
  Demodulation means for demodulating RLL (1, 7);
  Synchronization of the recorded datasignalDetect and syncsignalThe detected synchronization whensignalSubstantially stops the demodulating operation of the demodulating means at the timing when it is input to the demodulating means,signalDemodulation control means for causing the demodulation means to perform an RLL (1, 7) demodulation operation only when the modulation data obtained by modulating the original data except for is input to the demodulation means;
  Have
  RLL (1, 7) demodulation of only the modulated data,
  A data demodulator is provided.
[0008]
  According to a second aspect of the present invention, a synchronization signal, a plurality of RLL (1, 7) modulated encoded data, and a predetermined number of the encoded data are inserted.SameA data demodulator for demodulating the encoded data by performing RLL (1, 7) demodulation on data to be demodulated including a period signal,
  PreviousDescriptionWhen a period signal is detected, a synchronization detection signal of the first logic signal is generated,DescriptionWhen no signal is detected, a synchronization detection signal of the second logic signal is generatedSameA period detection circuit;
  A control circuit that outputs first to fourth encoding period control signals according to the encoding period;
  A first register that inputs the demodulation target data and shifts the input demodulation target data by 3 bits according to the first encoding cycle control signal only when the logic of the synchronization detection signal is the first logic. When,
  The output data of the first register is input, and the output data of the input first register is shifted by 3 bits according to the second encoding cycle control signal only when the logic of the synchronization detection signal is the first logic. A second register;
  The output data of the second register is input, and the output data of the input second register is shifted by 3 bits according to the third coding cycle control signal only when the logic of the synchronization detection signal is the first logic. A third register;
  A decoding circuit that performs RLL (1, 7) decoding based on the output data of the first to third registers;
  A fourth register for inputting the output data of the decoding circuit and shifting and outputting the input data in accordance with the fourth encoding cycle control signal;
  Have
  The decoding circuit includes:
    A first OR circuit for calculating an OR of 3-bit data output from the first register;
    A second OR circuit that calculates an OR of the 3-bit data output from the second register and the 1-bit data output from the third register;
    An inverting circuit for inverting the sign of the least significant bit data of the 3-bit data output from the second register;
    A NOR circuit for calculating NOR of 3-bit data output from the second register;
    A third OR circuit that calculates the OR of the output signal of the NOR circuit and the most significant bit data of the 3-bit data output from the second register, and outputs lower-order state data;
    A NAND circuit that computes a NAND of the output signal of the first OR circuit, the output signal of the second OR circuit, and the output signal of the inverting circuit and outputs high-order state data;
    Having
    A data demodulator is provided.
[0009]
[Action]
  The data demodulator according to the present invention provides synchronization data (so-called resynchronization data) required for taking the timing when reproducing the input data to the modulated data obtained by RLL (1, 7) modulation of the input data. Is insertedDeThe input data is reproduced from the data by a predetermined demodulation method (RLL (1, 7) demodulation).
  In the data demodulating device of the present invention, the demodulation control means detects the synchronization data from the recorded data, and stops the demodulation operation of the demodulation means at the timing when the synchronization data is input to the demodulation means. As a result, only the modulated data obtained by removing the synchronization data from the recording data is input to the demodulating means.
  The demodulating means demodulates only the input modulation data and reproduces the input data under the control of the demodulation control means.
[0010]
  The modulation data obtained by RLL (1, 7) modulation is characterized in that additional data of 4 bits (6 bits as data after modulation) is required as data before modulation for demodulation of the last modulation data. Therefore, when demodulating the recording data without taking care as in the data demodulating device of the present invention, it is necessary to put additional data between the modulation data and the synchronization data.
  The data demodulator of the present inventionFor example, including modulation data and synchronization data read from a recording mediumOf the recorded data, the demodulation means performs RLL (1, 7) demodulation only when the modulation data is input to the demodulation means, and when the synchronization data is input, the demodulation means RLL (1, 7). The demodulating operation is stopped, and the modulation data that is substantially divided and recorded in each data area is handled as a continuous series of data, thereby making additional data unnecessary.
[0011]
【Example】
Hereinafter, the configuration of a data modulation device, a data demodulation device, and a data recording / reproducing device using these will be described with reference to the drawings.
First, the configuration of the data recording / reproducing apparatus 1 of the present invention will be described with reference to FIG.
FIG. 1 is a diagram showing the configuration of the data recording / reproducing apparatus 1.
As shown in FIG. 1, the data recording / reproducing apparatus 1 includes a disk system 10, a control device (DSC) 18, a data recording device 20, and a data reproducing device 40.
[0012]
  The data recording / reproducing apparatus 1 uses the run length limited (1, 7) modulation of the input data ID input at a certain period (modulation timing, hereinafter referred to as “encoding period”). The encoded data obtained by modulating (encoding) by modulation (hereinafter referred to as “RLL (1,7) encoding”)(1,7) Add non-modulated synchronization data and resynchronization dataEncoded data recorded on the magneto-optical disk 12 and recorded on the magneto-optical disk 12With synchronization and resynchronization dataIs read from the magneto-optical disk 12 and demodulated (decoded).
[0013]
The magneto-optical disk 12 is a magneto-optical disk from which data is read and written using laser light and magnetism. The recording format of the magneto-optical disk 12 will be described later with reference to FIGS.
The disk system 10 includes a disk drive system 14 and an optical system 16.
The disk drive system 14 rotates the magneto-optical disk 12 under the control of the control device 18.
The optical system 16 includes a laser diode (LD) 38 and a light detection element (RFD) 42, and performs data writing and reading with respect to the magneto-optical disk 12.
[0014]
Based on the control data designating the operation of the data recording / reproducing apparatus 1 and the synchronization detection signal (signal SRDS) detected by the synchronization detection circuit (SRD) 46, the control device 18 controls each control signal (signal DGC, DSAC, Each component of the disk system 10, the data recording device 20, and the data reproducing device 40 is controlled via (WCEC, SRGC, DC, RCEC).
The setting terminal 186 outputs control data set by the user of the data recording / reproducing device to the control device 18.
[0015]
  The data recording device 20 includes a data input circuit (WDI) 22, an ECC encoder (WECCE) 24, a data encoding circuit (WCE) 30, a synchronization signal generation circuit (SRG) 32, a data selection circuit (DSB) 34, and a laser. A drive circuit (WAMP) 36 is included.
  The data recording device 20 encodes the input data ID by RLL (1, 7) encoding to generate encoded data, adds the synchronization data and the resynchronization data, and passes the laser diode 38 through the magneto-optical disk. 12 is recorded. The configuration and operation of the data encoding circuit 30 will be described later with reference to FIGS..
[0016]
The data reproducing device 40 includes a reproduction signal amplification circuit (RAMP) 44, a synchronization detection circuit (SRD) 46, a data decoding circuit (RCE) 50, an ECC decoder (RECCD) 52, and a decoded data output circuit (RDI) 54. Is done.
The data reproduction device 40 detects the encoded data from the reproduction signal (signal RF) input from the light detection element 42, further demodulates (decodes) (decodes RLL (1, 7)), and inputs the input data ID. Reproduce. The configuration and operation of the data decoding circuit 50 will be described later with reference to FIGS.
[0017]
Hereinafter, the configuration and operation of the data encoding circuit 30 will be described with reference to FIGS.
FIG. 2 is a diagram showing a configuration of the data encoding circuit 30 shown in FIG.
FIG. 3 is a diagram showing a configuration of the encoding circuit (WCEL) 310 shown in FIG.
As shown in FIG. 2, the data encoding circuit 30 includes a first register (WCERA) 300, a second register (WCERB) 302, an encoding circuit 310, and a third register (WCERC) 304.
The data encoding circuit 30 performs RLL (1, 7) encoding on the signal WES generated by adding an error correction code (ECC) by the ECC encoder 24 to the input data ID input via the data input circuit 22. Encode.
[0018]
As shown in FIG. 3, the encoding circuit 310 includes logic circuits 312, 314, 316, 318, 320, 322, 324, 326, 328, 330, and logic circuits (A) 314, 320, 322. , 326 and 330 calculate the logical product (AND) of the input signals, and the logic circuits (I) 312 and 324 invert the logical values of the input signals, respectively. 328 calculates an inverted logical sum (NAND) for each input signal, and a logic circuit (NOR) 316 calculates an inverted logical sum (NOR) of the input signals.
[0019]
  Hereinafter, the operation of the encoding circuit 310 will be described with reference to FIGS. 2 and 3.
  Serial format recording targetThe signal WES is input to the register 300 serially (serially) bit by bit from the ECC encoder 24 for each signal period.
  Register 300 isFirstAccording to the control of the control device 18 via the control signal WCECa,Recording targetEach time the signal WES is shifted and the signal WES is input by 2 bits (every encoding period), two 1 bitsStatusData s0 and s1 are output to the encoding circuit 310 at each encoding cycle.
  Register 302 isSecondAccording to the control of the control device 18 via the control signal WCECb, the 3-bit state data x2 ′, x1 ′, x0 ′ generated by the encoding circuit 310 in the immediately preceding encoding cycle is stored for each encoding cycle, Data x2, x1, and x0 are output to the encoding circuit 310.
[0020]
  Hereinafter, the operation of the encoding circuit 310 will be described.
  The logic circuit 312 inverts the logic value of the state data x2 input from the register 302 and outputs the result to the logic circuit 314.
  The logic circuit 314 calculates the logical product of the inverted state data x2 input from the logic circuit 312 and the state data x1, and outputs the logical product to the register 304 as encoded data y2 '.
  The logic circuit 316 calculates the inverted OR of the state data x2 and x1 and outputs the result as encoded data y1 'to the register 304.
  The logic circuit 318 calculates an inverted OR of the 1-bit data s1 and s0 and outputs the result to the logic circuit 320.
[0021]
  The logic circuit 320 is 1 bit input from the logic circuit 318.StatusA logical product of the inverted logical product of the data s1 and s0 and the state data x0 is calculated and output to the register 304 as encoded data y0 '.
  The logic circuit 322 includes the status data x0 and 1 bit.StatusThe logical product with the data s0 is calculated and output to the register 304 as the state data x2 'of the encoding cycle.
  The logic circuit 324 inverts the logic value of the state data x0 and outputs it to the logic circuit 324.
[0022]
  The logic circuit 326 includes the state data x0 whose logic value is inverted and 1 bit.StatusThe logical product with the data s0 is calculated and output to the register 304 as the status data x1 'of the encoding cycle.
  The logic circuit 328 includes status data x0 and 1 bit.StatusAn inverted logical product with the data s0 is calculated and output to the logic circuit 330.
  The logic circuit 330 includes a signal input from the logic circuit 328 and 1 bit.StatusA logical product with the data s1 is calculated and output to the register 304 as the state data x0 'of the encoding cycle.
[0023]
  The register 304 is input from the control device 18.ThirdAccording to the control signal WCECc, the encoded data y2 ′, y1 ′, y0 ′ generated in the encoding cycle is stored, and converted into serial data in the order of the encoded data y0, y1, y2 in the next encoding cycle. And output to the data selection circuit 34.
  Input from the ECC encoder 24 by the operation of each part of the data encoding circuit 30 described above.Recording targetThe signal WES is encoded into 3-bit encoded data by 2 bits for each encoding cycle and is output to the data selection circuit 34.
[0024]
  The configuration and operation of the data decoding circuit 50 will be described below with reference to FIGS.
  FIG. 4 is a diagram showing a configuration of the data decoding circuit 50 shown in FIG.
  FIG. 5 is a diagram showing a configuration of the decoding circuit (RCEL) 510 shown in FIG.
  As shown in FIG. 4, the data decoding circuit 50 includes a fourth register (RCERA) 500, a fifth register (RCERB) 502, a sixth register (RCERC) 504, a seventh register (RCERD) 506, and a decoding. The circuit 510 is configured.
  The data decoding circuit 50 detects the laser beam reflected from the magneto-optical disk 12 by the photodetecting element 42, and the reproduction signal amplification circuit 44 amplifies the signal RF generated by discriminating it into binary and discriminates it into binary.ReadEach time 3 bits of signal RASA are input (every encoding cycle), 3 bits ofReadThe signal RASA is decoded into 2-bit data.
[0025]
As shown in FIG. 5, the decoding circuit 510 is composed of logic circuits 512, 514, 516, 518, 520, and 522, and the logic circuit (NOR) 512 calculates an inverted logical sum (NOR) of the input signal. The logic circuits (OR) 514, 516, and 520 calculate the logical sum (OR) of the input signals, and the logic circuit (I) 518 inverts the logical value of the input signal. (NAND) 522 calculates the inverted logical product (NAND) of the input signal.
[0026]
  Hereinafter, the operation of the data decoding circuit 50 will be described with reference to FIGS.
  Reading to be decryptedThe signal RASA is sequentially input to the register 500 of the data decoding circuit 50 serially by one bit for each signal period.
  Register 500 isFirstControl of the control device 18 via the control signal RCECa, andSync detectionInput according to logic value of signal SRDSReadThe signal RASA is sequentially shifted, and is output to the decoding circuit 510 and the register 502 for each encoding period as 3-bit encoded data y0 ″ ′, y1 ″ ′, y2 ″ ′ in the order of input.
  As described later, the logical value of the synchronization detection signal SRDS is 1 when a resynchronization signal is detected, and is 0 when a resynchronization signal is not detected. As will be described later, the register 500 performs the above-described shift operation when the logical value of the synchronization detection signal SRDS is 1, and the synchronization detection signal SRDS when the logical value of the synchronization detection signal SRDS is 0. The data stored in the register 500 is held as it is at the falling point.
[0027]
  Register 502 isThirdControl of the control device 18 via the control signal RCECb, andSync detectionIn accordance with the logical value of the signal SRDS, the 3-bit encoded data input for each encoding cycle is stored, and the 3-bit encoded data y2 ″, y1 ″, y0 ″ is stored in the decoding circuit 510 in the next encoding cycle. On the other hand, it outputs to the register 504 as encoded data y0 ″.
  Register 504ThirdControl of the control device 18 via the control signal RCECc, andSync detectionAccording to the logical value of the signal SRDS, the encoded data y0 ″ ′ input from the register 502 is stored for each encoding period, and is output to the decoding circuit 510 as 3-bit encoded data y0 ′ in the next encoding period. To do.
[0028]
  These registers 500, 502, and 504 are input from the synchronization detection circuit 46, as will be described later with reference to FIG.Sync detectionWhen the logical value of the signal SRDS is 1,shiftPerform the actionSync detectionWhen the logical value of the signal SRDS is 0, the data stored in the registers 500, 502, and 504 are held as they are and output to the decoding circuit 510 at the falling point of the signal SRDS. By this operation, the data decoding circuit 50Sync detectionWhen the signal SRDS is a logical value 1, that is, when encoded data is input to the data decoding circuit 50, a normal RLL (1, 7) decoding operation is performed,Sync detectionWhen the signal SRDS has a logical value of 0, that is, when synchronization data or resynchronization data is input to the data decoding circuit 50, the decoding operation is stopped.
[0029]
  The logic circuit 512 calculates the inverted logical sum of the input encoded data y2 ″, y1 ″, y0 ″ and outputs the result to the logic circuit 514.
  The logic circuit 514 calculates a logical sum of the encoded data y2 ″ and the inverted OR of the encoded data y2 ″, y1 ″, y0 ″ input from the logic circuit 512.First stateThe decoded data s0 is output to the register 506.
[0030]
The logic circuit 516 calculates a logical sum of the input encoded data y2 ″ ′, y1 ″ ′, y0 ″ ′ and outputs the logical sum to the logic circuit 522.
The logic circuit 518 inverts the logic value of the input encoded data y0 ″ and outputs it to the logic circuit 522.
The logic circuit 520 calculates a logical sum of the input encoded data y2 ″, y1 ″, y0 ″ and outputs the logical sum to the logic circuit 522.
[0031]
  The logic circuit 522 includes a logical sum of the encoded data y2 ″ ′, y1 ″ ′, y0 ″ ′ input from the logic circuit 516, encoded data y0 ″ obtained by inverting the logical value input from the logic circuit 518, and Calculate the inverted logical product of the logical sum of the encoded data y2 ″, y1 ″, y0 ″ input from the logic circuit 520.Second stateThe decoded data s1 is output to the register 506.
[0032]
  The register 506 is input from the control device 18.4thIn accordance with the control signal RCECd, the decoded data s1 and s0 input from the decoding circuit 510 are stored for each encoding period, and in the next encoding period, the serial dataDecryptionThe signal RCS is output to the ECC decoder 52.
  By the operation of each part of the data decoding circuit 50 described above, the reproduction signal amplification circuit 44 amplifies the signal RF generated by detecting the laser beam reflected from the magneto-optical disk 12 by the light detection element 42 into a binary value. IdentifiedReadOf signal RASA, Except sync signal and resynchronization signal,Only the portion corresponding to the encoded data is decoded into 2-bit decoded data by 3 bits for each encoding period and output to the ECC decoder 52.
  Here, from the data decoding circuit 50DecryptionThe decoded data s1 and s0 output as the signal RCS are sent to the data encoding circuit 30.Recording targetThis is the same as the two 1-bit data s1 and s0 input as the signal WES.
[0033]
Hereinafter, the recording format of the magneto-optical disk 12 will be described with reference to FIG. 6, FIG. 7, and FIG.
FIG. 6 is a diagram showing sectors of the magneto-optical disk 12 shown in FIG.
FIG. 7 is a diagram showing the recording format of the sector of the magneto-optical disk 12 shown in FIG. 6, where (A) shows the recording format of the sector 120, and (B) shows the ID1 area shown in (A). The recording formats of (ID1) 128, ID2 area (ID2) 134, and ID3 area (ID3) 140 are shown. In FIG. 7, the recording capacity of each area of the magneto-optical disk 12 indicates the capacity of data before RLL (1, 7) encoding.
FIG. 8 is a diagram showing the configuration of the data area 148 shown in FIG.
[0034]
As shown in FIG. 6, the magneto-optical disk 12 is divided into a channel 1 recording area 180 and a channel 2 recording area 182 each having a plurality of tracks, and each track is divided into 42 sectors 120.
[0035]
Data is recorded in each sector 120 in accordance with a recording format as shown in FIG.
The sector 120 is composed of a 52 byte address part (precoded) formed in advance on the magneto-optical disk 12, a 21 byte ALPC area 144, an 18 byte VFO4 area 146, and a 2,978 byte data area 148. The
The address part includes a 5-byte sector mark area 122, a 12-byte VFO1 area 124, an 8-byte VFO2 area 130, an 8-byte VFO3 area 136, a 1-byte AM1 area 126, an AM2 area 132, an AM3 area 138, and ID1. An area 128, an ID2 area 134, and an ID1 area 140 are configured.
[0036]
The ID1 area 128, ID2 area 134, and ID3 area 140 (hereinafter, these areas are collectively referred to as “ID area”) have a recording format as shown in FIG.
The ID area is composed of a 2-byte track number area 160, a 1-byte sector number area 162, and a 2-byte CRC area 164.
[0037]
As shown in FIG. 8, the data area 148 includes a sync signal area (SB1 to SB3) 170, a data area (areas D1 to D1024 in which 104 rows of data are recorded, and areas P1, 1 in which DM pointers are recorded. ~ P3,4, areas C1 to C4 where CRC codes are recorded, areas E1,1 to E10,16) 172 where ECC codes of 16 rows are recorded, and resynchronization signal areas (RS1 to RS59) 174 The configuration is repeated alternately. The data recorded in the data area 148 is logically handled as data having the configuration shown in FIG.
[0038]
  Data recorded in the main area of the sector 120 of the magneto-optical disk 12 shown in FIGS. 7A, 7B and 8 will be described.
  In the sector mark area 122, data indicating the head of the sector 120 is written.
  In the VFO1 region 124, the VFO2 region 130, the VFO3 region 136, and the VFO4 region 146 (hereinafter, these regions are collectively referred to as “VFO region”), for example,In hexadecimal notationData such as 55h or AAh in which the bit pattern changes frequently is written, and the signal RF obtained from these areas is mainly used for regenerating a clock used for reading data. Therefore, the data in the VFO area has no effective meaning.
  In the AM1 area 126, AM2 area 132, and AM3 area 138, data indicating that the subsequent area is an ID area is written.
[0039]
The number of the track to which the sector 120 belongs is written in the track number area 160 of the ID area, the number of the sector 120 is written in the sector number area 162, and the track number area 160 and the sector number area 162 are written in the CRC area 164. A CRC code for error correction of the written data is written.
[0040]
Data used for synchronization detection is written in the synchronization signal area 170 of the data area 148.
In the data area 172, encoded data obtained by encoding the input data ID by RLL (1, 7) encoding is written.
In the resynchronization signal area 174, data (resynchronization data) used for resynchronization detection is written.
[0041]
As shown in FIG. 4 and described above, when RLL (1, 7) decoding is performed by the data decoding circuit 50, the code of the last encoded data y0 ′ includes the subsequent code in addition to the encoded data y0 ′. 6-bit encoded data (4 bits in terms of input data ID) of converted data y2 ″, y1 ″, y0 ″, y2 ″ ′, y1 ″ ′, y0 ″ ′ is required. Therefore, in the data recording / reproducing apparatus 1 of the present embodiment, for example, a 6-bit obtained by RLL (1, 7) encoding the known input data ID after the CRC area 164 and after the data area 148. Either an area for recording the encoded data is provided, or whether the 6-bit encoded data obtained by RLL (1, 7) encoding the known input data ID in the buffer area 150 is recorded.
[0042]
Of the parts of the data recording / reproducing apparatus 1 described above, the synchronization detection circuit 46 corresponds to the demodulation control means according to the present invention, the data decoding circuit 50 corresponds to the demodulation means according to the present invention, and the disk system 10 Corresponds to the data reading means according to the present invention.
The disk system 10 and the data reproducing device 40 correspond to the data reproducing device of the present invention.
[0043]
Hereinafter, the operation of the data recording / reproducing apparatus 1 of the present invention will be described with reference to the above-described drawings and FIG.
FIG. 9 is a diagram showing timings of the signals RASA, SRDS, RCS, and RES shown in FIG. 1, in which (A) shows the signal RASA, (B) shows the signal SRDS, and (C) shows the signal RCS. (D) shows the signal RES.
First, the case where the data recording apparatus 20 of the data recording / reproducing apparatus 1 writes data to the magneto-optical disk 12 will be described.
Input data ID is input in series to the input terminal IN.
The inputted input data ID is inputted to the ECC encoder 24 as a signal WDIS via the data input circuit 22.
The ECC encoder 24 adds an error correction code (ECC) to the signal WDIS and outputs the signal WES to the data encoding circuit 30.
[0044]
  The data encoding circuit 30 is connected to the control device 18.controlEach time 2 bits of the input signal ID are input (each encoding cycle) according to the control via the signal WCDC.Recording targetThe signal WES is RLL (1, 7) encoded and output to the data selection circuit 34 as a signal WCS.
  On the other hand, the synchronization signal generation circuit 32 generates the resynchronization signal RESYNC and outputs it to the data selection circuit 34 in accordance with the control via the control signal SRGC of the control device 18.
[0045]
  The data selection circuit 34 selects either the signal WCS or the resynchronization signal RESYNC according to control via the control signal SRGC of the control device 18. That is, the data selection circuit 34 divides the signal WCS into portions to be written in the data regions 172, inserts the resynchronization signal RESYNC to be written in the resynchronization signal region 174 between the data regions 172, and laser-drives as the signal WDBS It outputs to the circuit 36.
  The laser drive circuit 36 amplifies the signal WDBS and outputs it to the laser diode 38 as the signal WAS.
  On the other hand, the disk system 10 rotates the magneto-optical disk 12 according to the control via the signal DC of the control device 18, aligns the laser diode 38 at the predetermined position of the magneto-optical disk 12,The laser diode 38 is energized according to the recorded data.Position for writing signal WAS to magneto-optical disk 12In time withApply.
  The laser diode 38 converts the signal WAS into a laser beam, irradiates the magneto-optical disk 12, and writes the signal WAS to the magneto-optical disk 12 in accordance with the recording format of the magneto-optical disk 12.
[0046]
  Next, the data reproducing apparatus 40 of the data recording / reproducing apparatus 1 is connected to the magneto-optical disk 12.Read and play data fromThe operation will be described.
  The disk system 10 rotates the magneto-optical disk 12 in accordance with control via the signal DC of the control device 18, aligns the laser diode 38 with a predetermined position of the magneto-optical disk 12, and irradiates the magneto-optical disk 12 with a laser beam.
  A laser beam including data irradiated from the laser diode 38, reflected by the magneto-optical disk 12 and recorded on the magneto-optical disk 12 is converted into an electrical reproduction signal (signal RF) by the light detecting element 42 and reproduced. Output to the amplifier circuit 44.
  The reproduction signal amplifying circuit 44 amplifies the signal RF, identifies it as binary, outputs it to the synchronization detection circuit 46 as a signal RASB, and resynchronizes the signal region 174 shown in FIG._i And resynchronization signal area 174 corresponding to_i Including data corresponding to (i = 1 to 120)ReadThe signal RASA is output to the data selection circuit 48.
[0047]
  The synchronization detection circuit 46 detects the synchronization signal SYNC and the resynchronization signal RESYNC recorded in the synchronization signal area 170 of each sector 120 from the signal RASB, and the controller 18 and the data decoding as the signal SRDS shown in FIG. Output to the circuit 50. Input from the synchronization detection circuit 46 to the control device 18Sync detectionThe signal SRDS is used, for example, as a synchronization signal for generating a control signal for each part of the data recording / reproducing apparatus 1 by the control device 18 and input to the data decoding circuit 50.Sync detectionThe signal SRDS is stored in the registers 500, 502, and 504 as described above with reference to FIGS.Shift operationUsed for control.When the synchronization detection signal SRDS indicating that the resynchronization signal is detected is 0, the shift operation is not performed.Therefore, as shown in FIG. 9C, the resynchronization signal region 174_i The part 190 corresponding to_i Is output without being decoded by the data decoding circuit 50.
[0048]
  As shown in FIG. 9C, the data decoding circuit 50 is controlled according to control via the control signal RCEC of the control device 18 every time 3-bit encoded data is input (for each encoding cycle).ReadData area 172 of signal RASA_i RLL (1, 7) decoding only the part corresponding toDecryptionThe signal RCS is output to the ECC decoder 52 and the control device 18.
  DecryptionThe signal RCS includes data recorded in the ID area. The control device 18 processes the data recorded in the track number area 160, sector number area 162, and CRC area 164 of the ID area to detect the track number and sector number, and the data recording / reproducing apparatus 1 based on these numbers. Processing such as generation of a control signal DC for controlling the control is performed.
[0049]
  The ECC decoder 52Decryption illustrated in Figure 9Data area 172 of signal RCS_i Based on the error correction code included in the part corresponding toDecryptionOf the signal RCS, error correction of data corresponding to the data area 172 is performed. Further, the ECC decoder 52DecryptionThe error correction code is removed from the signal RCS, and only the data corresponding to the data area 172 is output to the decoded data output circuit 54 as the signal RES shown in FIG.
  The decoded data output circuit 54DecryptionThe signal RCS is output as the serial output data OD.
[0050]
  By configuring the data recording / reproducing apparatus 1 as described above,Illustrated in FIG.Since the data recorded in each data area 172 of the data area 148 is treated as a series of data and decoded, the encoded data without additional data recorded on the magneto-optical disk 12 can be correctly decoded.
  Also, the data length of the post-data area 166, 178 is 1 byte (1 byte as the data before encoding, 12 bits as the data after encoding), but 4 bits (4 bits as the data before encoding, The data length is not limited as long as the encoded data is 6 bits) or more.
  In the data recording / reproducing apparatus 1, the data recording apparatus 20 and the data reproducing apparatus 40 are integrally configured. However, the data recording apparatus in which the data recording apparatus 20 and the disk system 10 are combined, and the data reproducing apparatus 40 and the disk system 10 are combined. And may be configured separately as a data reproducing apparatus.
[0051]
Further, only the control device 18, the data selection circuit 48, and the data decoding circuit 50 can be combined and used alone as a data decoding device.
In the present embodiment, each component of the data recording / reproducing apparatus 1 is configured by hardware. However, each component may be configured as software having an equivalent function on a computer.
[0052]
In addition, the encoding method and the decoding method are not limited to RLL (1, 7) encoding and RLL (1, 7) encoding, but generally (d, k; m, n; r) encoding (( d, k; m, n; r) other run-length encoding methods called modulation) and decoding methods thereof. As described above, in the case of adapting to other encoding methods and decoding methods, the recording format of the magneto-optical disk 12, the configuration of the data encoding circuit 30, the configuration of the data decoding circuit 50, and the like are used as the encoding method and decoding method. It is necessary to change to match.
In addition to the embodiments described above, the data recording / reproducing apparatus 1 of the present invention can have various configurations as shown in the above-described embodiments, for example.
[0053]
【The invention's effect】
As described above, according to the present invention, recorded data in which synchronous data is inserted into encoded data encoded by a method in which encoded data of a plurality of encoding periods such as run-length encoding has a predetermined relationship. Even when the input data is reproduced, the additional data need not be recorded between the encoded data and the synchronization data.
Furthermore, according to the present invention, additional data between encoded data and synchronization data is not necessary, so that the storage area of the recording medium can be used effectively.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a data recording / reproducing apparatus.
2 is a diagram showing a configuration of a data encoding circuit shown in FIG. 1. FIG.
FIG. 3 is a diagram illustrating a configuration of a coding circuit (WCEL) illustrated in FIG. 2;
4 is a diagram showing a configuration of a data decoding circuit shown in FIG. 1. FIG.
FIG. 5 is a diagram illustrating a configuration of a decoding circuit (RCEL) illustrated in FIG. 4;
6 is a diagram showing a sector of the magneto-optical disk shown in FIG. 1. FIG.
7A and 7B are diagrams showing the recording format of the sector of the magneto-optical disk shown in FIG. 6, wherein FIG. 7A shows the recording format of the sector, and FIG. 7B shows the ID1 area (ID1) shown in FIG. ), The recording format of the ID2 area (ID2) and ID3 area (ID3).
8 is a diagram showing a configuration of a data area shown in FIG.
9 is a diagram showing timings of the signals RASA, SRDS, RCS, and RES shown in FIG. 1, in which (A) shows the signal RASA, (B) shows the signal SRDS, and (C) shows the signal RCS. (D) shows the signal RES.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Data recording / reproducing apparatus, 10 ... Disk type | system | group, 12 ... Magneto-optical disk, 120 ... Sector, 122 ... Sector mark area, 124 ... VFO1 area, 126 ... AM1 area, 128 ... ID1 area, 130 ... VFO2 area, 132 ... AM2 area, 134 ... ID2 area, 136 ... VFO3 area, 138 ... AM3 area, 140 ... ID3 area, 142 ... PA area, 144 ... ALPC area, 146 ... VFO4 area, 148 ... data area, 150 ... buffer area, 160 ... Track number area, 162 ... Sector number area, 164 ... CRC area, 166, 178 ... Post data area, 170 ... Synchronization signal area, 172 ... Data area, 174 ... Resynchronization signal area, 176 ... Recording area, 180 ... Channel 1 recording area, 182 ... channel 2 recording area, 14 ... disk drive system, 16 ... Academic system, 18 ... control device, 20 ... data recording device, 22 ... data input circuit, 24 ... ECC encoder, 30 ... data encoding circuit, 300,302,304 ... register, 310 ... encoding circuit, 312 to 330 ... Logic circuit 32... Sync signal generation circuit 34... Data selection circuit 36... Laser drive circuit 42... Photodetection element 44 .. Reproduction signal amplification circuit 46. Decoding circuit, 500, 502, 504, 506 ... register, 510 ... decoding circuit, 512-522 ... logic circuit, 52 ... ECC decoder, 54 ... decoded data output circuit

Claims (3)

The modulated data generated by RLL (1, 7) modulation of the original data to be modulated excluding the synchronization signal is RLL (1, 7) demodulated from the data in which a predetermined synchronization signal is inserted, and the synchronization signal is obtained. A data demodulator for demodulating original data excluding,
Demodulation means for demodulating RLL (1, 7);
A synchronization signal in the recorded data is detected, and when the synchronization signal is detected, the demodulation operation of the demodulation means is substantially stopped at the timing when the detected synchronization signal is input to the demodulation means, and the synchronization Demodulating control means for performing RLL (1, 7) demodulating operation on the modulated data in the demodulating means only when modulated data obtained by modulating the original data excluding the signal is input to the demodulating means,
RLL (1, 7) demodulation of only the modulated data,
Data demodulator. The demodulation control means includes
Before SL generates sync detection signals of the first logic signal upon detection of a synchronization signal, and synchronous detection means that generates a sync detection signal of the second logic signal when the previous SL does not detect a sync signal,
Control means for outputting first to fourth encoding period control signals according to the encoding period;
First register means for inputting the demodulation target data and shifting the input demodulation target data by 3 bits according to the first encoding cycle control signal only when the logic of the synchronization detection signal is the first logic When,
The output data of the first register means is input, and the input output data of the first register means is shifted by 3 bits according to the second encoding cycle control signal only when the logic of the synchronization detection signal is the first logic. Second register means for
The output data of the second register means is input, and the input output data of the second register means is shifted by 3 bits according to the third encoding cycle control signal only when the logic of the synchronization detection signal is the first logic. And a third register means
The demodulating means includes
Decoding means for performing RLL (1, 7) decoding processing based on the output data of the first to third register means;
And fourth register means for inputting the output data of the decoding means and shifting and outputting the input data in accordance with the fourth encoding cycle control signal,
The decoding means includes
First OR operation means for calculating an OR of 3-bit data output from the first register means;
Second OR operation means for calculating an OR of the 3-bit data output from the second register means and the 1-bit data output from the third register means;
Inverting means for inverting the sign of the least significant bit data of the 3-bit data output from the second register means;
NOR calculating means for calculating NOR of 3-bit data output from the second register means;
Third OR operation means for calculating the OR of the output signal of the NOR operation means and the most significant bit data of the 3-bit data output from the second register means, and outputting the lower state data;
NAND operation means for calculating NAND of the output signal of the first OR operation means, the output signal of the second OR operation means and the output signal of the inversion means, and outputting higher-order state data,
The data demodulator according to claim 1. Synchronization signals, a plurality of RLL (1, 7) modulated encoded data, the demodulated data containing a synchronization signal which is inserted between the coded data of a predetermined number, RLL (1, 7) demodulating A data demodulator for demodulating the encoded data,
Before SL generates sync detection signals of the first logic signal upon detection of a synchronization signal, and synchronous detection means that generates a sync detection signal of the second logic signal when the previous SL does not detect a sync signal,
Control means for outputting first to fourth encoding period control signals according to the encoding period;
First register means for inputting the demodulation target data and shifting the input demodulation target data by 3 bits according to the first encoding cycle control signal only when the logic of the synchronization detection signal is the first logic When,
The output data of the first register means is input, and the input output data of the first register means is shifted by 3 bits according to the second encoding cycle control signal only when the logic of the synchronization detection signal is the first logic. Second register means for
The output data of the second register means is input, and the input output data of the second register means is shifted by 3 bits according to the third encoding cycle control signal only when the logic of the synchronization detection signal is the first logic. Third register means to:
Decoding means for performing RLL (1, 7) decoding processing based on the output data of the first to third register means;
And fourth register means for inputting the output data of the decoding means and shifting and outputting the input data in accordance with the fourth encoding cycle control signal,
The decoding means includes
First OR operation means for calculating an OR of 3-bit data output from the first register means;
Second OR operation means for calculating an OR of the 3-bit data output from the second register means and the 1-bit data output from the third register means;
Inverting means for inverting the sign of the least significant bit data of the 3-bit data output from the second register means;
NOR calculating means for calculating NOR of 3-bit data output from the second register means;
Third OR operation means for calculating the OR of the output signal of the NOR operation means and the most significant bit data of the 3-bit data output from the second register means, and outputting the lower state data;
NAND operation means for calculating NAND of the output signal of the first OR operation means, the output signal of the second OR operation means and the output signal of the inversion means, and outputting higher-order state data,
Data demodulator.

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