JPS63263893A - Television receiver - Google Patents

Abstract

PURPOSE:To display a screen with the color video signal of a CCIP system without any damage even when an image memory is of only the capacity of the color video signal of an NTSC system by reducing and writing the color video signal of the CCIR system to approximately 5/6 times in a vertical direction compared with the color video signal of the NTSC system. CONSTITUTION:A switching circuit 7 to receive both a first color video signal of a CCIR system (PAL system or SECAM system) and a second color video signal of an NTSC system, synchronize to the synchronizing signal of either of first and second color video signals, drive a video display 18 and supply the first and second color video signals to a frame memory 14 is provided. When the first color video signal is written into the frame memory 14, the signal is reduced to approximately 5/6 times in the vertical direction compared with the second color video signal, namely, the number of lines is thinned and written, at the time of the reading from the frame memory 14, it is read as the color video signal of either of them and supplied to the video display 18.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Outline of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Embodiment G1. Overall configuration G2. Write/Read System inn'G] Operation G4 Effect H Effect of the Invention A Industrial Application Field The present invention relates to a television receiver using an image memory.

B. Summary of the Invention The present invention provides that in a television receiver using an image memory, when writing a color video signal of the CCIR system (PAL system or SECAM system) to the image memory, the color video signal of the NTSC system is compared to the color video signal of the NTSC system. By reducing the size of the image by approximately 5/6 times in the vertical direction,
The image memory only has a capacity for NTSC color video signals (this is so that a screen based on CCIR color video signals can be displayed without any defects).

C. Conventional technology Conventionally, image memory for storing video signals is used to display so-called picture-in-picture, which displays a sub-screen within the main screen, so-called multi-picture, which displays screens at multiple points in time at the same time, still images, screen enlargement, Various television receivers have been proposed that enable digital video effects such as reduction.

D. Problems to be Solved by the Invention In such a television receiver, a field memory having a capacity of, for example, a color video signal of the NTS C system, that is, a capacity of 256 lines, is used as the image memory. has been done.

Here, the color video signal of the NTSC system is 525 lines/frame and 60 fields/sec, whereas the CC
IR color video signal is 625 lines/frame,
50 fields/second.

Therefore, in the above-mentioned television receiver, when writing a CCIR color video signal to the image memory, 625/2 = 625/2 in each field.
The disadvantage was that only 256 lines out of 312.5 lines could be written, and only about 80% of the effective screen could be displayed.

Also, for example, in picture-in-picture, the main screen is N.
When the screen uses a TSC color video signal and the sub screen uses a CCIR color video signal, the image memory is written at 50 fields/second and read at 60 fields/second. As a result, an overtaking scan occurs in which two fields are mixed at the same time on the sub screen, and 10 fields are scanned per second.
There was a drawback that horizontal stripes appeared at a certain rate.
- In view of the above, the present invention makes it possible to display a screen based on CCIR color video signals without defects even if the image memory has only the capacity for NTSC color video signals.

E Means for solving the problem (Fig. 1) The present invention has the following features:
It receives both the first color video signal of the CCIR system and the second color video signal of the NTSC system, and the first and second color video signals are received.
drive the video display device (18) in synchronization with the synchronization signal of one of the color video signals, and selectively supply the first and second color video signals to the frame memory (14). A switching circuit (7) is provided, and when writing the first color video signal to the frame memory (14), it is approximately 5/5 times smaller in the vertical direction than the second color video signal.
It is written by reducing the number of lines by 6 times, that is, by thinning out the number of lines, and when reading from the frame memory (14), it is read out as one of the color video signals and supplied to the video display device (18). It is.

F Function In the above configuration, the frame memory (14) has CC
When writing IR color video signals, use NTSC.
Since the configuration is such that the data is written at a size approximately 5/6 times smaller in the vertical direction than the color video signal of the NTSC system, for example, even if the frame memory (14) has only the capacity of the color video signal of the NTSC system, it is possible to write the color video signal of the CCIR system. The entire color video signal can be written. Therefore, a screen based on CCIR color video signals can be displayed without any defects.

G. Example Hereinafter, an example of the present invention will be described with reference to FIG.

G1 overall configuration In Figure 1, (1) is an antenna, and the broadcast signal captured by this antenna +1) is sent to the tuner (2) and (
3). The channel selection operations of these tuners (2) and (3) are controlled by a microcomputer (hereinafter referred to as "microcomputer"). That is, an operation signal is supplied from the remote control receiver (5) to the microcomputer (4) in response to the user's operation of the commander (not shown), and the
21 and (3) are controlled to perform channel selection operations according to the user's operation of the commander.

From these tuners (2) and (3), PAL system, S
Color video signals of the ECAM system or the N1'SC system are output and supplied to fixed terminals on the A side of the switch circuits (6) and (7), respectively.

Further, (8) is an external input terminal, and a color video signal of PAL system, SECAM system, or NTSC system is supplied from, for example, a video tape recorder, a video disc player, or the like. The color video signal supplied to this terminal (8) is supplied to the B-side fixed terminals of the switch circuits (6) and (7). Further, (9) is also a similar external input terminal, and the color video signal supplied to this terminal (9) is supplied to the fixed terminals on the C side of the switch circuits (6) and (7).

The switching operation of switch circuits (6) and (7) is controlled by a microcomputer (
4). In other words, the microcomputer (4) is
An operation signal is supplied to switch circuits (6) and (7).
is controlled to perform a switching operation according to the user's operation of the commander.

Further, the color video signal output from the switch circuit (6) is supplied to the signal processing circuit (10). This signal processing circuit (10) includes a luminance signal and color signal separation circuit, a color demodulation circuit, a matrix circuit, etc., and automatically operates according to the format of the supplied color video signal. is switched so that primary color signals R, G, and B of red, green, and blue are output. This signal processing circuit (
The primary color signals R, G, and B outputted from 10) are supplied to the fixed terminal on the A side of the switch circuit (11). The signal processing circuit (10) includes a sync separation circuit, and horizontal and vertical sync signals PH1 and pvt separated by the sync separation circuit are output.

Further, the color video signal output from the switch circuit (7) is supplied to the signal processing circuit (12). This signal processing circuit (12) is equipped with a luminance signal and color signal separation circuit, a color demodulation circuit, etc., and its operation is automatically switched to operate according to the format of the supplied color video signal. Luminance signal Y, red difference signal RY, and blue difference signal B-Y
is output. This signal processing circuit (12
) output from the luminance signal Y, color difference signal R-Y, B-Y
is converted into a digital signal by an A/D converter (13) and then supplied to a memory (14). This memory (1
4) is a frame memory having two field areas for each of the luminance signal Y and the color difference signals R-Y and B-Y, and this frame memory is, for example, an NTS
Capacity IEt(2) for one frame of C color video signal
x256 lines). The signal processing circuit (12) includes a sync separation circuit, and horizontal and vertical sync signals PH2 and PV2 separated by the sync separation circuit are output.

Furthermore, the luminance signal Y, color difference signals R-Y, B-Y outputted from the memory (14) are respectively converted into analog signals by a D/A converter (15), and then sent to a matrix circuit (16).
supplied to Red, edge and blue primary color signals R1G and B are output from this matrix circuit (16), and these primary color signals R, G and B are sent to B of the switch circuit (11).
Supplied to the fixed terminal on the side.

The switching operation of the switch circuit (11) is controlled by the microcomputer (4). That is, in response to the user's commander operation, an operation signal is supplied from the remote control receiver ta (51) to the microcomputer (4), and the switch circuit (11) is controlled to perform a switching operation in accordance with the user's commander operation. For example, when displaying a moving image using a color video signal output from the switch circuit (6), it is switched to the A side, and when displaying a moving image or a still image using a color video signal output from the switch circuit (7), it is switched to the B side. It is switched to the B side for enlarged or reduced image display using the color video signal output from the switch circuit (7), and is switched to the B side for multi-picture display using the color video signal output from the switch circuit (7). In the case of picture-in-picture display, in which a sub-screen using a color video signal output from the switch circuit (7) is displayed within a main screen using a color video signal output from the switch circuit (6), the sub-screen display is switched to the side. It is switched to the B side in response to this, and switched to the A side during the other periods.

The color video signal output from this changeover switch (11) is supplied via a video amplifier (17) to a color picture tube (18) constituting a video display device.

Further, the horizontal and vertical synchronizing signals PH and pvt output from the signal processing circuit (10) are supplied to the deflection circuit (19). The deflection signal from this deflection circuit (19) is then supplied to the deflection coil (18a) of the picture tube (18). That is, in the picture tube (18), the switch circuit (
6) Horizontal and vertical deflections are performed in synchronization with the synchronization signal of the color video signal outputted from.

In addition, synchronization signals P H1+ P V1+ P H2 output from the signal processing circuits (10) and (12)
+PV2 is supplied to the microcomputer (4). In the microcomputer (4), these synchronization signals Pn1. PV
I, P)+2. Based on PV2, the color video signals output from switch circuits (6) and (7)
CIR method (PAL method or 5ECAP method) is NT
A determination is made as to whether it is the SC method.

Further, (20) is a memory controller, and this memory controller (20) controls reading and writing to the memory (14). This memory controller (20) includes a signal processing circuit (10).

Synchronous signal P )11+ P V1+ from (12)
P H2+ P V2 is supplied as a timing signal, and a control signal is also supplied from the microcomputer (4). In this case, an operation signal is supplied from the remote control receiver (5) to the microcomputer (4) in response to the user's commander operation, and the microcomputer (4) supplies the switch circuit to the memory controller (2o) in response to this operation signal. A control signal corresponding to the format of the color video signal outputted from (6) and (7) is supplied, and reading and writing to and from the memory (14) are performed based on this control signal.

02 Memory write/read control For example, when NTSC color video signals are output from the switch circuits (6) and (7), the memory (1
Writing/reading to/from 4) is performed as follows.

Switch circuit (6) by user's commander operation
When an instruction is given to display a moving image using a color video signal output from the memory (14), writing and reading to and from the two field areas of the memory (14) is not performed.

Furthermore, when a moving image display using a color video signal output from the switch circuit (7) is instructed by the user's operation of the commander, signals are stored in the two field areas of the memory (14) based on the synchronization signals PH2 and PV2. The luminance signal Y1 and the color difference signals R-Y and B-Y output from the processing circuit (12) are sequentially and alternately written for each field. The signals written in the two field areas of the memory (14) are the synchronization signal p,
are read out sequentially and alternately based on.

Furthermore, when a still image display is instructed by the user's commander operation, the two field areas of the memory (14) contain a luminance signal output from the signal processing circuit (12) based on the synchronization signal P H2 + P v2. Y,
Color difference signals R-Y and B-Y are written.

The signals written in the two field areas of this memory (14) are read out repeatedly and alternately based on the synchronizing signals PH1+PVI.

Also, when the user commands to display an enlarged or reduced image, the memory (1
4) In the two field areas, the synchronization signal PH21P
The luminance signal Y, color difference signals R-Y, B-Y output from the signal processing circuit (12) based on V2 are sequentially and alternately written for each field.

Then, when displaying an enlarged image, 2 of memory (14)
Among the signals written in the two field areas, signals of a predetermined screen to be enlarged are sequentially and alternately read out corresponding to the entire screen position based on the synchronizing signal PH1+PV1. On the other hand, when displaying a reduced image, the signals written in the two field areas of the memory (14) are the synchronizing signals PH1,
They are sequentially and alternately read out in correspondence with predetermined reduced screen positions based on pvt.

Furthermore, when multi-picture display is instructed by the user's commander operation, synchronization signals P H2 + P V are stored in two field areas of the memory (14).
The luminance signal Y and color difference signals R-Y and B-Y output from the signal processing circuit (12) based on No. 2 are sequentially and alternately written for each field. In this case, each field area is divided into 9 parts corresponding to, for example, 9 split screen positions, and the signal of each field is 1/3 times as large in the horizontal and vertical directions in each divided part of each field area. The reduced signal is written. In other words, only one out of three lines is written into each divided section, and only one out of three pixels is written into three pixels. The signals for nine screens thus obtained are sequentially and alternately read out as signals for one screen based on the synchronization signal Pt11°pvt.

In addition, when picture-in-picture display is instructed by the user's commander operation, memory (1
4) In the two field areas, the synchronization signal PH21P
The luminance signal Y and color difference signals R-Y and B-Y output from the signal processing circuit (12) based on y2 are sequentially and alternately written for each field.

In this case, each field signal is distributed horizontally and vertically in 1/9 area of each field area.
A signal reduced by /3 times is written.

That is, the number of lines to be written is only one out of three, and the number of pixels to be written is only 1+1JJ out of three. The signals written in the two field areas of the memory (14) are synchronization signals PHI.

They are sequentially and alternately read out in correspondence with the child screen position based on the pvt.

Next, the switch circuit (6) outputs an NTSC color video signal, and the switch circuit (7) outputs a C
When a CIR color video signal is output, reading and writing to the memory (14) is performed as follows.

Switch circuit (6) by user's commander operation
When an instruction is given to display a moving image using a color video signal output from the memory (14), writing and reading to and from the two field areas of the memory (14) is not performed.

Furthermore, when a video display using a color video signal output from the switch circuit (7) is instructed by the user's commander operation, two field areas of the memory (14) are filled with data based on the synchronization signal P H2 * P V2. luminance signal Y output from the signal processing circuit (12),
Color difference signals R-Y and B-Y are sequentially and alternately written for each field. In this case, each field area of the memory (14) has a capacity of 256 lines, which is one field of an NTSC color video signal.
Since it is not possible to write all of 312.5 fins, which is one field of a CCIR color video signal, each field signal is written after being reduced by a factor of 576 in the vertical direction. That is, only five out of six lines are written. The signals written in the two field areas of the memory (14) are the synchronization signal PH
, and are read out sequentially based on PVl. In this case, two field areas of the memory (14) have a frequency of 50Hz (
Since writing is performed at 6011z (frequency of synchronization signal PV2) and reading is performed at 6011z (frequency of synchronization signal Pv1), one field out of six fields is set to the previous field so that reading does not overtake writing. For example, As A2 BIB2 CI C2DI D2 as shown in FIG.
When the lO field of EI B2 is written (shown in solid line), AlAt A2BI B2 CI C2C
2Dt D2 EI 12 fields of B2 are read (shown with dashed lines), and in this case, AX is read from the start of writing the At(C2> field) so that the reading of the A1(C2) field does not overtake the writing of the AI(C2) field. (C2) The time T until the start of reading the field is set to be 20-16.7=3.3e sec or more.In FIG. 2, the position indicated by the dashed line is T.
= 3.3a+see, and when the time T is smaller than this, the writing of the At(C2) field will overtake the reading of the A1(C2) field. In this case, A2 B1 and 82 C1
Since the vertical positions of the scanning lines are reversed between each field, fields A2 and 82 are read out with a delay of one horizontal period.

Furthermore, when still image display is instructed by the user's commander operation, the two field areas of the memory (14) contain the luminance signal Y output from the signal processing circuit (12) based on the synchronization signal PH2+PV2; Color difference signals R-Y and B-Y are written. In this case, each field signal is reduced by 5/6 times in the vertical direction and written. That is, only five lines are written in six trees.

The signals written in the two field areas of this memory (14) are the synchronization signal PH1+Pyl
are read out repeatedly and alternately based on.

Also, when the user commands to display an enlarged or reduced image, the memory (1
In the two field areas of 4), the synchronization signal P H21
The luminance signal Y, color difference signals R-Y, B-Y output from the signal processing circuit (12) based on Py2 are sequentially and alternately written for each field.

In this case, each field signal is reduced by 5/6 times in the vertical direction and written. In other words, only five out of six lines are heated. When displaying an enlarged image, signals of a predetermined screen to be enlarged out of the signals written in the two field areas of the memory (14) are sequentially and alternately read out corresponding to all double-sided positions based on the synchronization signal PHIIPV1. It will be done. On the other hand, when displaying a reduced image,
The signals written in the two field areas of the memory (14) are sequentially read out corresponding to predetermined reduction double-sided positions based on the synchronization signal PH11P Vl. In this case too,
50Hz in two field areas of memory (14)
Since writing is performed at 60Hz (frequency of synchronization signal pv2) and reading is performed at 60Hz (frequency of synchronization signal pvt), in order to prevent reading from overtaking writing, 6 fields are For one field, the signal of the previous field is continuously read out. In this case, in order to prevent two field signals from coexisting in the same field, A
AI(C2) from start of writing of t(C2) field
For example, when enlarging 1/16th screen at the top of the screen (1/4 in the vertical direction and 1/4 in the horizontal direction), the period T is set appropriately. sec or more, but when enlarging 1/16 screen at the bottom of both sides, the period T is set to 15 msec or more.

Furthermore, when multi-picture display is instructed by the user's commander operation, synchronization signals P H2 + P V are stored in two field areas of the memory (14).
The luminance signal Y and color difference signals R-Y and B-Y output from the signal processing circuit (12) based on No. 2 are sequentially and alternately written for each field. In this case, each field area is divided into nine parts corresponding to, for example, nine split screen positions,
In each divided portion of each field area, the signal of each field is 1/3 times the horizontal direction and 1/4 times the vertical direction (
”=-1/3 3 (llil and l (Ri!) only.Then, the signals for nine sides written in the two field areas of memory (14) are synchronization signals P H1+ P
The signals for one screen are sequentially and alternately read out based on Vl.

In addition, when picture-in-picture display is instructed by the user's commander operation, memory (1
4) The two field areas are provided with synchronization signals pln and p.
The luminance signal Y and color difference signals R-Y and B-Y output from the signal processing circuit (12) based on the signal processing circuit (12) based on the signal processing circuit (12) are sequentially and alternately written for each field.

In this case, each field signal is reduced by 173 times in the horizontal direction and 1/4 (#1/3 x 5/6 = 5/18) times in the vertical direction in each 1/9 area of each field area. A signal is written. That is, only one out of four lines is written, and only one out of three pixels is written. And memory (1
The signals written in the two field areas 4) are sequentially read out based on the synchronization signal P H1+P Vl corresponding to the child screen position. In this case, memory (1
4), two frames' worth of signals, that is, four fields' worth of signals are written, and the signals of each field are selectively read out, thereby preventing two field signals from coexisting in the same field.

Next, the switch circuit (6) outputs a CCIR color video signal, and the switch circuit (7) outputs the N
When a TSC color video signal is output, reading and writing to the memory (14) is performed as follows.

Switch circuit (6) by user's commander operation
When an instruction is given to display a moving image using the color image ('I times signal) output from the memory (14), reading and writing to the two field areas of the memory (14) is not performed.

Furthermore, when a video display using a color video signal output from the switch circuit (7) is instructed by the user's operation of the commander, the synchronization signal P)! is stored in two field areas of the memory (14). Luminance signal Y output from the signal processing circuit (12) based on 2+P V2
, color difference signals R-Y, B-Y are sequentially and alternately written for each field. The signals written in the two field areas of the memory (14) are the synchronization signal P H1+
They are read out sequentially and alternately based on P Vl. In this case, each field signal is enlarged 615 times in the vertical direction and read out.

That is, for the five lines that have been written, six lines are read out by repeatedly reading out the same line. In addition, in this case, 6011z (frequency of synchronization signal PV2) is stored in the two field areas of memory (14).
50Hz (synchronization signal PV
Since reading is performed at a frequency of
For example, as shown in Figure 3, AI A2 Bt I32
Ct C2DI D2EI Et FI F2 no 1
2 fields are written (shown in solid line), At
A2 BL L32 CI DtD2 Et Et
Ten fields of Ft are read out (indicated by broken lines). In this case, read the Cz(Ft) field to 0.
1 (A1) field from the start of writing of the A1 (D,) field to avoid overtaking the writing of the A1 (A1) field.
(Dl) The time T until the start of field reading is 16
．． It is assumed to be 7 msec or less. In FIG. 3, the position indicated by the dashed line is T"" 16.7 m sec, and when the time T is longer than this, C1-(F
l) The writing of the Dl (At) field will overtake the reading of the field. In addition, in this case D
The vertical positions of the scanning lines are reversed between fields 2E1 and Et Fl, so fields D2 and Et are 1
The readout is delayed by a horizontal period.

Furthermore, when still image display is instructed by the user's commander operation, the two field areas of the memory (14) contain a luminance signal Y output from the signal processing circuit (12) based on the synchronization signals PH2 and PV2. , color difference signals R-Y, B-Y are written.

The signals written in the two field areas of this memory (14) are sequentially and alternately repeatedly read out based on the synchronization signals PHI and PV1. In this case, each field signal is enlarged 615 times in the vertical direction and read out. That is, six lines are read for every five lines written.

Also, when the user commands to display an enlarged or reduced image, the memory (1
The two field areas of 4) contain synchronizing signals P)12.
The luminance signal Y and color difference signals R-Y and B-Y output from the correspondence processing circuit (12) based on Pv2 are sequentially and alternately written for each field.

Then, when displaying an enlarged image, 2 of memory (14)
Among the signals written in the two field areas, the signals of the predetermined screen to be enlarged are sequentially and alternately read out corresponding to the entire screen position based on the synchronizing signal PH1+Pvt. On the other hand, when displaying a reduced image, the signals written in the two field areas of the memory (14) are the synchronizing signal PH□+
The data are sequentially read out in accordance with predetermined reduced screen positions based on P Vx. In this case, each signal is magnified 615 times in the vertical direction and read out. In other words, six lines are read for every five lines written.

In this case as well, writing is performed in the two field areas of the memory (14) at 6011z (the frequency of the synchronizing signal PV2), and reading is performed at 5011z (the frequency of the synchronizing signal PV), so that the writing is different from the reading. In order to avoid overtaking, one field out of the six fields to be written is not read out, as in the case of the moving image display described above. In this case, in order to prevent two field signals from coexisting in the same field, A! (Dt) A from the start of field writing
1 (・Dt) Time T until start of field reading
is set appropriately.

Furthermore, when multi-picture display is instructed by the user's commander operation, the two field areas of the memory (14) contain the luminance signal Y output from the signal processing circuit (12) based on the synchronization signals PH2 and PV2. ,
Color difference signals R-Y and B-Y are sequentially and alternately written for each field. In this case, each field area is, for example,
The field area is divided into nine parts corresponding to the nine divided screen positions, and a signal obtained by reducing the signal of each field by a factor of 1/3 in the horizontal and vertical directions is written in each divided part of each field area. In other words, only one out of three lines is written in each divided section, and one out of three pixels (Ilil only) is written in.
The signals for nine screens written in the two field areas of the memory (14) are sequentially and alternately read out as signals for one screen based on the synchronizing signal PH1°PVt. In this case, each signal is magnified 675 times in the vertical direction and read out. That is, six lines are read for every five lines written.

In addition, when picture-in-picture display is instructed by the user's commander operation, memory (1
4) In the two field areas, the synchronization signal PH21P
The luminance signal Y and color difference signals R-Y and B-Y output from the signal processing circuit (12) based on the signal processing circuit (12) based on the signal processing circuit (12) are sequentially and alternately written for each field.

In this case, each field signal is distributed horizontally and vertically in each 1/9th area of each field area.
A signal reduced by /3 times is written.

That is, only one out of three lines is written, and only one out of three pixels is written. Then, the signals written in the two field areas of the memory (14) are read out corresponding to the child screen position based on the synchronization signal P)11+Pvt. In this case, each signal is magnified 675 times in the vertical direction and read out.

That is, six lines are read for every five lines written. And in this case, memory (
14), signals for two frames, that is, four fields, are written, and the signals of each field are selectively read out, thereby preventing two field signals from coexisting in the same field.

Next, the switch circuit (6) outputs a CCIR color video signal, and the switch circuit (7) outputs a CCIR color video signal.
When a CIR color video signal is output, reading and writing to the memory (14) is performed as follows.

Switch circuit (6) by user's commander operation
When an instruction is given to display a moving image using a color video signal output from the memory (14), writing and reading to and from the two field areas of the memory (14) is not performed.

Furthermore, when the user's commander operation instructs video display using the color video signal output from the Sui Nochi circuit (7), the two field areas of the memory (14) are filled with data based on the synchronization signal P H21P v2. The luminance signal Y and color difference signals R-Y and B-Y outputted from the signal processing circuit (12) are sequentially and alternately written for each field. In this case, each field signal is reduced by 5/6 times in the vertical direction and written. That is, only five out of six lines are written. The signals written in the two field areas of the memory (14) are sequentially read out based on the synchronization signals PHI and PVl.

In this case, each field signal is enlarged 615 times in the vertical direction and read out. That is, the written 5
Six lines are read out for each book line.

Furthermore, when still image display is instructed by the user's commander operation, the two field areas of the memory (14) contain a luminance signal Y output from the signal processing circuit (12) based on the synchronization signals PH2 and PV2. , color difference signals R-Y, B-Y are written.

In this case, each field signal is reduced by 5/6 times in the vertical direction and written. That is, only five out of six lines are written. And this memory (I
The signals written in the two field areas 4) are read out repeatedly and alternately based on the synchronizing signals PH1 and PVt. In this case, each field signal is enlarged 615 times in the vertical direction and read out. That is, six lines are read for every five lines written.

Also, when the user commands to display an enlarged or reduced image, the memory (1
The two field areas of 4) contain synchronization signals PHI,
The luminance signal Y and color difference signals R-Y and B-Y output from the signal processing circuit (12) based on PV2 are sequentially and alternately written for each field.

In this case, each field signal is reduced by 5/6 times in the vertical direction and written. That is, only five out of six lines are written. When displaying an enlarged image, the signals of the predetermined screen to be enlarged among the signals written in the two field areas of the memory (14) are sequentially displayed corresponding to the full screen position based on the synchronization signal P Hll P Vl. They are read out alternately. On the other hand, when displaying a reduced image, the signals written in the two field areas of the memory (14) are sequentially and alternately read out corresponding to predetermined reduced screen positions based on the synchronizing signal PH□1PV1.

In this case, each field signal is enlarged 615 times in the vertical direction and read out. That is, the written 5
Six lines are read out for each book line.

Furthermore, when multi-picture display is instructed by the user's commander operation, synchronization signals P H2 + P V are stored in two field areas of the memory (14).
The luminance signal Y and color difference signals R-Y and B-Y output from the signal processing circuit (12) based on No. 2 are sequentially and alternately written for each field. In this case, each field area is divided into 9 parts corresponding to, for example, 9 split screen positions, and the signal of each field is 1/3 times the horizontal direction and 1/3 times the vertical direction in each divided part of each field area. /4 (Saki 1/3
×5/6 = 5/18) times the signal is written. That is, the number of lines written in each division is 4.
Only one pixel is written per book, and only one out of every three pixels is written. The nine screens' worth of signals written in the two field areas of the memory (14) are sequentially and alternately read out as one screen's worth of signals based on the synchronizing signals PH□ and Pv1.

In this case, each field signal is enlarged 615 times in the vertical direction and read out. That is, the written 5
Six lines are read out for each book line.

In addition, when picture-in-picture display is instructed by the user's commander operation, memory (1
The two field areas of 4) contain a synchronization signal P Hll
The luminance signal Y and color difference signals R-Y and B-Y output from the signal processing circuit (12) based on P Vz are sequentially and alternately written for each field.

In this case, each field signal is reduced by 1/3 times in the horizontal direction and 1/4 times (; 1/3 x 5/6 = 5/18) times in the vertical direction in each 1/9 area of each field area. signal is written. That is, only one out of four lines is written, and only one out of three pixels is written. The signals written in the two field areas of the memory (14) are sequentially read out in accordance with the child screen position based on the synchronization signal P Hll P Vi. In this case, each field signal is enlarged 615 times in the vertical direction and read out. Rabbit,
Six lines are read for every five lines written.

G3 operation This example is configured as described above, and when the user's commander operation instructs to display a moving image using the error video signal output from the switch circuit (6), the switch circuit (11) is switched to the A side. Since it can be switched, the picture tube (1
8) is supplied with the primary color signal R-B output from the signal processing circuit (10), and the horizontal and vertical deflections of this picture tube (18) are determined by the synchronization signal PH output from the signal processing circuit (10). □.

This is done based on PVl. Therefore, the picture tube (1
8) displays a moving image based on the color video signal output from the switch circuit (6).

Furthermore, when the user operates the commander to instruct moving image display using the color video signal output from the switch circuit (7), the switch circuit (11) is switched to the B side, so that the picture tube (18) A primary color signal R-B output from a matrix circuit (16) is supplied.

The memory (14) receives the signal Y output from the signal processing circuit (12).

R-Y and B-Y are sequentially written based on the synchronization signal P H2 + P V2 output from the signal processing circuit (12), and the synchronization signal output from the signal processing circuit (10) is written from this memory (14). Signal P H1+ P V
Signals Y, RY, and B-Y are sequentially read out based on l. That is, the signal is read out in the same format as the color video signal output from the switch circuit (6).

The horizontal and vertical deflections of the picture tube (18) are controlled by synchronizing signals PH1 and Pv output from the signal processing circuit (10).
It is carried out based on engineering. Therefore, the picture tube (18)
, a moving image based on the color video signal output from the switch circuit (7) is displayed in the format of the color video signal output from the switch circuit (6).

In this case, if the color video signal output from the switch circuit (7) is of the CCIR system, the memory
Since the signals Y, R-Y, and B-Y written in (14) are written in a 5/6-fold reduced size in the vertical direction to cover the planned surface, the screen is displayed without any defects. This also applies to still image display, enlarged image display, reduced image display, multi-picture display, and picture-in-picture display.

Further, when the field frequency of the color video signal output from the switch circuit (6) and the field frequency of the color video signal output from the switch circuit (7) are different, writing and reading to and from the memory (14) are controlled; Since two field signals are prevented from coexisting in the same field, horizontal stripes do not appear on the screen. This also applies to enlarged image display, reduced image display, and picture-in-picture display.

Furthermore, when a still image display is instructed by the user's commander operation, the switch circuit (11) is switched to the B side, so the picture tube (18) is connected to the matrix circuit (
The primary color signals R to B output from 16) are supplied. The memory (14) receives signals Y and RY output from the signal processing circuit (12).

B-Y is written for one frame based on the synchronization signals PH2 and PV2 output from the signal processing circuit (12), and the signal processing circuit (10) is written from this memory (14).
) The signals Y, RY, and B-Y are repeatedly read out based on the synchronization signals PH1 and PVI output from the synchronous signals PH1 and PVI. That is,
The signal is read out as a still image signal in the same format as the color video signal output from the switch circuit (6).

Further, the horizontal and vertical deflections of the picture tube (18) are controlled by synchronizing signals pH1 and Pv output from the signal processing circuit (10).
It is carried out based on engineering. Therefore, the picture tube (18)
There is a switch.

A still image based on the color video signal output from the circuit (7) is displayed using the color video signal format output from the switch circuit (6).

Furthermore, when an enlarged image display or reduced image display is instructed by the user's commander operation, the switch circuit (11) is switched to the B side, so that the output from the matrix circuit (16) to the picture tube (18) is Primary color signal R-
B is supplied. Then, the signals Y, RY, and B-Y output from the signal processing circuit (12) are stored in the memory (14) as the synchronization signal P H2 output from the signal processing circuit (12).
+ PV2 is sequentially written based on the synchronization signal PH1+PVI outputted from the signal processing circuit (10) from this memory (14). When displaying an enlarged image, the signal of a predetermined screen to be enlarged is written to the entire screen. The signal is read out corresponding to the position, and when displaying a reduced image, the signals of the entire screen are sequentially read out corresponding to the predetermined reduced screen position.

That is, the signal is read out as an enlarged or reduced image signal in the same format as the color video signal output from the switch circuit (6). Further, the horizontal and vertical deflections of the picture tube (18) are performed based on synchronization signals PH1 and Pvt output from the signal processing circuit (10). Therefore, an enlarged or reduced image based on the color video signal output from the switch circuit (7) is displayed on the picture tube (18) in the format of the color video signal output from the switch circuit (6).

In addition, when multi or picture display is instructed by the user's commander operation, the switch circuit (11
) is switched to the B side, so the picture tube (18) is supplied with the primary color signal R-B output from the matrix circuit (16). The nine divided sections of the memory (14) receive signals Y, R-Y output from the signal processing circuit (12).
, B-Y are sequentially written as one field's worth of signals reduced by 1/3 in both the horizontal and vertical directions based on the synchronization signal P142+PV2 output from the signal processing circuit (12). Data are sequentially read out from this memory (14) based on the synchronization signal PM1°PVl output from the signal processing circuit (10). That is, it is read out as a multi-picture signal of the same format as the color video signal output from the switch circuit (6).

Therefore, on the picture tube (18), a multi-picture based on the color video signal output from the switch circuit (7) is displayed in the format of the color video signal output from the switch circuit (6).

Furthermore, when picture-in-picture display is instructed by the user's commander operation, the switch circuit (11) is switched to the B side corresponding to the sub-screen display, and during other periods it is switched to the A side. (18)
are supplied with primary color signals R to B output from the matrix circuit (16) corresponding to the child screen display, and during other periods are supplied with primary color signals R to B output from the signal processing circuit (10). . The signals Y and R output from the signal processing circuit (12) are stored in the 1/9 area of the memory (14).
-Y.

B-Y is sequentially written with one field's worth of signals reduced to 1/3 in both the horizontal and vertical directions based on the synchronization signals PH2 and PV2 output from the signal processing circuit (12). , are sequentially read out from this memory (14) in accordance with the child screen position based on synchronization signals PH1 and PVl output from the signal processing circuit (10). In other words, it is read out as a signal for a child screen in the same format as the color video signal output from the switch circuit (6). Therefore, the picture tube (18) has a switch circuit (6
) A sub-screen based on the color video signal output from the switch circuit (7) is displayed within the main screen based on the color video signal output from the switch circuit (7).

G4 Effect According to this example, the color video signal supplied to and written into the memory (14) is CCII? When the video signal is of the NTSC format, the data is written to the memory (14) after being reduced vertically by 5/6 times compared to when the NTSC color video signal is supplied. It is possible to display both sides without defects. Further, according to this example, when the field frequencies for writing and reading the memory (14) are different, the memory (14) has different field frequencies.
4) Writing/reading is controlled to prevent two field signals from coexisting in the same field, so it is possible to avoid image quality deterioration such as the appearance of horizontal stripes on the screen.

Note that although the above-mentioned embodiment is an example in which the operation is performed using a remote control, the same applies to an operation in which the user directly presses an operation key.

Effects of the Invention According to the present invention described above, when writing a CCIR system (P/VL system or SECAM system) color video signal, the vertical direction is approximately 5/5 times smaller than that of an NTSC system color video signal. Since the data is written after being reduced six times, even if the image memory only has a capacity for the NTSC color video signal, a screen based on the CCIFi color video signal can be displayed without loss.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining the same. (2) and (3) are tuners, (4) are microcomputers, (6) (?) and (11) are switch circuits,
(8) and (9) are external input terminals, (10) and (12)
) is a signal processing circuit, (14) is a memory, (18) is a color picture tube, (19) is a deflection circuit, and (20) is a memory controller.

Claims (1)

[Claims] Receiving both a first color video signal of the PAL system or the SECAM system and a second color video signal of the NTSC system; A switching circuit is provided for driving the video display device in synchronization with a synchronization signal of the video signal and selectively supplying the first and second color video signals to the frame memory, and the switching circuit drives the video display device in synchronization with the synchronization signal of the video signal, and selectively supplies the first and second color video signals to the frame memory, and the first color video signal is stored in the frame memory. When writing a signal, the signal is reduced vertically by about 5/6 times compared to the second color video signal, and when reading from the frame memory, one of the color video signals is written. A television receiver characterized in that the signal is read out as a signal and supplied to the video display device.