JPS63263806A - Phase detection circuit - Google Patents

Phase detection circuit

Info

Publication number
JPS63263806A
JPS63263806A JP9840387A JP9840387A JPS63263806A JP S63263806 A JPS63263806 A JP S63263806A JP 9840387 A JP9840387 A JP 9840387A JP 9840387 A JP9840387 A JP 9840387A JP S63263806 A JPS63263806 A JP S63263806A
Authority
JP
Japan
Prior art keywords
signal
multiplier
converter
reference signal
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9840387A
Other languages
Japanese (ja)
Inventor
Toru Kitamura
透 北村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP9840387A priority Critical patent/JPS63263806A/en
Publication of JPS63263806A publication Critical patent/JPS63263806A/en
Pending legal-status Critical Current

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  • Processing Of Color Television Signals (AREA)

Abstract

PURPOSE:To perform phase measurement with high resolution, by multiplying an input signal to be detected by a reference signal having the same frequency component as that of the input signal, and multiplying the input signal multiplied by 2<n> to be detected by the reference signal multiplied by 2<n>. CONSTITUTION:A multiplier 10 multiplies the frequency of the input signal Vi to be detected by 2<n>, and an output signal is added on the input terminal on one side of a multiplier 11. A multiplier 12 multiplies the frequency of the reference signal CL outputted from a reference signal generator 4 by 2<n>, and the output signal is added on the input terminal on the other side of the multiplier 11. An A/D converter 14 which converts the output signal to a digital signal is connected to a low-pass filter 13 connected to the output terminal of the multiplier 11. A measured result obtained from the A/D converter 14 is provided with resolution higher than that of the measured result obtained from an A/D converter 7. The rough value of a phase difference is found from the measured result of the A/D converter 7, and the detailed value can be obtained from the measured result of the A/D converter 14.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、TV信号の色信号の検波などに用いられる位
相検波回路に関するものであり、詳しくは、デジタル信
号処理に適した回路を提供するものである。。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase detection circuit used for detecting color signals of TV signals, etc., and more specifically, provides a circuit suitable for digital signal processing. It is something. .

〔従来の技術] 例えば、NTSC方式のカラー映像信号の搬送色信号は
、送信側で2つの色信号1.0がD1搬送波で直角平衡
度IIされたものであり、副搬送波と同期した基準副搬
送波信号を用いて位相検波することにより夏信号および
Q信号を再生することができる。すなわち、■信号の大
きさをEl −、Q信号の大きさをEo=、副搬送波の
角周波数をωSとすると、搬送色信@ecは、 e(−EI′CogωB t+Eo−sinωs tと
なる。この搬送色信号etH,に基準副搬送波信号[□
5in(ωst十〇)を乗じるとともに、出力側にロー
パスフィルタを入れて第2高調・波成分を除去すること
により、 e  c  EQ  Sin   (ω Bt+  θ
 )=(EoEl   ′sinθ)/2+ (EoE
Q−008θ)/2となる。
[Prior Art] For example, the carrier color signal of a color video signal in the NTSC system is obtained by performing quadrature balance II on two color signals 1.0 with a D1 carrier wave on the transmitting side, and a reference subcarrier synchronized with the subcarrier. The summer signal and the Q signal can be reproduced by performing phase detection using the carrier signal. That is, if the magnitude of the ■ signal is El -, the magnitude of the Q signal is Eo=, and the angular frequency of the subcarrier is ωS, the carrier color signal @ec becomes e(−EI′CogωB t+Eo−sinωs t). This carrier color signal etH is added to the reference subcarrier signal [□
By multiplying by 5in (ωst 10) and inserting a low-pass filter on the output side to remove the second harmonic wave component, e c EQ Sin (ω Bt+ θ
)=(EoEl ′sinθ)/2+ (EoE
Q-008θ)/2.

ここで、基準副搬送波の位相をθ−〇にしてEa′si
nωs1に合わせると出力としてEQ′に比例した信号
が得られ、θ−π/2にしてEz”cosωstに合わ
せると出力としてEt−に比例した信号が得られる。
Here, the phase of the reference subcarrier is set to θ−〇, and Ea′si
When adjusted to nωs1, a signal proportional to EQ' is obtained as an output, and when adjusted to θ-π/2 and adjusted to Ez''cosωst, a signal proportional to Et- is obtained as an output.

第4図は、このような位相検波回路の一例を示す回路図
である。第4図において、1は被検波入力信号v1の入
力端子であり、乗算器2.3のそれぞれの一方の入力端
子に接続されている。4は被検波入力信号v1と等しい
周波数成分を有する基準信号OLを出力する基準信号発
生器であり、その出力信@CLは乗算器2の他方の入力
端子に接続されるとともに+90度の位相シフトを与え
る遅延回路5を介して乗算器3の他方の入力端子に接続
されている。6は乗算器2の出力端子に接続されたロー
パスフィルタであり、このローパスフィルタ6には出力
信号をデジタル信号に変換するA/D変換器7が接続さ
れている。8は乗算器3の出力端子に接続されたローパ
スフィルタであり、このローパスフィルタ8には出力信
号をデジタル信号に変換するA/D変換器9が接続され
ている。
FIG. 4 is a circuit diagram showing an example of such a phase detection circuit. In FIG. 4, reference numeral 1 denotes an input terminal for the wave input signal v1 to be tested, which is connected to one input terminal of each of the multipliers 2.3. 4 is a reference signal generator that outputs a reference signal OL having the same frequency component as the test wave input signal v1, and its output signal @CL is connected to the other input terminal of the multiplier 2 and has a phase shift of +90 degrees. It is connected to the other input terminal of the multiplier 3 via a delay circuit 5 which provides . A low-pass filter 6 is connected to the output terminal of the multiplier 2, and an A/D converter 7 for converting the output signal into a digital signal is connected to the low-pass filter 6. A low-pass filter 8 is connected to the output terminal of the multiplier 3, and an A/D converter 9 for converting the output signal into a digital signal is connected to the low-pass filter 8.

このように構成することにより、A/D変換器7からs
in成分に応じたデジタル信号が出力され、A/D変換
器9からCO8成分信0に応じたデジタル信号が出力さ
れることになる。
With this configuration, the A/D converter 7
A digital signal corresponding to the in component is output, and a digital signal corresponding to the CO8 component signal 0 is output from the A/D converter 9.

[発明が解決しようとする問題点] しかし、このような従来の構成で高分解能の測定結果を
得るためにはA/D変換器として高分解能特性を有する
ものを用いなければならず、回路構成が複雑になり、コ
ストも高くなってしまうという欠点がある。また、この
ためにはローパスフィルタの時定数を大きくしな番プれ
ばならず、回路のセトリング時間が長くなってしまう。
[Problems to be solved by the invention] However, in order to obtain high-resolution measurement results with such a conventional configuration, it is necessary to use an A/D converter with high-resolution characteristics, and the circuit configuration The disadvantage is that it becomes complicated and the cost becomes high. Further, for this purpose, the time constant of the low-pass filter must be increased, which increases the settling time of the circuit.

本発明は、このような点に羽目してなされたものであり
、その目的は、比較的簡単な構成で、高分解能の位相測
定が行える位相検波回路を提供することにある。
The present invention has been made in view of these points, and an object of the present invention is to provide a phase detection circuit that has a relatively simple configuration and can perform high-resolution phase measurement.

[問題点を解決するための手段] このような目的を達成する本発明は、 被検波入力信号と等しい周波数成分を有する基準信号を
出力する基準信号発生器と、 被検波入力信号の周波数を2n逓倍する第1の逓倍器と
、 基準信号の周波数を2n逓倍する第2の逓倍器と、 被検波入力信号と基準信号とを乗算するとともに各逓倍
器で2n逓倍された被検波入力信号と基準信号とを乗算
する乗算器と、 乗算器の出力信号をデジタル信号に変換するA/D変換
器、 とで構成されたことを特徴とする。
[Means for Solving the Problems] The present invention, which achieves the above objects, includes: a reference signal generator that outputs a reference signal having a frequency component equal to that of the input signal to be tested; a first multiplier that multiplies the frequency of the reference signal; a second multiplier that multiplies the frequency of the reference signal by 2n; A multiplier that multiplies signals, and an A/D converter that converts the output signal of the multiplier into a digital signal.

[実施例] 以下、図面を用いて本発明の実施例を詳細に説明する。[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例を示す回路図であって、si
n成分系統について示したものであり、第4図と同一部
分には同i符号を付けている。第1図において、10は
被検波入力信号■1の周波数を2n’i!j4F3する
第1の逓倍器であり、その出力信号は乗算器11の一方
の入力端子に加えられている。12は基準信号発生器4
から出力される基準信号OLの周波数を2n逓倍する第
2の逓倍器であり、その出力信号は乗算器11の他方の
入力端子に加えられている。なお、nは整数とする。1
3は乗算器11の出力端子に接続されたローパスフィル
タであり、このローパスフィルタ13には出力信号をデ
ジタル信号に変換するA/D変換器14が接続されてい
る。
FIG. 1 is a circuit diagram showing one embodiment of the present invention.
This figure shows an n-component system, and the same parts as in FIG. 4 are given the same i symbols. In FIG. 1, 10 indicates the frequency of the test wave input signal ■1 by 2n'i! j4F3, and its output signal is applied to one input terminal of the multiplier 11. 12 is a reference signal generator 4
This is a second multiplier that multiplies the frequency of the reference signal OL output from the multiplier 11 by 2n, and its output signal is applied to the other input terminal of the multiplier 11. Note that n is an integer. 1
3 is a low-pass filter connected to the output terminal of the multiplier 11, and an A/D converter 14 for converting the output signal into a digital signal is connected to this low-pass filter 13.

第2図はこのように構成された回路の動作を説明するた
めの波形図であり、(a)は基準信号CLを示し、(b
)は被検波入力信号viを示し、(C)は基準信号OL
が2逓倍された信@CL′を示し、(d)は被検波入力
信号V:が2逓倍された信号Vi−を示している。
FIG. 2 is a waveform diagram for explaining the operation of the circuit configured as described above, in which (a) shows the reference signal CL, and (b)
) indicates the test wave input signal vi, and (C) indicates the reference signal OL.
shows the signal @CL' which is doubled, and (d) shows the signal Vi- which is obtained by multiplying the input signal V: to be tested.

ここで、基準信号OLと被検波入力信号v1との時間差
を工すると、この時間差Tはこれら基準信号OLと被検
波入力信号Viの逓倍数に拘らず一定である。従って、
これら基準信@CLと被検波入力信号v1を2逓倍した
場合の位相差は2g3になる。すなわち、基準信号CL
をsinωctとし、被検波入力信号Viをsinωc
t+θとすると、基準信号CLが2逓倍された信号OL
=はsin 2ωatとなり、被検波入力信号Viが2
逓倍された信号vi′はsin 2ωci+2θとなる
Here, when the time difference between the reference signal OL and the wave input signal v1 is calculated, this time difference T is constant regardless of the multiplier of the reference signal OL and the wave input signal Vi. Therefore,
The phase difference when the reference signal @CL and the test wave input signal v1 are doubled is 2g3. That is, the reference signal CL
is sinωct, and the input signal Vi to be tested is sinωc.
If t+θ, the signal OL obtained by doubling the reference signal CL
= is sin 2ωat, and the test wave input signal Vi is 2
The multiplied signal vi' becomes sin 2ωci+2θ.

これにより、A/D変換器14から得られる測定結果は
、A/D変換器7の測定結果よりも高い分解能を有する
ことになる。これら測定結果の処理にあたっては、A/
D変換器7の測定結果から位相差の概略値を求め、A/
D変換!114の測定結果から詳細値を求めるようにす
る。ここで、逓倍数2nは2に限るものではなく、用途
に応じて任意の値に設定すればよい。
Thereby, the measurement results obtained from the A/D converter 14 have higher resolution than the measurement results from the A/D converter 7. In processing these measurement results, A/
An approximate value of the phase difference is obtained from the measurement results of the D converter 7, and the A/
D conversion! Detailed values are obtained from the measurement results of 114. Here, the multiplication number 2n is not limited to 2, and may be set to any value depending on the purpose.

このような構成によれば、分解能が比較的低いA/D変
換器を用いて分解能の高い測定結果を得ることができる
。すなわち、A/D変換器14の分解能をmビットとし
、逓倍数を2nとすると、(m+n)ピットの測定分解
能を得ることができる。そして、ローパスフィルタの時
定数を大きくしなくてよいことから、セトリング時間を
短くでき、高速測定が行える。
According to such a configuration, a measurement result with high resolution can be obtained using an A/D converter with relatively low resolution. That is, if the resolution of the A/D converter 14 is m bits and the multiplication number is 2n, a measurement resolution of (m+n) pits can be obtained. Furthermore, since it is not necessary to increase the time constant of the low-pass filter, settling time can be shortened and high-speed measurement can be performed.

なお、上記実施例では、各乗算器2,11にそれぞれロ
ーパスフィルタとA/D変換器で構成される信号変換系
統を設ける例を示したが、第3図に示すように連動した
切換スイッチ15.16で乗n器2の入力信号を切り換
えることにより、信号変換系統を1系統にすることもで
きる。
In the above embodiment, each multiplier 2, 11 is provided with a signal conversion system consisting of a low-pass filter and an A/D converter, but as shown in FIG. By switching the input signal of the multiplier 2 by .16, the number of signal conversion systems can be reduced to one.

なお、上記実施例では、TV信号の色信号の検波回路と
して用いる例を説明したが、モデム信号のような位相変
調された各種の信号の検波にもイi効である。
In the above embodiment, an example has been described in which the detection circuit is used as a detection circuit for a color signal of a TV signal, but it is also effective for detection of various phase-modulated signals such as a modem signal.

E′R明の効果] 以上説明したように、本発明によれば、比較的mttt
な構成で、高分解能の位相測定が行える位相検波回路が
実現でき、実用、Eの効果は大きい。
Effect of E′R Light] As explained above, according to the present invention, relatively mttt
With this configuration, a phase detection circuit capable of high-resolution phase measurement can be realized, and the practical effect of E is great.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示プ回路図、第2図は第1
図の動作を説明するための波形図、第3図は本発明の他
の実施例を示す回路図、第4図は従来の回路偶因である
。 1・・・入力端子、2.11・・・乗算器、4・・・ク
ロック発生器、6.13・・・ローパスフィルタ、7.
14・・−A/D変換器、10.12・・・逓倍器、1
5゜第3図 j 第4図
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a conventional circuit diagram. 1... Input terminal, 2.11... Multiplier, 4... Clock generator, 6.13... Low pass filter, 7.
14...-A/D converter, 10.12... Multiplier, 1
5゜Figure 3j Figure 4

Claims (1)

【特許請求の範囲】 被検波入力信号と等しい周波数成分を有する基準信号を
出力する基準信号発生器と、 被検波入力信号の周波数を2^n逓倍する第1の逓倍器
と、 基準信号の周波数を2^n逓倍する第2の逓倍器と、 被検波入力信号と基準信号とを乗算するとともに各逓倍
器で2^n逓倍された被検波入力信号と基準信号とを乗
算する乗算器と、 乗算器の出力信号をデジタル信号に変換するA/D変換
器、 とで構成されたことを特徴とする位相検波回路。
[Scope of Claims] A reference signal generator that outputs a reference signal having a frequency component equal to that of the input signal to be tested; a first multiplier that multiplies the frequency of the input signal to be tested by 2^n; and a frequency of the reference signal. a second multiplier that multiplies the input signal by 2^n, and a multiplier that multiplies the input signal to be detected by the reference signal and the input signal to be tested multiplied by 2^n by each multiplier, and the reference signal. A phase detection circuit comprising: an A/D converter that converts an output signal of a multiplier into a digital signal.
JP9840387A 1987-04-21 1987-04-21 Phase detection circuit Pending JPS63263806A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9840387A JPS63263806A (en) 1987-04-21 1987-04-21 Phase detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9840387A JPS63263806A (en) 1987-04-21 1987-04-21 Phase detection circuit

Publications (1)

Publication Number Publication Date
JPS63263806A true JPS63263806A (en) 1988-10-31

Family

ID=14218866

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9840387A Pending JPS63263806A (en) 1987-04-21 1987-04-21 Phase detection circuit

Country Status (1)

Country Link
JP (1) JPS63263806A (en)

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