JPS63262768A - Pattern detecting signal binarization circuit - Google Patents

Abstract

PURPOSE:To constantly obtain a proper slice level by following a slice level to an original signal with respect to a base material part to be detected and reducing the slice level with a constant coefficient with respect to a pattern part to be detected. CONSTITUTION:A pattern detecting signal and the slice level from a buffer 19 are compared in a comparator 20 to output a binarization signal and a switch 11 is opened and closed according to this signal. In the base material part to be detected, the output of the comparator 20 goes to a low level to turn on the switch 11 and time constant circuits 12, 13 are charged, so that the output of a buffer 15 is substantially similar to the original signal and said slice level follows the original signal. In the pattern part to be detected, the output of the comparator 20 goes to a high level to turn off the switch 11, an electric charge stored in the tie constant circuits 12, 13 is discharged, the output of the buffer 15 is gradually reduced, so that said slice level is reduced with the constant coefficient.

Description

[Detailed Description of the Invention] [Summary] The present invention uses the binary output of the circuit itself to determine whether the object to be detected is a pattern part or a base material part, and if it is a base material part, the slice level is determined. This circuit relates to a circuit that follows the original signal to be binarized, reduces the slice level by a certain coefficient in the case of a pattern part, and thereby always converts it to an appropriate slice level. It is something.

[Industrial application field]

The present invention relates to a pattern detection signal binarization circuit for binarizing an original signal detected from a detection target such as a printed circuit board and making the signal correspond to a pattern portion and a base material portion.

[Conventional technology]

The basic configuration of a conventional binarization circuit is shown in FIG. 3, and a diagram illustrating its operation is shown in FIG. 4. The binarization circuit shown in FIG. 3 uses a fixed slice level. In pattern detection using a blank line illumination method in which a linear light-shielding band is provided on the object to be detected and reflected and scattered light is detected, the detection signal strength in areas with high pattern density (areas with many conductive patterns) is The signal strength is smaller than that of a portion with low pattern density. This is because the black line illumination method is based on the amount of diffused leakage light from around the black line. Therefore, when a fixed slice level is used, as shown in FIG. 3, when the pattern detection signal is compared with the fixed slice level obtained from the power supply voltage ■ and the variable resistor 32 by the comparator (COMP) 31, as shown in FIG. A binarized signal as shown in is obtained.

In FIG. 4, the upper part shows the pattern to be detected, and the diagonally shaded part is the conductor pattern part. The part without diagonal lines is the base material part. A pattern detection signal obtained by detecting this pattern along a line is shown as a solid curve 41 in the waveform diagram in the middle part of FIG. The fixed slice level is indicated by strand vA42. As can be seen from the figure, the detection signal becomes smaller in areas where the conductor pattern density is high (round broken line 4
(See part 4).

Therefore, the pattern detection signal 41 and the fixed slice level 4
2, a corresponding binary signal as shown by the solid line in the lower part of FIG. 4 can be obtained. However, in this case, the ideal slice level is the dashed line 43, and a signal like the dashed line is desired as the binarized signal. Note that G indicates the ground level.

Another conventionally used circuit is a binarization circuit using an integral slice level shown in FIG.

In this circuit, the comparator 53 compares the pattern detection signal and the integral value of the pattern detection signal and converts them into binary values. That is, the pattern detection signal is supplied to one input terminal of the comparator 53, and is also supplied to an integrating circuit consisting of a resistor 56 and a capacitor 57. The output of the integrating circuit is supplied to the other input terminal of the comparator 53 via a buffer (B) 51 and a variable resistor 54. The circuit that supplies voltage from the power supply V to the other input terminal of the comparator 53 via the variable resistor 55, buffer 52, and diode 58 is for maintaining the lowest slice level (minimum limit).

The operation of the above circuit will be explained using FIG.

In FIG. 6, similarly to FIG. 4, the pattern to be detected is shown in the upper row, the pattern detection signal 51 is shown in the middle row, and the binary signal is shown in the lower row, respectively. In this case, the slice level is as shown by the chain line 52, and the binarized signal is as shown by the lower solid line. The ideal slice level in this case is desired to be a level as shown by the broken line 53, and when this slice level is used, the binarized signal will be modified as shown by the broken line.

[Problem that the invention seeks to solve]

As described above, when the binarization circuit uses a fixed slice level, the intensity of the detection signal changes depending on the density of the pattern portion, making it impossible to perform binarization using an appropriate slice level.

Further, even if an integral slice level is used, it may not be possible to follow sudden changes in the pattern (such as changes from a low pattern density part to a high pattern density part), and there is a problem that proper binarization is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a binarization circuit that can binarize a pattern detection signal at an appropriate slice level regardless of changes in pattern density of a detection target and improves detection accuracy.

[Means for solving problems]

As illustrated in FIG. 1, the circuit of the present invention includes a comparison means 20, a switching means 11, a buffer 15, a time constant circuit
, 13, lowest slice level supply circuit 14゜16 , 1
B.

The comparison means 20 receives the pattern detection signal of the object to be detected at one input, receives the output of the buffer 15 at the other input, compares the two, and outputs a binary signal. The input of the buffer 15 receives the pattern detection signal via the switching means 11 and time constant circuits 12 and 13, and the switching means 11 is opened and closed by the output of the comparison means 20, and the time constant circuits 12 and 13
is charged when the switching means 11 is closed and discharged when the switching means 11 is opened, and the lowest slice level supply circuits 14 and 16
, 18 are arranged to hold the lowest value when the output level of the buffer 15 becomes lower than a preset lowest value.

[For production]

If the above-mentioned pattern detection signal binarization circuit is used, the slice level will be a floating type that follows the original signal, and even a pattern in a portion where the detection signal intensity is low as illustrated in the middle part of FIG. 4 can be sliced at an appropriate level. When tracking the original signal at the slice level, the base material follows at high speed,
In the pattern portion, it does not follow, but decreases with a specific time constant depending on the pattern to be inspected. An excessive drop in the slice level in the pattern portion is prevented by a minimum slice level supply circuit that sets a lower limit value of the slice level.

〔Example〕

A circuit diagram of a pattern detection signal binarization circuit as an embodiment of the present invention is shown in FIG. 1, and a diagram for explaining the operation is shown in FIG.

This circuit includes a comparator (COMP) 20, a switch 11, a capacitor 12, a resistor 13, and a buffer (B) 1.
5 and 16, variable resistors 14 and 17, diode 1
8, and a buffer (B) 19.

The pattern detection signal from the object to be detected is sent to the comparator 20.
and one terminal of the switch 11. The other terminal of switch 11 is connected to capacitor 12.
and resistor 13, and the other ends of capacitor 12 and resistor 3 are grounded. switch 11
The other terminal of is simultaneously connected to the input of buffer 15. The output of buffer 15 is supplied to the input of buffer 19 via variable resistor 17. A power supply voltage V is supplied to the input of the buffer 16 via a variable resistor 14 .

The output of buffer 16 is supplied via diode 18 to the input of buffer 19. The output of buffer 19 is supplied to the other terminal of comparator 20. The opening and closing of the switch 11 is controlled by the output of the comparator 20.

The output of the comparator 20 is at a high level or a low level depending on the presence or absence of a pattern. When there is no pattern, that is, when the intelligence signal corresponds to the base material portion, the output of the comparator 20 becomes a low level and the switch is closed (turned on). Since the value of the capacitor 12 is about 100 pF or less, it is quickly charged, and the voltage at the output of the buffer 15 has a waveform almost similar to the original signal. If there is a pattern,
That is, when the output of the comparator 20 is at a high level,
Switch 11 is opened (off). Then capacitor 1
The charge accumulated in 2 is discharged by the time constant of CR,
The voltage at the output of buffer 15 gradually decreases. When the input voltage of the buffer 19 becomes lower than the output voltage of the buffer 16, the diode 18 becomes conductive, and the lowest value of the slice level becomes approximately the output voltage of the buffer 16. The lowest value of the slice level is set by the variable resistor 14. The variable resistor 17 adjusts the ratio between the detected signal strength and the slice level.

In FIG. 2, the pattern to be detected is shown at the top. The shaded portion is the pattern portion, and the other portions are the base material portion. A pattern detection signal that detects the linear portion is shown as a solid curve 21 in the next stage. The slice level is a chain! 23, in the part without a pattern, that is, in the base material part, it follows the pattern detection signal, but in the part with a pattern, it decreases with the time constant CXR. The ideal slice level in this example pattern is shown by dashed line 22. This shows that the slice level of the circuit of the embodiment is more appropriate than that of the conventional circuit. The third row of FIG. 2 shows the binarized signal. The bottom row shows how the switch 11 opens and closes in response to the binary signal.

〔Effect of the invention〕

According to the present invention, it is possible to binarize a pattern detection signal with an appropriate slice level regardless of changes in pattern density of a detection target, and as a result, it is possible to realize an improvement in detection accuracy.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a pattern detection signal binarization circuit as an embodiment of the present invention, Fig. 2 is a diagram explaining the operation of the circuit of Fig. 1, and Fig. 3 is a conventional binarization circuit. 4 is a diagram explaining the operation of the circuit of FIG. 3, FIG. 5 is a circuit diagram of another conventional binarization circuit, and FIG. 6 is a diagram of the circuit of FIG. 5. It is a figure explaining operation. In the figure, 11... Switch, 12... Capacitor, 13... Resistor, 14, 17... Variable resistor, 15, 16, 19... Buffer, 1
8...Diode, 20, 31...Comparator, 32...Variable resistor, 51.52...Buffer,
53... Comparator, 54, 55...
Variable resistor, 56...Resistor, 57...Capacitor, 58...Diode.

Claims (1)

[Claims] Comparing means (2
0), a buffer (15) that receives the pattern detection signal via the switching means (11) and supplies the output to the other input of the comparison means (20), and the output of the buffer (15) is set in advance. When the lowest value is equal to or lower than the lowest value, the lowest value is compared with the comparing means (20).
The lowest slice level supply circuit (
14, 16, 18), and an input terminal of the buffer (15) and the switching means (11).
), the switching means (11) includes a time constant circuit (12, 13) for discharging the electric charge charged in a predetermined time constant between The circuit is closed to charge the time constant circuit (12) when corresponding to the base material portion to be detected, and the circuit is opened to discharge when corresponding to the pattern portion, and the output of the comparison means (20) is binarized. A pattern detection signal binarization circuit designed to obtain signals.