JPH0124372B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binarization circuit that can accurately binarize an input signal even during rising and falling portions of an analog input signal.

When automatically performing quality inspections of industrial products, pattern inspections of printed circuit boards, etc., the object to be inspected is imaged with a television camera, etc., converted to an electrical signal, and this electrical signal is compared with an appropriate threshold level to generate a binary value. turned into
Determination of flaws, defects, etc. is performed based on this binary signal. When such signals are to be binarized, conventionally, a floating level binarization circuit as shown in FIG. 1, for example, has often been employed. In the figure, COMP1 and COMP2 are comparators, DAT is a delay/attenuation circuit, and AND is an AND gate. Further, FIG. 2 is an explanatory diagram of the operation of FIG. 1.

If the signal shown by the solid line in Fig. 2A is input to the binarization circuit shown in Fig. 1, the delay/attenuation circuit
The output signal of the DAT is shown by the broken line in the figure.
The comparator COMP1 compares the output signal of the delay/attenuation circuit DAT with the input signal as a floating reference level, and outputs a binary signal as shown in FIG. 1B, for example. Also, the comparator COMP2 is connected to the input signal A in the same figure.
A gate signal shown in C in the same figure is output by comparing with a fixed level threshold value as shown in the dotted line STD. Therefore, the signal output from the AND gate AND is not affected by the background, as shown in FIG. However, as is clear from FIG. D, there is a drawback in that it is not possible to remove the chatter-like noise caused by the influence of noise present in the falling portion of the input signal.

The present invention has been made in view of the above-mentioned drawbacks of the conventional art, and its purpose is to provide a highly sensitive binarization circuit that does not produce any chatter in either the rising or falling portions. be.

The details of the present invention will be explained below with reference to Examples.

FIG. 3 is a block diagram of an embodiment of the present invention, in which 1 is an inversion sample and hold circuit, 2 is an operational amplifier, 3 to 5 are delay circuits, 6 to 9 are comparison circuits, 10 is a timer circuit, 11 to 13 is a logic gate.

The input terminal 18 receives an analog signal with an appropriate waveform to be binarized. It is assumed that a video signal 40 having a waveform as shown in FIG. 4 is received. Assuming that the brightness of the object to be observed by the television camera is higher than the background level, the background black level and the signal of the object to be observed are signals 38 and 3, respectively.
The result will be as shown in 9. 41 is a horizontal synchronization signal. Normally, the black level 38 changes depending on the operating temperature, the illumination conditions of the object, and the like. In order to sample the black level 38 that varies in this manner, a sample command signal 42 is supplied to the input terminal 19 of FIG. The waveform 39 of the video signal is uniform as illustrated by the solid line in FIG. 4 if there is no defect in the object to be inspected, but if there is a defect, a defect signal 67 as illustrated by the dotted line is included.

The inverted sample and hold circuit 1 receives the video signal 4
0 and the sample command signal 42, the operational amplifier 2 outputs a voltage having the same absolute value and opposite sign to the black level 38.
Output to. The operational amplifier 2 performs addition and non-rotation amplification of the input voltage and the video signal 40, and the fifth
An A video signal 20 as shown in the figure is output.

That is, the reverse sample and hold circuit 1 receives the sample and hold command signal 42 and samples and holds the black level 38 out of 40 of the video signal.
A signal having the same absolute value and the opposite sign is output to the operational amplifier 2. The operational amplifier 2 adds and amplifies the output signal of the inversion sample and hold circuit 1 and the video signal 40 to create a signal in which the black level matches the zero level. Add the negative voltage to 20 in Figure 5.
As shown in FIG. 2, an A video signal 20 is output in which the black level 38 of the video signal 40 is shifted by a certain amount to the negative side.

In this way, the circuits 1 and 2 constitute a shift means for shifting the video signal 40, which is an analog signal, by a certain amount to the negative side.

The A video signal 20 is input to a comparator circuit 6 which is a first signal generating means, and the other input terminal of this comparator circuit is connected to a fixed threshold value generating circuit 56, which generates a fixed threshold value as shown in FIG. It receives voltage 55. As a result, the comparator circuit 6 outputs the WiDTH signal 32, which is the first signal having a waveform as shown in FIG. The WiDTH signal 32 is input to the AND gate 13 and the timer circuit 10. Timer circuit 10
uses WiDTH signal 32 as a trigger signal.
Second signals that rise together with the WiDTH signal, that is, a short signal CUT1 signal 28, a medium signal CTU2 signal 29, and a long signal CTU3 signal 30 are generated. The details of the configuration of the timer circuit 10 will be described later.

In FIG. 3, the A video signal 20 is transferred to a suitable delay means such as attenuated passive delay elements 3, 4.
GND signal 31 delayed through each of 5
(FIG. 5), a B video signal 21, a C video signal 22, and a D video signal 23 are created in the same order. Each of these video signals 2
1, 22, 23 are variable resistors 16 which are damping means.
Alternatively, the CMP11 signal 33, the CMP12 signal 35, and the CMP13 signal are inputted to the comparison circuits 7, 8, and 9, which are comparison means, via the signal 17 or directly, and are the comparison outputs.
A signal 36 is generated. First, the CMP11 signal 33 will be explained.

The A video signal 20 is attenuated by a suitable amount by a variable resistor 17 to become an A video 11 signal 25, which is input via the resistor to the inverting input terminal of a comparator circuit 7 using an operational amplifier, which is the first comparison means. . Although the A video 11 signal 25 has a smaller delay amount than the B video signal 21, it is attenuated more than the B video signal 21 by the variable resistor 17. On the other hand, this inverting input terminal is grounded via a transistor 15, and the ON/OFF state of this transistor is controlled by the CUT1 signal 28 via the integrating circuit 14. A preferred example of the integrating circuit 14 is one that includes a diode so that the charging time constant is sufficiently shorter than the discharging time constant.

As shown in FIG. 6, the CUT1 signal 28 rises a short time after the A video 11 signal 25 rises. Therefore, the integrating circuit 14 is rapidly charged and the transistor 15 is immediately turned on, and the A video 11 signal rapidly changes to the GND signal 31 immediately after its rise.
descend to After this state continues for a certain period of time,
CUT1 signal 28 falls. Along with this, the integrating circuit 14 gradually discharges, and the transistor 15 gradually approaches the off state. As a result, the waveform of the A video 12 signal 26 input to the inverting input terminal of the comparison circuit 7 is as shown in FIG. As a result, the A video 12 signal 26 and the B video signal 21 are
While in GND signal 31, that is, CUT1 signal 28
intersects at a very sharp angle while is at a high level. Since the A video 12 signal 26 has such a waveform, even if the signals 21 and 26 are brought closer together by adjusting the variable resistor 17 in order to increase the defect detection sensitivity, the occurrence of chatter near the intersection can be avoided. As shown in FIG. 7, it is possible to detect minute defects present in the rising portion.

In short, the A video 12 signal 26 and the B video signal 21 cross each other at an acute angle at the rising edge of their waveforms to prevent the occurrence of chatter.
The CUT1 signal 28 functions to determine this chatter prevention period. In this embodiment, A video signal 2
0 and the B video signal 21, the comparison circuit 7 outputs the CMP11 signal 33. For example,
B video signal 21 instead of A video signal 20,
The C video signal 22 may be used instead of the B video signal 21. In this case, the B video signal 21 has a smaller delay amount than the C video signal 22, is attenuated by the variable resistor 17 more than the B video signal 21, and is input to the comparator circuit 7.

Next, the CMP12 signal 35 and CMP12' signal 35' will be explained. As shown in FIG. 3, the B video signal 21 and the A video 11 signal 25 are compared by a comparison circuit 8, which is a second comparison means, and a CMP12 signal 35 is generated.
get. Next, the second logical means, OR gate 1
1, the above signal 35 and the CUT2 signal 29 are ORed to obtain a CMP12' signal 35', which is input to the AND circuit 13, which is the first logic means. Time charts at this time are shown in FIGS. 8 and 9 for non-defective products and defective products, respectively. If you try to adjust the variable resistor 17 to bring the signals 21 and 25 closer together to increase the defect detection sensitivity,
Since the CMP12 signal 35 tends to cause chatter at the rising edge, OR logic is performed between this signal and the CUT2 signal 29 to prevent the occurrence of chatter. Therefore, while the CUT2 signal 29 is at a high level, the defect detection function by the CMP12 signal 35 is disabled.
The defect detection function of CMP12 signal 35 is CUT2 signal 2
It is limited to only after the falling edge of 9.

Next, the CMP13 signal 36 and CMP13' signal 36' will be explained. The CMP11 signal 33 mentioned above,
As shown in FIGS. 6 to 9, the CMP12 signal 35 attenuates the amplitude of the signal with the smaller delay amount among the two signals to be compared, so defects in the rising portion of the waveform can be detected. However, it is not suitable for detecting defects in the falling part. Therefore, as shown in the configuration diagram of FIG. 3 and the waveform diagrams of FIGS. 10 and 11, the D video signal 23 having a larger delay amount than the C video signal 22 is attenuated by the variable resistor 16, and the C video signal 22 is obtained, and this signal and the C video signal 22 are
A comparison circuit 9, which is a third comparing means, performs a comparison with CMP13 signal 36. FIG. 10 shows the case where there is no defect, and FIG. 11 shows the case where there is a defect, but the structure is such that it is easy to detect defects in the falling portion of the signal. Even in this case, if you try to increase the defect detection sensitivity, a chatter will occur at the rising edge of the waveform, so the CMP13 signal 36 and CUT3 signal 30 are ORed in the OR gate 12, which is the third logic means. By obtaining the 'signal 36', this difficulty is overcome.

On the other hand, the CUT3 signal 30 cannot prevent the CMP13' signal 36' from chattering that occurs at the falling edge of the waveform, but this signal is ANDed with the WiDTH signal 32 in the AND gate 13. Therefore, the above-mentioned chatter in the falling portion is effectively eliminated by this AND logic. This means that the tail of CMP13' signal 36' is WiDTH signal 3
This is due to the fact that it does not overlap with 2. For this reason,
Although the CMP13' signal 36' cannot detect all falling edge defects on the video signal,
This is particularly effective for detecting defects when there is a gentle undulation in the latter half of the waveform, as illustrated in the figure.
In this embodiment, the D video signal 23 is connected to the variable resistor 1.
The comparison circuit 9 compares the D video signal 24 and the C video signal 22 attenuated in step 6, and outputs the CMP13 signal 36.
However, without using the variable resistor 16, for example, the B video signal 24 can be input instead of the D video signal 24.
1, A video signal 2 instead of C video signal 22
0 may be used, and these two signals may be compared by the comparison circuit 9. In this case, the B video signal 21 has a larger delay amount than the A video signal 20 and is a more attenuated signal.

Comparison result signals 33, 3 obtained in this way
5' and 36' are input together with the WiDTH signal 32 to an AND circuit 13, which is a first logic means, and a binary signal 27 is obtained as its output.

FIG. 12 is a circuit diagram showing an embodiment of the timer circuit 10 of FIG. 3 when a television camera is used as a sensor. 43, 44, 45, and 46 are all JK flip-flops, 47 and 48 are all counters, 57 to 59 and 60 to 66 are all NAND gates, 52 to 54 are output terminals of this timer circuit 10, and symbol VP5 is 5 volts. This is the power terminal. A clock signal of approximately several MHz is input to the clock signal input terminal 49. First, when the horizontal synchronizing signal 41 is applied to the horizontal synchronizing signal input terminal 51, the JK flip-flops 43, 44, 4
5 and 46 are all reset. At this time,
Counters 47 and 48 receiving a low level from the Q terminal of JK flip-flop 43 are also reset.
Also, since the JK flip-flop 43 is at a high level, the output terminal 52 of the gate 57 that supplies the CUT2 signal, the output terminal 53 of the gate 58 that supplies the CUT1 signal, and the gate 5 that supplies the CUT3 signal.
All output terminals 54 of No. 9 are at low level. This is the initial state of the counter circuit 10.

After this, WiDTH is connected to the WiDTH signal input terminal 50.
When the signal 32 is input and subsequently the clock signal is input to the clock signal input terminal 49, the Q output of the JK flip-flop 43 becomes a low level, and as a result, the output terminals 52, 53, All 54 rise from low level to high level. At the same time, the counters 47 and 48, which have received the high level Q output of the JK flip-flop 43, come out of the reset state and start counting the clock signals. The count values of counters 47 and 48 are output from the counters to the output signal line and gate 6.
When the predetermined value set by the combination of 0, 61, and 62 is reached, each gate circuit outputs a pulse, and this pulse output is sent to the gate circuits 63, 64, and 64, respectively.
Synchronization with the clock is established at 65 to trigger the clock input terminals of JK flip-flops 44, 45, and 46. As a result, the Q outputs of the JK flip-flops 44, 45, and 46 become high level, and are passed through the gate circuits 57, 58, and 59 to CUT2.
The output terminals 52, 53, and 54 of the signal 29, CUT1 signal 28, and CUT3 signal 30 are caused to fall to a low level. In this way, the waveform shown in Figure 5 is created.
Can supply CUT1, CUT2, CUT3 signals. The JK flip-flops 43 to 46 and the counters 47 and 48 may be any suitable integrated circuits, and for example, commercially available products SN74107 and SN74161 manufactured by Texas Instruments, Inc. may be used, respectively.

As explained above, in one embodiment of the present invention, CUT1, CUT2,
Under the control of each signal of CUT3, defects are inspected mainly using the CMP11 signal 33 for the rising part of the waveform, and the CMP12 signal 33 is used for the rising part of the waveform.
The configuration is such that the signal 35 is used as the main component to inspect for defects, and the falling portion of the waveform is tested for defects using the CMP13 signal 36 as the main component. In other words, by slightly lowering the detection sensitivity at the rising edge of the waveform, we ensured the prevention of chatter.
Defects are detected using the CMP11 signal 33, and after the waveform rises, where there is little risk of chatter,
Defects are detected using the CMP12 and 13 signals, which have high detection sensitivity. With such a configuration, the defect detection sensitivity can be increased while effectively preventing the occurrence of chatter.

In the embodiment described above, three delay circuits, 3
Although comparison circuits 7, 8, and 9 are provided as comparison means, the number of delay circuits may generally be two or more as appropriate. Further, the number of comparison circuits serving as comparison means may generally be three or more as appropriate.

[Brief explanation of drawings]

Figures 1 and 2 are a block diagram of a conventional example and an explanatory diagram of its operation, Figure 3 is a block diagram of an embodiment of the present invention, and Figures 4 to 11 are for explaining the operation of Figure 3. FIG. 12 is a circuit diagram of an embodiment of the timer circuit 10 in FIG. 3. DESCRIPTION OF SYMBOLS 1... Reverse sample hold circuit, 2... Operational amplifier, 3 to 5... Delay circuit, 6 to 9... Comparison circuit, 10... Timer circuit, 11 to 13...
Logic gate, 14...Integrator circuit, 43 to 46...
...JK flip-flop, 47, 48... counter, 57 to 59, 60 to 66... and gate.

Claims (1)

[Claims] 1. Shifting means for shifting the analog signal to a constant voltage level based on the level at a predetermined point on the analog signal and outputting the same, and n units for dividing and delaying the shifted analog signal output into n stages (n is a natural number). delay means, m attenuation means (m is a natural number equal to or less than n), and at least one unit that inputs and compares predetermined two signals among the respective output signals of the shift means, the delay means, and the attenuation means. a first comparing means, at least one second comparing means, and at least one third comparing means, and generating a signal only during a period in which the shifted analog signal has a value equal to or greater than a predetermined value. a first signal generating means; and, using the first signal as a trigger, generate three types of second signals (hereinafter referred to as a timer means for generating a short signal, a medium signal, and a long signal; and switch means provided in the same number as the first comparison means and for lowering one input of the first comparison means to the ground level;
the same number of second comparing means for generating logical sums as the second comparing means;
logic means, third logic means for generating an OR of the same number as the third comparison means, the first signal, the output of the first comparison means, and the second and third logic means. and a first logic means for generating an AND with a logical sum generated by the above, and the predetermined two signals to be compared by the first comparison means and the second comparison means are such that at least one of them is delayed. The signal is
and the shift means, the delay means, and the attenuation means are connected to the first comparison means and the second comparison means, respectively, so that a signal with a smaller delay amount is attenuated more than a signal with a larger delay amount. , at least one of the two predetermined signals to be compared by the third comparison means is a delayed signal, and the signal with a larger amount of delay is attenuated more than the signal with a smaller amount of delay, The shift means, the delay means and the attenuation means are connected to the third comparison means, the short signal generated by the timer means is inputted to the switch means, and the time of the short signal is equal to the first The timer means, the switch means, and the first comparison means are connected so that the input having a larger amount of attenuation input to the comparison means is lowered to the ground level, and the second
The logic means is configured to generate a logical sum of the medium signal generated by the timer means and the output signal of the second comparison means, and the third logic means is configured to generate a logical sum of the intermediate signal generated by the timer means and the output signal of the second comparison means. An analog signal binarization circuit characterized in that it is configured to generate a logical sum of a long signal and an output signal of the third comparison means.