JPS6417181A - Optical picture input device - Google Patents

Optical picture input device

Info

Publication number
JPS6417181A
JPS6417181A JP62173170A JP17317087A JPS6417181A JP S6417181 A JPS6417181 A JP S6417181A JP 62173170 A JP62173170 A JP 62173170A JP 17317087 A JP17317087 A JP 17317087A JP S6417181 A JPS6417181 A JP S6417181A
Authority
JP
Japan
Prior art keywords
level
signal
picture signal
slice level
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62173170A
Other languages
Japanese (ja)
Inventor
Shinya Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP62173170A priority Critical patent/JPS6417181A/en
Publication of JPS6417181A publication Critical patent/JPS6417181A/en
Pending legal-status Critical Current

Links

Landscapes

  • Character Input (AREA)
  • Image Input (AREA)

Abstract

PURPOSE:To select a constantly proper binarization condition irrespective of a printing state by comparing the level of a picture signal with a prescribed slice level and deciding the slice level based on the result. CONSTITUTION:A comparator 1 compares a picture signal P with the prescribed slice level A and when the picture signal P is higher than the level A, a high level control signal CH is outputted and when it is low, a low level control signal CL is outputted. A delay circuit 2 delays the picture signal P to form a time allowance until and A/D converting circuit 3 normally operates. Then, the A/D converting circuit 3 raises the slice level B at the time of inputting the signal CH from a comparator 1 and on the contrary, at the time of inputting the signal CL, it lowers the slice level B. The slice level B can be fixed to change the level of the picture signal P.
JP62173170A 1987-07-10 1987-07-10 Optical picture input device Pending JPS6417181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62173170A JPS6417181A (en) 1987-07-10 1987-07-10 Optical picture input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62173170A JPS6417181A (en) 1987-07-10 1987-07-10 Optical picture input device

Publications (1)

Publication Number Publication Date
JPS6417181A true JPS6417181A (en) 1989-01-20

Family

ID=15955390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62173170A Pending JPS6417181A (en) 1987-07-10 1987-07-10 Optical picture input device

Country Status (1)

Country Link
JP (1) JPS6417181A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0493204U (en) * 1990-02-17 1992-08-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0493204U (en) * 1990-02-17 1992-08-13

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