JPS6326135A - Line switching device - Google Patents

Abstract

PURPOSE:To improve the degree of random processing of a data signal even without extending frame length of each stage by stacking the frame in 2-stage by a 1st transmission signal processing circuit and a 2nd or 3rd transmission signal processing circuit and using a scramble pattern differenct in repeating period at each stage to scramble the data signal. CONSTITUTION:A data signal D3 is scrambled in 2-stage by the 1st and 2nd scramble patterns. Then the data signal is scrambled by such a long repeating period as 199000 bits being the least common multiple of respective patterns and the data signal D3 is subject to sufficiently high random processing regardless of the 1st and 2nd scramble patterns are repeating periods of comparatively short. The repeating periods of the 1st and 2nd scramble patterns are selected to be comparatively short and the least common multiple is selected to be large as required. Thus, the degree of random processing of the scrambled data is increassed without prolonging the line switching time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line switching device, and particularly to a line switching method for switching between a working line and a protection line without code errors in a digital wireless communication system.

[Conventional technology]

Large-capacity wireless communication systems usually have a backup line in addition to the working line in case of line maintenance, fading, equipment failure, etc.

In a digital wireless communication system, if there is a propagation delay difference between the working and backup lines that are switched, the synchronization between the output signals of both lines may be lost and a sign error υ may occur when switching lines. A line switching device is often used that synchronizes the output signals of both lines and switches the line without code errors.

FIG. 2 is a block diagram showing an example of such a conventional line switching device.

The conventional example shown in FIG. 2 is used in a digital wireless communication system consisting of a working line and one protection line, and it transmits two data signals each from a transmitting carrier terminal station (not shown). Input one branch output of each of the branching hybrids (hereinafter referred to as HYB) l-1 to l-, a test pattern generator (hereinafter referred to as TE8TPG) 2, and HYBI-1 to 1- and the output of TESTPG. A switch 3 outputs one of these inputs, and a transmission signal processing circuit (hereinafter referred to as TXD) inputs the output of the switch 3.
TXDPUs 14-1 to 14 which input the other branch outputs of PU) 14-0 and HYBI-1 to HYBI-1- and output one of the two outputs to the respective working lines.
−, the output of TXDPU14-O and TXi)P
A transmission switching circuit (hereinafter referred to as TX
SW) 15, and a frame synchronization circuit (hereinafter referred to as FSYN) which inputs the respective outputs of the protection line and working line.
C) 16-o to 16-, FSYNC16-0
A received signal distribution device (hereinafter referred to as XDIST) 17 that branches the output of (k+1), and a synchronous switching circuit (hereinafter referred to as 8YNC8W) 18-1 to 18-, 几XDI8T17・5YNC
The received signal processing circuits (hereinafter referred to as XDPUs) 19-0 to 19-, which input the outputs of 8WIs 8-1 to 18-, and the test pattern detector (hereinafter referred to as TESTPD) 1
2 and the outputs of RXDPUIs 9-0 to 19- are input, the outputs of RXDPUIs 9-1 to 19- are output to the receiving carrier terminal station (not shown), and the output of RXDPUIs 9-0 is input to the TE.
Output to STPD12 or RXDPU19-1
～19-The rest except the inside and RXDPUl 9-
0 to the receiving carrier terminal station.

First, the operation of the conventional example shown in FIG. 2 will be described for the case where all lines are normal and the protection line is on standby.

Data signals from the transmitting carrier terminal station are normally bipolar, and one of them, for example, data signal D1, is input to the TXDPU 14-1 via HYBl-1. TXDPU14
-1 is a frame synchronization bit for converting the input data signal D1 to unipolar, rate conversion, and configuring a frame, a parity check bit, and an ID code for line identification.

Additional bits such as a digital service channel (hereinafter referred to as DSC) signal are inserted, scrambled with a scrambling pattern synchronized with the constituent frames, and converted into a data signal D6. Data signal D6 is transmitted on one of the working lines and input to FSYNC16-1. FSYNC1
6-1 detects a frame synchronization bit in the data signal D6, performs frame synchronization, and generates a frame pulse. In this case, the frame pulse and data signal D6 are
Input to R,XDPU19-1 via 8YNC8W18-1. The R,XDPU 19-1 converts the data signal D6 into the data signal D1 using the input frame pulse. That is, the inverse conversion of the conversion in the TXDPU 14-1 is performed. In this case, this data signal DI is outputted to the receiving carrier terminal station via the switch 13. Other data signals input from the transmitting carrier terminal station are similarly transmitted on the respective working lines and sent to the receiving carrier terminal station.

TE8TPG2 generates a test pattern, which in this case is transmitted to TXD via switch 3.
It is input to PU14-0, is converted in the same way as the above data signal D1 is converted to data signal D6, and is converted to TX8W1.
5 as a data signal D7 on the protection line, and F
8YNet6-〇・RXDI R, XD via 8T17
It is input to the PU l9-〇 and converted into a test pattern again, and this test pattern is sent to the TES via the switch 13.
It is input to the TPD 12 and used for monitoring the protection line.

Next, the operation of the conventional example shown in FIG. 2 will be described in the case where one of the working lines is synchronously switched to a protection line due to line quality deterioration due to line maintenance, fading, etc.

For example, assume that the line quality of the working line that transmits the data signal D6 has deteriorated. FSYNC16-1 is data signal D
The line quality of this working line is monitored by detecting the parity check pit in 6.

When the FSYNC 16-1 detects deterioration in line quality, the line switching control device (not shown) controls the TXSW 15 to switch the output to the protection line to the output of the TXDPU 14-1 (i.e., the transmission (parallel ends). however,
Since the protection line needs to transmit its own ID code and DEC signal, the If) code and DEC signal in the data signal D6 input from the TXDPU14-1 is set to 'L'.
Rewrite to the same ones inserted in XDPU14-O.

In this way, the TXSW 15 requires an additional bit rewriting function. Due to this parallel transmission end, the data signal D7 output to the protection line becomes the same as the data signal D6 except for the code/jJSC signal portion.

Since the NAO and 'L'XDPUs 14-0-14-1 operate asynchronously with each other, this switching also changes the clock of the data signal D7. If the clock changes discontinuously, the modulator (not shown) of the protection line may become out of synchronization, and recovery may take a long time. Therefore, the TXSW 15 has a phase-locked loop that synchronizes with the clock of the input data signal, and uses the output of this phase-locked loop to retime the input data signal and output it. The input data signal is transferred from the TXDPU14-00 output to the TXDPU14-
Even when switching to the output of 1, the output phase of the phase-locked loop changes continuously with the time constant of the loop filter, so the clock of data signal D7 also changes continuously, preventing the loss of synchronization of the modulator of the protection line. It can be prevented.

By paralleling the sending end with TX8W15, FSYNC16
The frame of data signal D7 input to -0 is TXDP
TXDPU14-1 from the frame configured by U14-0
As a result, the frame synchronization of F8YNC16-0 is lost, and recovery thereof requires (on average) a time approximately proportional to the length of these frames. F8YNC1
Once frame synchronization of F8YNC16-0 is reestablished, the line switching controller controls RXDIST17 to
Frame pulse and data signals output by 1) 7 to 8
Output to YNC8W18-1.

Data signals D6 and D7 input to 5YNC8W18-1
The timings do not match due to the propagation delay difference between the working line and the protection line. The fixed component of the propagation delay difference is 5Y
Compensate in advance with NC8WI 8-1. 8YN
C8W18-1 uses two frame pulses corresponding to data signals D6 and D7, respectively, and outputs data signals from data signal D6 to data signal D71.
1C.

Switching can be performed at the timing when the data signals D6 and D7 match, thereby compensating for the fluctuation component of the propagation delay difference, and switching the working line to the protection line without code errors. The data signal D7 switched and outputted by the 5YNC8W18-1 is converted into the data signal D1 by the RXDPU19-1. A specific example of the structure of such 5YNC8W is described in detail in, for example, Japanese Patent Laid-Open No. 143850/1983.

Synchronous switching from other working lines to reserve lines is also performed in the same manner as in the above case.

If the line is momentarily disconnected due to equipment failure or the like, synchronous switching is not possible, so the switching devices 3 and 13 are used to switch the line. For example, input the ≠-ta signal DI to the TXDPU14-〇 via the HYBI-1 switch 3,
By outputting the output of 9-0 to the receiving carrier terminal station via the switch 13, the working line for transmitting the data signal L)1 is switched to the protection line.

[Problem to be Solved by the Invention 3] As explained above, in the conventional line switching device, when the sending end is paralleled in the TXSW, the frame synchronization in the FSYNC corresponding to the protection line is lost, and it takes time to re-establish it. However, the average value of this time is proportional to the length of the frame constituted by the TXDPU, and the frame length increases with the repetition period of the scramble pattern, so in order to increase the randomization of the scrambled data signal, the repetition period is long. The disadvantage of using a scramble pattern is that the line switching time becomes longer.

When a line uses a multilevel modulation method, it is desirable that the modulation signal pattern be long and that the correlation between each data string making up the modulation signal be small, so it is required to use a scrambling pattern with a long repetition period. In this case, the above drawback becomes a particularly big problem. For example, if the scramble pattern generation circuit is equivalent to 23 stages of PN, the repetition period is 8.4X10', and even for 15 stages of PN, the repetition period is 3.2X10'.
It becomes long.

SUMMARY OF THE INVENTION An object of the present invention is to provide a line switching device capable of solving the above drawbacks and increasing the randomization of scrambled data signals without increasing the line switching time.
be.

[Failure to solve the problem]

The line switching device of the present invention converts the speed of the first data signal into 1. A frame is constructed and sent to the working line, and is also sent in parallel to the standby protection line if necessary, and by establishing frame synchronization on reception on each of the working line and protection line, these received outputs are synchronized. In a line switching device that switches a line in synchronization with a signal without code error), a first additional bit including at least a first frame synchronization bit is inserted into the first data signal to form a first frame. , a first transmission signal processing circuit that scrambles with a first scrambling pattern synchronized with the first frame of a first repetition period and outputs it as a second data signal, and at least a second frame synchronization bit. A second additional bit is inserted into the second data signal to form a second frame, and a second data signal is synchronized with the second frame and has a second repetition period different from the first data signal. a second transmission signal processing circuit for scrambling with a scramble pattern and sending it to the working line as a third data signal; and inserting a third additional bit including at least the second frame synchronization bit into the fourth data signal. a third transmission signal processing circuit that configures the second frame, scrambles it with the second scramble pattern, and sends it to the protection line as a fifth data signal; and a transmission switching circuit that outputs the fourth data signal to the third transmission signal processing circuit.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a diagram showing an embodiment of the line switching device of the present invention.

The embodiment shown in FIG. 1 is used in a digital wireless communication system consisting of a working line and one protection line, similar to the conventional example shown in FIG. -to-TE8TPG2/switcher 3,
A first transmission signal processing circuit (hereinafter referred to as TXIDPU) 4-O that inputs the output of the switch 3, and a TXIDPU that inputs one of the two-branch outputs of each of HYBI-1 to 1-.
4-1 to 4-, TX8Ws inputs the output of TXIDPU4-0 and one of the two outputs of TXIDPU4-1 to 4- to output data signal D4, and TX8Ws inputs to data signal D4 and outputs data signal D5. A second transmission signal processing circuit (hereinafter referred to as TX2DPU) 6 that outputs the signal to the protection line
-O and the other of the two outputs of each of the TXIDPUs 4-1 to 4- are input to the TX2DPUs 6-1 to 6-, which output data signals to the corresponding working lines, and the respective outputs of the protection line and working line. to the second receiving signal processing circuit (hereinafter referred to as RX2DPU) 7-0 to 7-, which inputs
The first frame synchronization circuit (hereinafter referred to as F18YNC) 8-0 to B- inputs the output to the X2DPU7-0 to 7-
RXDIST9 branches the output of F18YNC8-0 to (k+X), and 5 inputs one of the branched outputs of RXDIST9 and the output to F18YNC8-1 to F18YNC8-8.
YNC8W10-1~10- and RXD I8T
9. First reception signal processing circuit (hereinafter referred to as XIDPU) 11 which inputs the output of syNcswiO-1 to 10-
-0 to 11-, the same TESTPD as in Fig. 2
12 and a switch 13. The outputs of RXIDPU II-〇 to 11- are input to the switch 13.

First, the operation of the embodiment shown in FIG. 1 will be described for the case where all lines are normal and the protection line is on standby.

One of the data signals from the transmitting carrier terminal station, for example, the data signal D1, is input to the TXIDPU 4-1 via the HYBI-1. The TXIDPU 4-1 converts the data signal D1 from bipolar to unipolar, performs speed conversion, inserts additional bits to form a first frame, scrambles it with a first scrambling pattern, and converts it into a data signal D2.

The repetition period of the first scramble pattern is set to 1, for example.
Keep it relatively short, 000 bits. As a result, the length of the first frame can also be made relatively short.

The TX2DPU 6-1 speed-converts the data signal 1)2, inserts additional bits to form a second frame, scrambles it with a second scrambling pattern, and converts it into a data signal D3. The repetition period of the second scramble pattern is set to a length different from that of the first scramble pattern, for example, 995 bits. Since the data signal D3 is scrambled in two stages using the first and second scrambling patterns, it is scrambled with a long repetition period of 199,000 bits, which is the least common multiple of the respective repetition periods of these scramble patterns.・Even though the repetition period of the second scramble pattern is relatively short, the data signal D
3 is highly randomized. The repetition periods of the first and second scrambling patterns are each set to be relatively short, and the least common multiple thereof is set to be as large as necessary.

Data signal D3 is transmitted on one of the working lines to RX2D
Input to PU7-1. The RX2DPU 7-1 converts the data signal D3 into the data signal D2 in frame synchronization with the second frame (comprised of the TX2DPU 6-1) of the data signal D3. FlsYNc8-1 is the data signal D2
A frame pulse is generated in synchronization with the first frame, that is, the first frame. This frame pulse and data signal D2 is input to RXID PUI 1-1 via 8YNC8W10-1 in this case. RXIDPUII
-1 converts the data signal D2 into the data signal D1 using the input frame nox.

In this case, this data signal D1 is outputted to the receiving carrier terminal station via the switch 13. Other data signals input from the transmitting carrier terminal station are similarly transmitted on the respective working lines and sent to the receiving carrier terminal station.

In this case, the test pattern generated by TE8TPG2 is switch 3, TX I DPU 4-0, TXSWs,
TX2DPU6-0/protection line/RX2DPU7-0-
F18YNC8-0・RXD I 8T9・RXIDP
TESTPD1 through the path of UII-0/switcher 13
Enter 2.

Next, the operation of the embodiment shown in FIG. 1 will be described in the case where, for example, a working line transmitting the data signal D3 is synchronously switched to a protection line due to line quality deterioration due to line maintenance or fading.

In this case, under the control of a line switching control device (not shown), the TXSWs switch the data signal D4 from the output of the TXIDPU 4-0, which had been output until then, to the output of the TXIDPU 4-1. As a result, 'rX2DPU6-0・6-
1 is the data signal D5/D output to the protection line/working line
3 are the same except for the additional bits inserted in the TX2DPU 5-Q and 6-1 and the difference in the scrambling caused by the second scrambling pattern. Therefore, the TXSWs are arranged in parallel at the sending end. TX2DPU
6-0 and 6-1 configure the input data signals into the same second frame and scramble them with the same second scrambling pattern, but since they operate asynchronously, the frame phase of the second frame is data signal D5
and the data signal D3 do not necessarily match, and therefore the pattern phases of the second scramble pattern also do not necessarily match. The ID code and DSC signal unique to the protection line is T.
Insert with X2DPU6-0. Jin and Kyoshi, TX8
W5Vc cannot have the additional bit rewriting function. Also, T
X21) PU6-0 originally has a buffer function for manually input data signals for speed conversion, and even if the clock of the input data signal D4 changes discontinuously due to the sending end parallel operation of 9,'rxsws. Since the clock of the output data signal D5 does not change suddenly, the TX8W5 has a clock that prevents the clock of the output data signal D5 from changing suddenly.
There is no need for a switch function and a switch function for selecting and outputting one of the input data signals.

Since the second frame of the data signal D5 input to the RX2DPU7-O does not change due to the sending end parallelism in the TXSW5, the frame synchronization in the RX2DPU7-o is not affected either, and the data signal D4 is changed from the data signal D5 by the RX2DPU7-0. The conversion to is also not interrupted by sending-end parallelism. The first frame with which FIS YNC8-0 is frame synchronized changes from one composed of 9 TXIDPU4-0 to one composed of TXIDPU4-1 due to sending end parallelism, so at this time the frame synchronization of F18YNC8-0 is lost and the Recovery requires an average time approximately proportional to the length of the first frame, during which the synchronization switching operation is interrupted. As mentioned above, since the length of the first frame is relatively short, this interruption time is also short. Once p18YNc8-0 frame synchronization is reestablished, the line switching controller
In the conventional example shown in Fig. 2, RXDI8T17/5YNC8WI
Similarly to 8-1, the data signal output from 8YNC8W10-1 is switched from data signal D2 to data signal D4 without any code error. The output data signal D4 is converted into the data signal D1 by the converter XIDPUII-1.

Synchronous switching from other working lines to protection lines is also performed in the same manner as in the above case.

The switching of the line using the switching devices 3 and 13 when the line is disconnected due to equipment failure, etc. is the same as in the conventional example shown in FIG.

Note that the parity check bit inserted into the data signal is inserted into TXIDPU4-0 to 4-, and the TX2D
It also has the effect that it can be used as a section check bit and the other as a hop check bit.

〔Effect of the invention〕

As explained in detail above, the line switching device of the present invention stacks frames in two stages using a first transmission signal processing circuit and a second or third transmission signal processing circuit, and has a different repetition period in each stage. Since each data signal is scrambled using a scramble pattern, the randomization of the data signal can be increased without increasing the frame length of each stage.
Moreover, when the transmitting end is paralleled for synchronization switching, the time during which the line switching operation is interrupted until the receiving end loses frame synchronization and recovers can be shortened by shortening the frame length of the previous stage.
This has the effect of increasing the randomization of scrambled data signals without increasing the line switching time). This has the advantage of being economical because the clock buffer function and additional bit rewriting function of the transmission switching circuit required in the line switching device can be omitted.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing an embodiment of a line switching device of the present invention, and FIG. 2 is a block diagram showing an example of a conventional line switching device. 4-0~4-k...TXIDPUls...
...TXSW, 6-0~6-k...-TX2DP
U, 7-0~7-k---RX2DPU, 8-0~
8- to --- FISYNC, 9...R, XD
IST, 10-1~10-k...8YNC8W
, 11-0-11-k...RXIDPUo 3/3: #77 trash

Claims (1)

[Claims] The speed of the first data signal is converted, a frame is constructed, and the frame is sent to the working line, and if necessary, it is also sent in parallel to the standby protection line, and each of the working line and the protection line is In a line switching device that synchronizes these reception outputs with each other by establishing frame synchronization upon reception and switches lines without code errors, a first additional bit including at least a first frame synchronization bit is set to the first additional bit. A first transmission that is inserted into a data signal to form a first frame, is scrambled with a first scrambling pattern synchronized with the first frame of a first repetition period, and is output as a second data signal. a signal processing circuit; inserting second additional bits, including at least a second frame synchronization bit, into the second data signal to form a second frame; a second transmission signal processing circuit for scrambling with a second scrambling pattern having a second repetition period different from the repetition period of the data signal, and transmitting the scrambled signal to the working line as a third data signal; and at least the second frame synchronization bit. a third additional bit containing the data signal is inserted into the fourth data signal to form the second frame, and the third additional bit is scrambled with the second scrambling pattern and sent to the protection line as a fifth data signal. A line switching device comprising: a transmission signal processing circuit; and a transmission switching circuit that outputs the second data signal as the fourth data signal to the third transmission signal processing circuit.