JPH0685515B2 - Line switching method - Google Patents

Description

The present invention relates to a line switching system, and more particularly to a line switching system for switching lines between a working line and a protection line in a digital wireless communication system without code error.

[Conventional technology]

A large-capacity wireless communication system is usually provided with a protection line in addition to the working line in case of line disconnection due to line maintenance, fading, equipment failure, or the like.

In a digital wireless communication system, if there is a propagation delay difference between the working and protection lines that are switched, the output signals of both circuits may be out of synchronization and a code error may occur during line switching. A line switching method is often used in which line output signals are synchronized and line switching is performed without code errors.

FIG. 2 is a block diagram showing a first example of such a conventional line switching system.

The conventional example shown in FIG. 2 is a digital wireless communication system consisting of working lines SYS _-1 to _{k of} k (k is a natural number) lines and a protection line SP, which is transmitted from a transmitting side carrier terminal station (not shown). Each of the k data signals is branched into two, and a switch 32-1 is provided.
To k and the code converters 34-1 to 34-k to output the branching device 31
-1 to k, the pilot generator 33, and a switch 32 for selecting one of the output of the pilot generator 33 and the branch output of the branch devices 31-1 to k to output to the code conversion device 34.
-1 to k, code conversion devices 34.34-1 to k, and transmission signal processing device to which outputs of the code conversion devices 34.34-1 to k are input
35.35-1 to k and the output of the transmission signal processing devices 35-1 to 35-k are branched into two, the working lines SYS-1 to k and the transmission signal switching device 3
To the protection line SP by selecting any one of the transmission signal distribution devices 37-1 to 37-k to be output to 6 and the output of the transmission signal processing device 35 and the branch outputs of the transmission signal distribution devices 37-1 to 37-k. The transmission signal switching device 36 for outputting, the data signal from the protection line SP are branched, and the reception signal processing device 40 and the line switching devices 39-1 to 39-1.
to the received signal distribution device 38 and the working line SYS-
Received signal processing device 40-1 by selecting one of the data signals from 1 to k and the branched output of received signal distribution device 38
To line switching devices 39-1 to k, received signal processing devices 40.40-1 to 40k, and received signal processing devices 40.40-1.
Code converters 41.41-1 to k for inputting the outputs of
A switch 42-1 which outputs one of the outputs of the code conversion device 41 and the outputs of the code conversion devices 41-1 to 4k to the receiving-side carrier terminal station (not shown) and the other to the pilot detection device 43.
To k and a pilot detection device 43.

First, the operation of the conventional example shown in FIG. 2 will be described for the case where all the working lines SYS-1 to SYS-k are normally used.

In this case, the pilot signal output from the pilot generator 33 is input to the code converter 34 through the switches 32-k to 1 in sequence. The pilot signal to be transmitted on the protection line SP and the data signal to be transmitted on the working lines SYS-1 to k are code-converted from the bipolar to the unipolar by the code converters 34.34-1 to k, and the transmission signal processing device. 35 ・ 35−
The speed is converted by 1 to k, additional bits such as a frame synchronization signal and a parity check bit for wireless transmission section monitoring are inserted, and further scrambled, the transmission signal switching device 36.
The backup line SP and the working line SY are transmitted via the transmission signal distribution devices 37-1 to 37-k, and further via wireless transmission devices (not shown), respectively.
It is transmitted to the wireless section of S-1 to k.

Received signals from the wireless section of the protection line SP / working line SYS-1 to k are received signals via a wireless receiver (not shown), a received signal distributor 38, and line switching devices 39-1 to k, respectively. The data is input to the processing devices 40.40-1 to 40-k, descrambled, the additional bits are removed, the speed is converted, and the code is converted from unipolar to bipolar by the code converters 41.41-1 to k. In this case, the output signals of the code conversion devices 41-1 to k are output to the receiving side carrier terminal station via the switches 42-1 to k. The pilot signal, which is the output signal of the code conversion device 41, is input to the pilot detection device 43 through the switches 42-1 to 42-k in order and used for monitoring the protection line SP.

Next, an operation in the case of switching the line from the working line SYS-1 to the protection line SP without any code error for the purpose of deterioration of the line quality due to fading and line maintenance will be described.

A switching instruction signal (not shown) instructs switching of the line from the working line SYS-1 to the protection line SP. By this command,
The transmission signal switching device 36 selects and outputs the input signal from the transmission signal distribution device 37-1. As a result, the signal in the wireless section of the protection line SP is switched to the same signal as in the working line SYS-1 (that is, transmission switching).

The protection line SP input to the line switching device 39-1 and the signal via the reception signal distribution device 38 and the signal via the working line SYS-1 have the same information content after transmission switching, but the protection line SP The timings do not always match due to the difference in propagation delay between the working lines SYS-1. The fixed component of the propagation delay difference is compensated in advance in the line switching device 39-1. When the line switching device 39-1 is instructed to switch the line by the switching instruction signal, the timing shift (propagation) of both input signals is caused by the frame synchronization signal (inserted as an additional bit in the transmission signal processing device 35-1) or the like. The fluctuation component of the delay difference) is automatically compensated, and the output signal is switched from the signal output through the working line SYS-1 that has been output until then to the signal output through the protection line SP / received signal distribution device 38. Complete.

Line switching from the working line SYS-2 to k to the protection line SP or from the protection line SP to the working lines SYS-1 to k without any code error is performed in the same manner as above.

Working lines SYS-1 to k-for disconnection due to equipment failure
When line switching is performed between the protection lines SP, the switchers 31-1 to k and 42-1 to k corresponding to the working line to be line switched
Is used.

The operation of the conventional example shown in FIG. 2 has been described above.

The conventional example shown in FIG. 2 is a transmission switching device 36 having a complicated structure.
Since the transmission signal distribution devices 37-1 to 37-k are required, there is a drawback that the cost is high.

A line switching method that solves this drawback will be described below.

FIG. 3 is a block diagram showing a second example of the conventional line switching system.

In the conventional example shown in FIG. 3, the transmission signal switching device 36, the transmission signal distribution devices 37-1 to k, the reception signal distribution device 38, and the line switching devices 39-1 to 39k are removed from the conventional example shown in FIG. , The received signal processing device 40.40-1 to k and the code conversion device 41.41-1.
between the receiving signal distribution device 44 and the line switching device 45-1
It is configured by inserting k.

When all the working lines SYS-1 to k are normally used, the output signals of the reception signal processing devices 40 and 40-1 to k are coded through the reception signal distribution device 44 and the line switching devices 45-1 to 45k. The operation of the conventional example shown in FIG. 3 is the same as the operation of the conventional example shown in FIG.

One of the working lines, for example, working line SYS-1 is the protection line SP
When the line switching is performed without code error, the process is performed as follows.

A switching instruction signal (not shown) for instructing the line switching from the working line SYS-1 to the protection line SP is input to the switch 32-1.
The switch 32-1 switches the output signal from the pilot signal that has been output so far to the output signal of the branching device 31-1. By this transmission switching, both the input signals of the code conversion devices 34 and 34-1 become the data signal S11, and the data signals S2 and S12 which are the output signals also become the same signal. Transmit signal processor 35
Insertion of additional bits and scramble in 35-1 are usually performed asynchronously with each other, and the data signal S2
Even if S12 is the same, the output signal, that is, the signal sent to the protection line SP / working line SYS-1 is generally a completely different signal. Therefore, as in the conventional example shown in FIG. -Before 40-1, it is not possible to switch both data signals via the protection line SP / working line SYS-1. Both of these data signals are descrambled by the reception signal processing devices 40 and 40-1, the additional bits are removed, and the data signals S2 and S12 are restored. The reception signal distribution device 44 branches the data signal S2 to divide the line switching device 45-
Output to 1 to k. The data signals S2 and S12 input to the line switching device 45-1 are the same signal except for the timing difference due to the propagation delay difference. The fixed component of the propagation delay difference is compensated in advance in the line switching device 45-1.

The line switching device 45-1 divides the data signals S2 and S12 by N (N is an integer of 2 or more) by a serial-parallel conversion circuit, respectively, and forms two data signals each being a bit string of N columns.
Since the frequency division usually involves N kinds of phase uncertainties, the order of the columns of the two frequency-divided data signals does not necessarily match. That is, it is uncertain in which order of the N bit columns after division the bits of a certain time slot in the data signal before division are arranged. As described above, the two divided data signals have N uncertainties in the order of columns. These two data signals are input to the comparison circuit via the column switching circuit. When the line switching is instructed by the switching instruction signal, the comparison circuit bit-compares the two data signals. If the order of the columns of the two data signals is different, a bit comparison will be inconsistent. At this time, the comparison circuit controls the column replacement circuit corresponding to the data signal S2 to replace the columns until the order of the columns matches. Since the time slot length of the frequency-divided data signal is N times as long as the time slot length of the data signal before frequency division, the fluctuation component of the propagation delay difference can be absorbed and such bit comparison can be performed.
The two data signals whose column order is the same are
The data signal obtained by dividing the data signal S12 up to that point is switched to the data signal obtained by dividing the data signal S2 at the timing when both bits match. The data signal of the Nth column which is the output of the switching circuit is 1 from the Nth column by the parallel-serial conversion circuit.
It is converted into a column and becomes the data signal S15. The data signal S15 is
It is equal to the data signal S12 before the switching circuit is switched and equal to the data signal S2 after the switching. As described above, since the line switching device 45-1 absorbs the fluctuation component of the propagation delay difference by dividing the data signals S2 and S12 and lengthening the time slot length, the data signal S12 to the data signal S2 are absorbed. The line can be switched without code error. The data signal S15 is code-converted by the code conversion device 41-1 to become the data signal S11.

As described above, in the conventional example shown in FIG. 3, the section in which the speed is converted for inserting the additional bit for monitoring the wireless transmission section, that is, the transmission signal processing devices 35.35-1 to 35-k to the reception signal processing device 40. Since the line is switched at a stage after the section from 40-1 to k, unlike the conventional example shown in FIG. 2, the transmission signal switching device 36 and the transmission signal distribution devices 37-1 to 37-k are not required, which is economical. Is. However, the line switching devices 45-1 to 45-k require two column switching circuits and a comparison circuit because of the uncertainties in the order of columns that occur when dividing two input data signals. Is complicated, and when the data signal from the transmitting end terminal is lightly loaded and there is almost no bit change component, there is almost no AC component of both data signals that are bit-compared by the comparison circuit. It is difficult for the comparison circuit to determine whether the order of the columns of the two data signals is the same or not, and there is a drawback that there is a risk of malfunction due to the determination of a match at the pseudo coincidence point.

[Problems to be solved by the invention]

As described above, the conventional line switching method capable of line switching without code error has a complicated transmission signal switching configuration when line switching is performed within a section where speed conversion is performed for inserting additional bits for wireless transmission section monitoring. There is a disadvantage that it requires a device / transmission signal distribution device and becomes expensive, and when switching lines at a stage after the section where the speed is being converted, there is a risk of malfunction when the data signal to be transmitted is lightly loaded. There is a drawback that the configuration of the line switching device becomes complicated.

An object of the present invention is to solve the above-mentioned drawbacks and to perform line switching without code error at a stage after the section where the speed conversion is performed, the configuration of the line switching device is simple, and the data signal to be transmitted has a light load. It is to provide a line switching method that does not malfunction even in the case of.

[Means for Solving the Problems] The line switching system of the present invention includes a working line and a protection line for wirelessly transmitting one first data signal including a frame synchronization bit from a transmitting carrier terminal. In the line switching system in which two second data signals, which are reception outputs, are switched by the line switching device without any code error after the period in which the speed conversion is performed for inserting the additional bit for wireless transmission section monitoring, The line and the protection line respectively include frame synchronization means for detecting the frame synchronization bit included in the second data signal and outputting a frame pulse, and the line switching device outputs each of the second data signals. , Two serial signals which are divided into third data signals by using the frame pulse output from the corresponding frame synchronization means as a phase reference for frequency division Parallel conversion means and switching means for switching from one of the two third data signals to the other at the timing at which the respective bits match, the repetition cycle of the frame synchronization pulse being the clock cycle of the third data signal Is set to an integral multiple of.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 is a block diagram showing an embodiment of the line switching system of the present invention.

In the embodiment shown in FIG. 1, frame synchronizing devices 46.46-1 to k are added to the conventional example shown in FIG.
.About.k are replaced by line switching devices 47-1.about.k.

The data signal from the transmitting carrier terminal has a frame structure and includes a frame synchronization bit. The frame synchronizer 46-1 uses the data signal S11 from the transmission-side carrier terminal station.
This frame synchronization bit included in the above is detected from the data signal S12 which is the output of the reception signal processing device 40-1, and the frame pulse F1 is generated. Frame synchronizer 46-2 to k
Similarly, the frame synchronizing bit is detected from the output data signals of the reception signal processing devices 40-2 to 40-k to generate a frame pulse. The frame pulses generated by the frame synchronizers 46-1 to k are input to the line switching devices 47-1 to k.

When the transmission is switched by the switchers 32-1 to k, the data signal S2 which is the output of the reception signal processing device 40 is different from any of the output data signals of the reception signal processing devices 40-1 to 40k. However, the frame synchronizer 46 also generates the frame pulse F in this case because the frame sync bits included in the data signal from the transmitting carrier terminal are equal to each other. Frame pulse F is a line switching device
It is input to 47-1 to k.

When all of the working lines SYS-1 to k are normally used, the line switching devices 47-1 to 47-k are connected to the reception signal processing device 40-1.
The output data signals of ~ k are directly converted to the code converters 41-1 to 41-1.
Output to k.

One of the working lines, for example, working line SYS-1 to protection line S
When switching the line to P without code error, first switch 32−
The transmission is switched by 1. As a result, the line switching device 47-
The two data signals S12 and S2 input to 1 become the same,
The frame pulse F generated from the data signal S2 is also input. In this case, the line switching device 47-1 switches the output data signal S15 from the previously selected data signal S12 to the data signal S2.

FIG. 4 (a) is a block diagram showing the line switching device 47-1,
FIG. 4B is a waveform diagram for explaining the operation.

The line switching device 47-1 is a serial-parallel conversion circuit 1 that inputs a data signal S2 / frame pulse F and outputs a data signal S3.
And the serial-parallel conversion circuit 11 that inputs the data signal S12 / frame pulse F1 and outputs the data signal S13, and the data signal S
The switching circuit 2 receives the 3 · S13 and the switching instruction signal CS and outputs the data signal S14, and the parallel-serial conversion circuit 3 receives the data signal S14 and outputs the data signal S15.

One frame of the data signal S11 from the transmitting end terminal is 100
If it is composed of bits, the data signal S12 has the structure shown in FIG. 4 (b). The time slots marked P in the figure are the time slots occupied by the frame synchronization bits, and the time slots marked 2 to 100 are the 2nd to 100th time slots in one frame.
The frame pulse F1 is a pulse generated in the time slot marked P of the data signal S12.

The serial-parallel conversion circuit 11 divides the clock signal CL12, which is the clock of the data signal S12, into four by using the frame pulse F1 as a phase reference for frequency division, and produces a clock signal CL13 shown in FIG. 4 (b). The cycle of the clock signal CL13 is the clock signal
Since it is four times as long as the cycle of CL12, the repetition cycle of the frame pulse F1 (the repetition cycle of the frame synchronization bit of the data signal S11) is the cycle of the clock signal CL13 (this cycle is the clock cycle of the data signal S13 described below). It will be 25 times. In this way, the repetition cycle of the frame pulse F1 is set to be an integral multiple of the cycle of the clock signal CL13. With this setting, the frame pulse F1 can be used as a phase reference for frequency division. If there is no phase reference in the frequency division, the time slot that can be formed by the clock signal CL13 is 4 consecutive time slots of the data signal S12, for example, P.2.
・ It is uncertain which time slot to start with 4, but since there is a phase reference in this frequency division, the time slot that can be made up of the clock signal CL13 is the data signal S1.
It is possible to start from the time slot marked P of 2, that is, the time slot in which the frame pulse F1 is present.

The serial-parallel conversion circuit 11 divides the data signal S12 by 4 based on the clock signal CL13 to obtain a data signal D13 composed of four bit strings D1 to D4. In this division, the data signal S1 corresponding to one time slot of the clock signal CL13
2 4 time slots, for example, each bit of the time slot marked P ・ 2 ・ 3 ・ 4 sequentially from the beginning bit sequence D1
Place them in the same time slot from ~ D4. By dividing the frequency of the data signal S12 in this way, the bit strings D1 to D4 of the data signal S13 are uniquely determined (for example, the frame synchronization bit, that is, the bit of the time slot marked P is always arranged in the bit string D1). ), There is no uncertainty in the order of the columns.

When the working line SYS-1 is normally used, the switching circuit 2 detects this from the switching instruction signal CS, selects the data signal S13 and outputs it as the data signal S14. The parallel-serial conversion circuit 3 converts the data signal S14 of four columns into one column and outputs it as a data signal S15. In this case, the data signal S15
Indicates that the data signal S12 has been restored, and in the end, the line switching device 47-1 outputs the data signal S12 as it is.

Switching circuit SP from the current circuit SYS-1 by switching instruction signal CP
When the line switching is instructed, the frame pulse F is input, and the serial / parallel conversion circuit 1 similarly divides the data signal S2 into four by using the frame pulse F as a phase reference to form a data signal S3. The data signal S3 is the same signal as the data signal S13 except for the timing difference. The fixed component of the timing difference due to the fixed component of the propagation delay difference between the working line SYS-1 and the protection line SP is compensated in advance. In this case, the switching circuit 2 switches the data signal S14 from the data signal S13 that has been selected and output until then to the data signal S3 at the timing when each bit of the data signal S3 matches each bit of the data signal S13. By this switching, the data signal S15 becomes the data signal S2 restored. The time slot length of the data signals S3 and S13 is four times as long as the time slot length of the data signals S2 and S12, and the fluctuation component of the timing difference due to the fluctuation component of the propagation delay difference can be absorbed.
There is a timing in which the respective bits coincide with each other, and therefore, no code error occurs when the switching circuit 2 switches.

The line switching device 47-1 divides the data signals S2 and S12 by four to divide the time slot length of the data signals S3 and S13 into the data signal S.
The fluctuation component of the propagation delay difference between the working line SYS-1 and the protection line SP is absorbed by making the time slot length of 2 · S12 four times, but the order of frequency division is adjusted according to the length of this fluctuation component. May be increased or decreased to a degree other than 4.

The embodiment of the present invention has been described above in the case where the data signal input to the line switching device is a single bit string.
The present invention can also be applied to the case where the data signal input to the line switching device is a bit string of a plurality of columns.

In digital radio communication systems, it is often practiced that the receiving side detects the frame synchronization bit included in the data signal from the transmitting end terminal in order to confirm the line quality. Made ready-made IC
The frame synchronizer can be constructed at low cost.

〔The invention's effect〕

As described in detail above, the line switching system of the present invention divides the data signal to be switched at the stage after the section in which the speed is converted to insert the additional bit for monitoring the wireless transmission section and divides the time slot length. Since the line is switched to a long length without code error, there is no need for a complicated transmission signal switching device / transmission signal distribution device at a later stage of the transmission signal processing device,
Further, by detecting the frame synchronization bit included in the data signal from the transmitting-side carrier terminal station at the receiving side and using it as the phase reference for frequency division of the data signal to be switched, the sequence order of columns in the divided data signal is Since the determinism does not occur, there is no need for a column switching circuit / comparison circuit in the line switching device, which has the effect of being economical. Furthermore, the comparison circuit allows the sequence of the two data signal columns to match. -Since there is no need to judge a non-constant value, there is an effect that a malfunction does not occur even when the data signal to be transmitted has a light load.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a line switching system of the present invention, FIGS. 2 and 3 are block diagrams showing first and second examples of a conventional line switching system, and FIG. (A) is a block diagram showing the line switching device in FIG. 1, and FIG. 4 (b) is a waveform diagram for explaining the operation of the line switching device shown in FIG. 4 (a). 1 ・ 11 …… Series-parallel conversion circuit, 2 …… Switching circuit, 46 ・ 46
-1 to k ... Frame synchronization device, 47-1 to k ... Line switching device.

Claims (1)

[Claims] 1. A speed for inserting an additional bit for monitoring a wireless transmission section of a working line and a protection line for wirelessly transmitting one first data signal including a frame synchronization bit from a transmitting side carrier terminal. After the section being converted, in a line switching system in which two second data signals that are reception outputs are switched by a line switching device without code error, the working line and the protection line are converted into the second data signal. Each of the second data signals includes a frame synchronization unit that outputs a frame pulse by detecting the frame synchronization bit including the frame pulse output by the corresponding frame synchronization unit. Is used as a phase reference for frequency division, and two serial-to-parallel conversion means that divide the frequency into a third data signal and two third data signals are used. And a switching means for switching from one to the other at the timing when the respective bits match, and the line switching is characterized in that the repetition cycle of the frame synchronization pulse is set to an integral multiple of the clock cycle of the third data signal. method.