JPS6326122A - Noise squelch circuit - Google Patents

Noise squelch circuit

Info

Publication number
JPS6326122A
JPS6326122A JP17020186A JP17020186A JPS6326122A JP S6326122 A JPS6326122 A JP S6326122A JP 17020186 A JP17020186 A JP 17020186A JP 17020186 A JP17020186 A JP 17020186A JP S6326122 A JPS6326122 A JP S6326122A
Authority
JP
Japan
Prior art keywords
sample
output
noise
hold circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17020186A
Other languages
Japanese (ja)
Inventor
Katsuharu Kimura
克治 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17020186A priority Critical patent/JPS6326122A/en
Publication of JPS6326122A publication Critical patent/JPS6326122A/en
Pending legal-status Critical Current

Links

Landscapes

  • Noise Elimination (AREA)

Abstract

PURPOSE:To detect a pulse noise component with narrow width by using a detector so as to detect an output of a noise amplifier in a demodulated voice circuit of a receiver via a sample-and-hold circuit. CONSTITUTION:A demodulated voice of a receiver inputted from a demodulated voice input terminal 10 is amplified by a noise amplifier 1, the amplified noise is subject to sample-and-bold processing by a sample-and-hold circuit 2, and its sample-and-hold output is detected by a detector 3. That is, in inserting the sample-and-hold circuit 2 to the output of the noise amplifier 1, the noise is converted into a pulse train having a pulse width depending on a period T of the sample-and-hold circuit 2. In making the period T of the sample-and- hold circuit 2 constant, a sufficiently strong correlation between a mean value of an output noise level of demodulated voice and a mean value of an output level of the output of the sample-and-hold circuit is obtained after a sufficiently many number of times of sample-and-hold processings. Thus, in detecting the output of the sample-and-hold circuit 2, the noise level is detected.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、受信機に用いられるノイズスケルチ回路に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise squelch circuit used in a receiver.

〔従来の技術〕[Conventional technology]

従来、この種のノイズスケルチ回路は、受信機の復調音
声回路におけるノイズを増幅し、この増幅出力を直接検
波器により検波し出力していた。
Conventionally, this type of noise squelch circuit amplifies noise in a demodulation audio circuit of a receiver, and directly detects and outputs the amplified output using a wave detector.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のノイズスケルチ回路は、ノイズレベルが
高い場合、あるいはノイズの周波数成分が低い場合には
、安定な検波出力を得ている。しかし、復調音声のノイ
ズ波形が幅の狭いパルス状の波形であるとすると、増幅
した後に検波器で整流検波しても、もともとパルス幅が
狭いために検波出力に十分な直流レベルを得られなかっ
た。また、検波器回路として例えば半波整流器に対して
2倍の直流成分が得られる両波整流器を用いた場合には
、整流器回路の動作速度の制約からパルス状のノイズの
位相の変化点を遅れなく追従していくことは難しく、従
って検波器出力に十分な成分の直流レベルが得られない
という問題点があった。
The conventional noise squelch circuit described above obtains a stable detection output when the noise level is high or when the frequency component of the noise is low. However, if the noise waveform of demodulated audio is a narrow pulse-like waveform, even if rectified detection is performed using a detector after amplification, it will not be possible to obtain a sufficient DC level for the detection output because the pulse width is originally narrow. Ta. In addition, when using a double-wave rectifier that can obtain twice as much DC component as a half-wave rectifier as a detector circuit, for example, the point of change in the phase of pulse-like noise is delayed due to operating speed constraints of the rectifier circuit. Therefore, there was a problem that a sufficient DC level of the component could not be obtained for the detector output.

本発明の目的は、このような問題を解決し、安定な検波
出力を得ることのできるノイズスケルチ回路を提供する
ことにある。
An object of the present invention is to provide a noise squelch circuit that can solve such problems and obtain a stable detection output.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のノイズスケルチ回路は、受信機からの復調音声
出力のノイズを増幅するノイズ増幅器と、このノイズ増
幅器の出力を所定周期で保持するサンプルホールド回路
と、このサンプルホールド回路の出力を検波する検波器
とを含み構成される。
The noise squelch circuit of the present invention includes a noise amplifier that amplifies noise in the demodulated audio output from the receiver, a sample hold circuit that holds the output of the noise amplifier at a predetermined period, and a detector that detects the output of the sample hold circuit. It consists of a container.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である6本
実施例は、入力端子10から入力された受信機の復調音
声をノイズ増幅器1で増幅し、この増幅したノイズにサ
ンプルホールド回路2でサンプルホールドし、このサン
プルホールド出力を検波器3で検波している。すなわち
、第2図(a)に示すノイズ増幅器1の出力にサンプル
ホールド回路2を挿入すると、第2図(b)に示すよう
に、サンプルホールド回路2の周期Tで決まるパルス幅
のパルス列に変換することが出来る。
FIG. 1 is a block diagram showing an embodiment of the present invention.6 In this embodiment, demodulated audio from a receiver inputted from an input terminal 10 is amplified by a noise amplifier 1, and a sample-hold circuit is applied to the amplified noise. 2 performs sample and hold, and the sample and hold output is detected by a detector 3. That is, when the sample-and-hold circuit 2 is inserted into the output of the noise amplifier 1 shown in FIG. 2(a), it is converted into a pulse train with a pulse width determined by the period T of the sample-and-hold circuit 2, as shown in FIG. 2(b). You can.

このサンプルホールド回路2の周期Tを一定にすれば、
十分多くのサンプルホールド回数の後には復調音声の出
力ノイズレベルの平均値と、サンプルホールド回路出力
の出力レベルの平均値とは十分強い相関関係が得られる
。従って、サンプルホールド回路2の出力を検波すれば
ノイズレベルを検出出来る。しかも、サンプルホールド
の周期Tを整流検波器3の動作速度よりも十分大きくす
れば、両波整流器回路等を用いても良い。
If the period T of this sample and hold circuit 2 is kept constant,
After a sufficiently large number of samples and holds, a sufficiently strong correlation is obtained between the average value of the output noise level of the demodulated audio and the average value of the output level of the sample and hold circuit output. Therefore, by detecting the output of the sample and hold circuit 2, the noise level can be detected. Furthermore, if the sample-and-hold period T is made sufficiently larger than the operating speed of the rectifying detector 3, a double-wave rectifier circuit or the like may be used.

第3図は第1図の回路例としてスイッチトキャパシタ回
路を用いた場合を示す(以下SCと略す)、図において
、互いに重り合わないクロックφ1゜φ2によりキャパ
シタ01〜C5をオン、オフさせるスイッチをもち、3
段のオペアンプ21〜23とトランジスタM1と平滑用
キャパシタC6とから構成される。
Figure 3 shows a case where a switched capacitor circuit is used as an example of the circuit in Figure 1 (hereinafter abbreviated as SC). Mochi, 3
It is composed of stage operational amplifiers 21 to 23, a transistor M1, and a smoothing capacitor C6.

オペアンプ21とキャパシタC1,C2およびスイッチ
で構成されるブロックは、SC逆相増幅器であり、その
利得GはキャパシタC1と02の比で決まる(G=C1
/C2)、’。このSC逆相増幅器の出力はSC回路で
あるため、クロックφ1.φ2の周期によりサンプルホ
ールドされている。 次に、オペアンプ22.23とキ
ャパシタ03〜C5およびスイッチで構成されるブロッ
クは、SC両波整流器であり、その傾斜はそれぞれ−C
4/C1,およびC4/CIで表され、キャパシタC5
は2C3に相当する。
The block consisting of the operational amplifier 21, capacitors C1 and C2, and a switch is an SC anti-phase amplifier, and its gain G is determined by the ratio of capacitors C1 and 02 (G=C1
/C2),'. Since the output of this SC anti-phase amplifier is an SC circuit, the clock φ1. Sample and hold is performed with a period of φ2. Next, the block consisting of the operational amplifier 22, 23, capacitors 03 to C5, and switches is an SC double-wave rectifier, and its slope is −C
4/C1, and C4/CI, and the capacitor C5
corresponds to 2C3.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、受信機の復調音声回路
におけるノイズ増幅器の出力をサンプルホールド回路を
介して検波器で検波することにより、幅の狭いパルス状
のノイズ成分を検出することが出来るという効果がある
As explained above, the present invention makes it possible to detect narrow pulse-like noise components by detecting the output of the noise amplifier in the demodulation audio circuit of the receiver with a detector via a sample and hold circuit. There is an effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図(a)
、(b)は第1図の入力およびサンプルホールドの出力
を示す波形図、第3図は第1図の具体例としてSC回路
を用いた回路図である。 1・・・ノイズ増幅器、2・・・サンプルホールド回路
、3・・・検波器、10・・・入力端子、11・・・出
力端子、21〜23・・・オペアンプ。 第 1 図 手 2 図
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
, (b) are waveform diagrams showing the input and sample-and-hold outputs of FIG. 1, and FIG. 3 is a circuit diagram using an SC circuit as a specific example of FIG. 1. DESCRIPTION OF SYMBOLS 1... Noise amplifier, 2... Sample hold circuit, 3... Detector, 10... Input terminal, 11... Output terminal, 21-23... Operational amplifier. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 受信機からの復調音声出力のノイズを増幅するノイズ増
幅器と、このノイズ増幅器の出力を所定周期で保持する
サンプルホールド回路と、このサンプルホールド回路の
出力を検波する検波器とを含むノイズスケルチ回路。
A noise squelch circuit includes a noise amplifier that amplifies noise in demodulated audio output from a receiver, a sample hold circuit that holds the output of the noise amplifier at a predetermined period, and a detector that detects the output of the sample hold circuit.
JP17020186A 1986-07-18 1986-07-18 Noise squelch circuit Pending JPS6326122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17020186A JPS6326122A (en) 1986-07-18 1986-07-18 Noise squelch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17020186A JPS6326122A (en) 1986-07-18 1986-07-18 Noise squelch circuit

Publications (1)

Publication Number Publication Date
JPS6326122A true JPS6326122A (en) 1988-02-03

Family

ID=15900541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17020186A Pending JPS6326122A (en) 1986-07-18 1986-07-18 Noise squelch circuit

Country Status (1)

Country Link
JP (1) JPS6326122A (en)

Similar Documents

Publication Publication Date Title
TWI432742B (en) Rf power sensor with chopping amplifier and method for measuring rf power in connection with high frequency pulsed rf signals
JPS6238062A (en) Method and apparatus for detecting binary signal
JPH1051402A (en) Reception electric field detection circuit
JPS6326122A (en) Noise squelch circuit
JPH09184823A (en) Apparatus for processing detection signal of analyzing apparatus
US6229471B1 (en) Method for detecting a pulse-usable system
US6664816B1 (en) Signal amplitude comparator
JP2514940B2 (en) Video intermediate frequency signal processing circuit
KR200187185Y1 (en) Modem
US7592845B2 (en) Input signal level detection apparatus and method
JPH0621980A (en) Optical signal demodulating system
US6972617B2 (en) FM demodulator including a DC offset detector
JP2001102963A (en) Device and method for synchronization
US6265933B1 (en) FM demodulator
JPS61266963A (en) Rectifying circuit
JP2536579B2 (en) Two-input high-frequency signal level difference detector
JP2022026089A (en) Magnetic recording information processing method and device
JP2827581B2 (en) Digital receiver
JPH0156385B2 (en)
JPS637551A (en) Envelope output circuit
JPH1188449A (en) Ask demodulating device
JPH0528832Y2 (en)
JPH0211188B2 (en)
JPH0464213B2 (en)
JPH052450U (en) Signal meter circuit