JPH0156385B2 - - Google Patents

Info

Publication number
JPH0156385B2
JPH0156385B2 JP2788383A JP2788383A JPH0156385B2 JP H0156385 B2 JPH0156385 B2 JP H0156385B2 JP 2788383 A JP2788383 A JP 2788383A JP 2788383 A JP2788383 A JP 2788383A JP H0156385 B2 JPH0156385 B2 JP H0156385B2
Authority
JP
Japan
Prior art keywords
signal
differential
circuit
output
offset component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2788383A
Other languages
Japanese (ja)
Other versions
JPS58154671A (en
Inventor
Masao Hotsuta
Kenji Maio
Keiichi Myamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2788383A priority Critical patent/JPS58154671A/en
Publication of JPS58154671A publication Critical patent/JPS58154671A/en
Publication of JPH0156385B2 publication Critical patent/JPH0156385B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0023Measuring currents or voltages from sources with high internal resistance by means of measuring circuits with high input impedance, e.g. OP-amplifiers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Description

【発明の詳細な説明】 本発明は、大きな搬送波あるいはオフセツトに
重畳した微少な信号を取り出すための信号検出回
路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection circuit for extracting a minute signal superimposed on a large carrier wave or offset.

ある一定量からのわずかな変化を検出測定する
場合、その一定量が搬送波あるいはオフセツトで
あり、またその変化量が信号であるが、この搬送
波あるいはオフセツト(以下搬送波を含めてオフ
セツト成分と呼ぶ)を取り除くために、一般に差
動法が用いられる。これにはブリツジなど種々の
手段があるが、原理的には第1図に示すようにし
て行なわれる。
When detecting and measuring a slight change from a certain amount, that certain amount is a carrier wave or offset, and the amount of change is a signal, but this carrier wave or offset (hereinafter referred to as the offset component including the carrier wave) is To remove this, differential methods are generally used. There are various means for this, such as a bridge, but in principle it is carried out as shown in FIG.

ここで、vc1、vc2はいずれもオフセツト成分で
あり、vc1はvc2を相殺するために加えたものであ
る。なおvSはvc2に重畳された信号である。ポテ
ンシヨメータや増幅器などの利得調整器1により
オフセツト成分vc1とvc2の振幅を合致させ、差動
回路2によりその差をとると、その差出力V01
vc1とVc2の整合度α(ただし、 α=vc2−vc1/vc1< 1)とし、利得調整器1の利得をβとすると、 V01=vS+vc2−βvc1 =vS+(1+α−β)vc1 ……(1) ただし、vc2=(1+α)vc1 となる。ここで、 1+α−β=0 ……(2) となるようにβを選ぶが、βにΔβという誤差が
あると、Δβvc1なるオフセツト成分が取り切れず
残ることになる。この残留オフセツト成分の許容
値を信号vSのn1倍とすると、 Δβvc1=n1vS ……(3) となり、vS/vc1=とすれば、(2)式より Δβ/β=n1/β n1/(1+α) ……(4) を得る。したがつて、n1=1としても、利得調整
器1に必要な精度はと同程度となり、信号が搬
送波の10-5〜10-6倍のように非常に小さな場合に
は、利得調整器1にそれだけの精度を要求するの
は非常に困難である。
Here, v c1 and v c2 are both offset components, and v c1 is added to cancel v c2 . Note that v S is a signal superimposed on v c2 . When the amplitudes of offset components v c1 and v c2 are matched by a gain adjuster 1 such as a potentiometer or an amplifier, and the difference is taken by a differential circuit 2, the difference output V 01 is
Let the degree of matching between v c1 and V c2 be α (however, α = v c2 − v c1 / v c1 < 1), and let the gain of gain adjuster 1 be β, then V 01 = v S + v c2 − βv c1 = v S + (1+α-β)v c1 ...(1) However, v c2 = (1+α) v c1 . Here, β is selected so that 1+α−β=0 (2), but if there is an error of Δβ in β, an offset component of Δβv c1 will remain. If the allowable value of this residual offset component is n 1 times the signal v S , then Δβv c1 = n 1 v S ...(3), and if v S /v c1 =, then from equation (2), Δβ/β =n 1 /β n 1 /(1+α) ...(4) is obtained. Therefore, even if n 1 = 1, the accuracy required for the gain adjuster 1 is about the same as , and if the signal is very small, such as 10 -5 to 10 -6 times the carrier wave, the gain adjuster It is extremely difficult to require that much precision from 1.

そこで、第2図に示すように第1の差動回路2
aにより一度差動を取り、その差動出力と利得調
整器1により適当に利得調整されたオフセツト成
分とを第2の差動回路2bによりもう一度差動を
取る。これにより、差動出力V02は差動回路2
a,2bの利得をそれぞれAa、Abとすると、 V02=AaAb(vS+vc2−vc1)−Abβvc1 AaAb{vS+(α−β/Aa)vc1} ……(5) ただし、vc2=(1+α)vc1 となる。ここで、 α−β/Aa=0 ……(6) となるようにβが選ばれるが、βにΔβという誤
差があると、(Δβ/Aa)vc1が誤差となる。この
誤差の許容値を信号のn2倍とすると、次式とな
る。
Therefore, as shown in FIG.
A is once made differential, and the differential output and the offset component whose gain has been suitably adjusted by the gain adjuster 1 are once again made differential by the second differential circuit 2b. As a result, the differential output V 02 is the differential output V 02 of the differential circuit 2.
If the gains of a and 2b are A a and A b , respectively, then V 02 = A a A b (v S + v c2 − v c1 ) − A b βv c1 A a A b {v S + (α−β/A a ) v c1 } ...(5) However, v c2 = (1 + α) v c1 . Here, β is selected so that α−β/A a =0 (6), but if there is an error of Δβ in β, the error is (Δβ/A a )v c1 . If the allowable value of this error is set to n 2 times the signal, the following equation is obtained.

Δβvc1Aa=n2vS ……(7) これより、(6)式を考慮して Δβ/β=Aan2/β n2/α ……(8) を得る。したがつてこの場合は、出力における誤
差の許容値n2として第1図における誤差の許容値
n1と等しい値を得ようとすると、利得調整器1に
要求される精度はの1/αで良いことになる。
Δβv c1 A a = n 2 v S ...(7) From this, considering equation (6), we obtain Δβ/β=A a n 2 /β n 2 /α ...(8). Therefore, in this case, the allowable error value in Figure 1 is set as the allowable error value n 2 in the output.
To obtain a value equal to n 1 , the accuracy required for the gain adjuster 1 is 1/α.

一般に、整合度αは10-1〜10-2は容易に得られ
るから、n2=1として、=10-5〜10-6の場合で
も、利得調整器1の精度は10-3〜10-4で良く、第
1図の場合に比べて有利となる。また、第1の差
動回路2aとして差動増幅器2a′を用い、参照信
号の極性をオフセツト成分のそれと逆にすれは第
3図のような構成にでき、第2の差動回路は不用
となる。
In general, a matching degree α of 10 -1 to 10 -2 can be easily obtained, so even if n 2 = 1 and = 10 -5 to 10 -6 , the accuracy of gain adjuster 1 is 10 -3 to 10 -4 is sufficient, which is more advantageous than the case in Figure 1. Furthermore, by using the differential amplifier 2a' as the first differential circuit 2a and reversing the polarity of the reference signal to that of the offset component, the configuration can be made as shown in Fig. 3, and the second differential circuit is unnecessary. Become.

次に、本発明の具体的な実施例を述べる。第4
図において、3aは固定インピーダンス、3bは
可変インピーダンスである。またD1,D2は整流
用ダイオードで、オフセツト成分vcが直流の場合
はなくても良い。なお本実施例では、差動回路2
a,2bに差動増幅器4a,4bを用いた場合を
示す。さらに第5図は第4図における初段の差動
増幅器4aの代りに一般の増幅器5を用いたもの
である。この場合、オフセツト成分を参照信号に
より差し引くために、ダイオードD1,D2の方向
を互に逆にし、極性が逆のオフセツト成分と参照
信号とが加算される構成となる。
Next, specific examples of the present invention will be described. Fourth
In the figure, 3a is a fixed impedance, and 3b is a variable impedance. Further, D 1 and D 2 are rectifying diodes, which may be omitted if the offset component v c is direct current. Note that in this embodiment, the differential circuit 2
A case where differential amplifiers 4a and 4b are used for a and 2b is shown. Further, in FIG. 5, a general amplifier 5 is used in place of the first-stage differential amplifier 4a in FIG. In this case, in order to subtract the offset component from the reference signal, the directions of the diodes D 1 and D 2 are reversed, and the offset component and the reference signal having opposite polarities are added.

次に、第4図において利得調整器として制御可
能なもの、例えば乗算型DA変換器
(Multiplying D―A Converter;以下MDAC
と略記する)6を用いてオフセツト成分の除去を
自動化した実施例を第6図に示す。ここで、7は
比較器、8はUP/DOWNカウンタである。入力
信号がない場合、アンバランス成分が出力V0
現われると、UP/DOWNカウンタ8は比較器7
の出力レベルに従つてカウントアツプ、またはカ
ウントダウンする。これをクロツクCKに同期し
て出力V0が零になるまで繰り返し、MDAC6の
±1LSBの範囲内でバランスする。
Next, in Fig. 4, a controllable gain adjuster, such as a multiplying DA converter (hereinafter referred to as MDAC), is shown.
FIG. 6 shows an example in which the removal of the offset component is automated using 6. Here, 7 is a comparator and 8 is an UP/DOWN counter. In the absence of an input signal, if an unbalanced component appears at the output V 0 , the UP/DOWN counter 8 is activated by the comparator 7.
Counts up or down according to the output level. This is repeated in synchronization with the clock CK until the output V0 becomes zero, and the balance is maintained within the range of ±1LSB of MDAC6.

そこで、信号のないときにUP/DOWNカウン
タ8を制御信号Eによつてカウント状態から保持
状態にすれば、MDAC6の利得はそのまま保持
され、入力vc中の微小信号成分のみを検出するこ
とが可能になる。なお、第5図には第3図の差動
構成を用いたが、第5図の場合でも同様である。
Therefore, if the UP/DOWN counter 8 is changed from the counting state to the holding state by the control signal E when there is no signal, the gain of the MDAC 6 is maintained as it is, and only the minute signal component in the input v c can be detected. It becomes possible. Although the differential configuration shown in FIG. 3 is used in FIG. 5, the same applies to the case shown in FIG.

さらに、残留するオフセツト成分すなわち上述
した±1LSBが問題となる場合には、第4図ない
し第6図に示したオフセツト成分除去回路に第7
図または第8図の回路を付加すれば良い。第7図
において、9は第4図ないし第6図に示したオフ
セツト成分除去回路である。また10は増幅器
で、コンデンサ11と増幅器12とよりなる帰還
回路をスイツチ13を介して接続されている。
Furthermore, if the remaining offset component, that is, the above-mentioned ±1LSB, becomes a problem, a seventh
It is sufficient to add the circuit shown in Fig. 8 or Fig. 8. In FIG. 7, 9 is the offset component removal circuit shown in FIGS. 4 to 6. Reference numeral 10 denotes an amplifier, which is connected to a feedback circuit consisting of a capacitor 11 and an amplifier 12 via a switch 13.

この場合、信号の有無を適当な手段で検知でき
るようにし、無信号時にスイツチ13をONとす
ると直流帰還がかかり、出力は零となる。信号測
定時にはスイツチ13をOFFとすれば直流レベ
ルは保持され、オフセツト成分を零として微小信
号を検出することできる。なお増幅器10の代り
に第4図または第5図の差動増幅器4bを用いる
ことも可能である。また、信号が直流成分を含ま
ない場合には、第8図に示すように、オフセツト
除去回路9からコンデンサ14を介して増幅器1
0に接続し、スイツチ13を増幅器10の入力端
子とアースとの間に設けた構成とすることもでき
る。
In this case, the presence or absence of a signal can be detected by an appropriate means, and when the switch 13 is turned on when there is no signal, DC feedback is applied and the output becomes zero. When the switch 13 is turned off during signal measurement, the DC level is maintained, and a minute signal can be detected with the offset component set to zero. Note that it is also possible to use the differential amplifier 4b of FIG. 4 or 5 in place of the amplifier 10. In addition, when the signal does not include a DC component, as shown in FIG.
0, and the switch 13 may be provided between the input terminal of the amplifier 10 and ground.

以上のような回路構成を用いることによりオフ
セツト成分を除去し、オフセツト成分に対して
10-5〜10-7という微小な信号を検出することが可
能となる。
By using the above circuit configuration, the offset component can be removed and
It becomes possible to detect signals as small as 10 -5 to 10 -7 .

さらに、第6図の実施例において、差動回路2
bの入力に、差動回路2aの出力の代りに一定の
参照信号VREFを入れることにより、自動利得調整
回路としても使用できる。その実施例を第9図に
示す。ここで、整流用ダイオードDおよびローパ
スフイルタ15は、信号vSが直流の場合は無くて
も良い。また、MDAC6に入力側と差動回路2
bのVREF入力側とにそれぞれ増幅器を接続すれ
ば、両者の増幅度を同一にすることも可能であ
る。この場合、差動回路2bの代りに比較器7を
直接接続しても良い。
Furthermore, in the embodiment of FIG. 6, the differential circuit 2
By inputting a constant reference signal V REF instead of the output of the differential circuit 2a to the input of the differential circuit 2a, it can also be used as an automatic gain adjustment circuit. An example thereof is shown in FIG. Here, the rectifying diode D and the low-pass filter 15 may be omitted if the signal v S is a direct current. In addition, the input side and differential circuit 2 are connected to MDAC6.
If an amplifier is connected to the V REF input side of b, it is also possible to make the amplification degree of both the same. In this case, the comparator 7 may be directly connected instead of the differential circuit 2b.

以上説明したように、本発明によるときは微小
信号の重畳されたオフセツト成分と第1の参照信
号との差動をとり、さらに差動出力と第2の参照
信号との差動をとることによつて、微小信号をき
わめて高精度で検出することができ、その効果は
大きいものである。
As explained above, according to the present invention, the difference between the offset component on which the minute signal is superimposed and the first reference signal is taken, and the difference between the differential output and the second reference signal is taken. Therefore, minute signals can be detected with extremely high precision, and the effect is great.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はオフセツト成分に重畳された微小信号
を検出する従来の回路例を示すブロツク図、第2
図ないし第9図は本発明の各実施例を示すブロツ
ク図である。 1……利得調整器、2,2a,2b……差動回
路、4a,4b……差動増幅器。
Figure 1 is a block diagram showing an example of a conventional circuit for detecting a minute signal superimposed on an offset component;
9 through 9 are block diagrams showing each embodiment of the present invention. 1... Gain adjuster, 2, 2a, 2b... Differential circuit, 4a, 4b... Differential amplifier.

Claims (1)

【特許請求の範囲】[Claims] 1 微小信号を重畳された入力信号と参照信号と
を加えられた第1の差動回路と、上記参照信号を
加えられた利得調整回路と、該利得調整回路出力
と上記第1の差動回路出力とを加えられる第2の
差動回路とを具備することを特徴とする信号検出
回路。
1. A first differential circuit to which an input signal superimposed with a minute signal and a reference signal are added, a gain adjustment circuit to which the reference signal is added, the output of the gain adjustment circuit and the first differential circuit. and a second differential circuit to which an output is applied.
JP2788383A 1983-02-22 1983-02-22 Detecting circuit of signal Granted JPS58154671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2788383A JPS58154671A (en) 1983-02-22 1983-02-22 Detecting circuit of signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2788383A JPS58154671A (en) 1983-02-22 1983-02-22 Detecting circuit of signal

Publications (2)

Publication Number Publication Date
JPS58154671A JPS58154671A (en) 1983-09-14
JPH0156385B2 true JPH0156385B2 (en) 1989-11-29

Family

ID=12233288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2788383A Granted JPS58154671A (en) 1983-02-22 1983-02-22 Detecting circuit of signal

Country Status (1)

Country Link
JP (1) JPS58154671A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078179A (en) * 1997-04-24 2000-06-20 Dkl International, Inc. Selective polarization matching filter for triggering and maximizing rapid dielectrokinesis response
US6011476A (en) * 1996-11-27 2000-01-04 Dkl International, Inc. Metering circuit to detect dielectrokinetic response
US5748088A (en) 1996-11-27 1998-05-05 Afilani; Thomas L. Device and method using dielectrokinesis to locate entities

Also Published As

Publication number Publication date
JPS58154671A (en) 1983-09-14

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