JPS6165113A - Sensor circuit with zero point compensation - Google Patents
Sensor circuit with zero point compensationInfo
- Publication number
- JPS6165113A JPS6165113A JP59187050A JP18705084A JPS6165113A JP S6165113 A JPS6165113 A JP S6165113A JP 59187050 A JP59187050 A JP 59187050A JP 18705084 A JP18705084 A JP 18705084A JP S6165113 A JPS6165113 A JP S6165113A
- Authority
- JP
- Japan
- Prior art keywords
- output
- zero point
- circuit
- signal
- point correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、零点補正機能を持ったセンナ回路に関する。[Detailed description of the invention] Industrial applications The present invention relates to a senna circuit having a zero point correction function.
従来の技術
一般に、測定・制御には光電、変位、速度など様々なか
免ちの検出対象の物理iを電気信号に変換する種々のセ
ンナが使用される。このセンサの主要部になる変換器は
、一般的に物理的変位(例えば光量や角度の変化>t−
電気的な変位(例えば電流値や抵抗値の変化)K変換す
る検出端と、この検出端に得る電気的変位を信号処理可
能なレベルまで増幅するプリアンプとで構成される。第
2図(A)は光センサ変換器をその零点補正回路と共に
示し、検出端としてのフォトダイオードpシで入力光量
に比例し之′rL流(DOQ〜1m7k)全得、この電
流をプリアンプPAで電圧信号(θ〜10v)に変換増
幅する。第2図(B)は角度センサ変排Bを示し、ポテ
ンショメータPMを角度検出端として分圧電圧として取
出し、この電圧を電圧ホロワVFでインピーダンス変換
する。2. Description of the Related Art In general, various sensors are used for measurement and control, which convert physical signals of various detection targets such as photoelectric, displacement, and velocity signals into electrical signals. The transducer, which is the main part of this sensor, generally responds to physical displacement (for example, changes in light intensity or angle > t-
It is comprised of a detection end that performs K conversion of electrical displacement (for example, changes in current value or resistance value), and a preamplifier that amplifies the electrical displacement obtained at this detection end to a level that allows signal processing. Fig. 2 (A) shows the optical sensor converter together with its zero point correction circuit.The photodiode p serves as the detection end, and the current is proportional to the input light amount (DOQ~1m7k), and this current is transferred to the preamplifier PA. It is converted and amplified into a voltage signal (θ~10v). FIG. 2(B) shows an angle sensor variable/discharge B, in which a potentiometer PM is used as an angle detection end to extract a divided voltage, and this voltage is impedance-converted by a voltage follower VF.
これらセンサ変換器では、特に検出端にはそれが配置さ
れる環境(温度、湿度等)の変化や検出端自体の経年変
化などで零点の変化、いわゆる零ドリフトが少なからず
存在する。この零ドリフト補償には第2図(A)に示す
ように、町7S抵抗器VFと電隋変ぐ用抵抗器R,によ
るゼロ調整回路を設け、補正時に入力光量ヲ零にして可
変抵抗器VFIを訓堅して出力電圧voが零にするもの
がある。In these sensor converters, there is a considerable amount of change in the zero point, so-called zero drift, due to changes in the environment (temperature, humidity, etc.) in which the sensor converter is placed, aging of the detection end itself, etc., especially at the detection end. For this zero drift compensation, as shown in Figure 2 (A), a zero adjustment circuit consisting of a town 7S resistor VF and a voltage changing resistor R is provided, and the input light amount is set to zero during correction, and a variable resistor is used. There is one that improves the VFI so that the output voltage vo becomes zero.
また、第3図には工業プロセスや検査工程で使用される
零点補正回路を示す。この場合、検出端/とプリアンプ
λからなるセンサ変神器の出力Ml 。Further, FIG. 3 shows a zero point correction circuit used in industrial processes and inspection processes. In this case, the output Ml of a sensor transformer consisting of a detection terminal and a preamplifier λ.
を差動増幅器3の一方の入力とし、その他方の入力にホ
ールド回路≠の出力VHとしてその差分を零補償し九出
力vo′とし得る工うにしている0ここで、ホールド回
路弘lは検出端/の物鼎帯を零にしたときのプリアンプ
−〇出力全取込んで記憶し、そのtitプリアンプコの
出力から引算するホールド回路弘の出力VFIとする。is set as one input of the differential amplifier 3, and the other input is set as the output VH of the hold circuit≠. Capture and store the entire preamplifier output when the output band at the end is set to zero, and use it as the output VFI of the hold circuit that is subtracted from the output of the tit preamplifier.
この従来例では零補正を第2図(A)の工5に可変抵抗
を調整するという煩わしい作業を不要にして測定時にホ
ールド回路弘の入力にプリアンプ2の出力を与えるスイ
ッチタの簡単な操作で済み、?補正を頻繁に数多く行な
り必要のちる工業プロセスや検査工程に多く採用される
0
発明が解決しようとする問題点
第3図に示す従来の零点補正回路は、補正操作が簡単で
検出端及びプリアンプを含んだセンナ変換器全体の零点
補正ができる。しかし、ホールド回路≠はコンデンサの
充電記憶を利用するため、自然放電によるドリフトが存
在する。このドリフトは少なくするにはコンデンサの静
電容量を大きくすれば良いが、プリアンプ出力電流が比
較的小さいことからその光電に時間がかかりスイッチタ
を押す時間が長くなり、迅速な測定を難しくする。In this conventional example, zero correction can be done by simply operating the switcher that supplies the output of the preamplifier 2 to the input of the hold circuit Hiro during measurement, eliminating the troublesome work of adjusting the variable resistor in step 5 of Fig. 2 (A). Done? Problems to be Solved by the Invention The conventional zero point correction circuit shown in FIG. It is possible to perform zero point correction for the entire Senna converter including However, since the hold circuit ≠ uses the capacitor's charge memory, there is a drift due to natural discharge. This drift can be reduced by increasing the capacitance of the capacitor, but since the preamplifier output current is relatively small, the photovoltaic process takes time, making it difficult to press the switch, making quick measurements difficult.
また、最終段になる差動増幅器3についてはそのドリフ
トを補償できないため、依然としてドリフト分が残る問
題がある。Further, since the drift of the differential amplifier 3, which is the final stage, cannot be compensated for, there is still a problem that the drift remains.
問題点を解決するための手段
本発明は、センサ変揄器の出力と零点補正信号との差を
センサ出力とする差動増@器と、該センサ出力と零点補
正信号との和をとる加算回路と、この加算回路の出力を
零点補正時にディジタル信号に変換して記憶しこの内容
をアナログ信号に戻して前記零点補正信号として出力す
る記憶回路とを備える。Means for Solving the Problems The present invention provides a differential multiplier whose sensor output is the difference between the output of a sensor transformer and a zero point correction signal, and an adder which takes the sum of the sensor output and the zero point correction signal. and a storage circuit that converts the output of the adder circuit into a digital signal during zero point correction, stores it, converts the content back into an analog signal, and outputs the converted signal as the zero point correction signal.
作 用
センサ変換器の入刃物理号の変位を零にした状態では、
センサ変換器の出力にはドリフト分が現われ、このドリ
フト分と記憶回路の零点補正値との差分を差動増幅器に
得て該差分に加算回路で零点補正値を加えることにエリ
加xri5]路にはドリフト分が現われ、これ全記憶回
路の祈念な記憶データとして零点補正値とすることで差
動増幅器の出力にはドリフト分を除いた零にし、零点補
正値は討ドリフト分にする。そして、差動増幅器等の各
要素のドリフト分も含めて補正した零点補正をし、記憶
回路は記憶データを次回補正まで破壊されることなく保
持する。When the displacement of the force sensor converter is zero,
A drift component appears in the output of the sensor converter, and the difference between this drift component and the zero point correction value of the memory circuit is obtained in the differential amplifier, and the zero point correction value is added to the difference by the addition circuit. A drift component appears in , and by using this as a zero point correction value as the stored data of all the memory circuits, the output of the differential amplifier becomes zero excluding the drift component, and the zero point correction value is made to be the zero point correction value. Then, the zero point correction is performed including the drift of each element such as the differential amplifier, and the storage circuit holds the stored data without being destroyed until the next correction.
実施例 第1図は本発明の一実施例を示す回路図である。Example FIG. 1 is a circuit diagram showing an embodiment of the present invention.
検出端/及びプリアンプλによる物理量の検出信号Vo
d差励差幅増幅器一方の入力にされる。差動増幅器3の
出力はセンナ出力volとして取出されるほかに加算回
路乙の一方の加算入力にされる。Detection signal Vo of physical quantity by detection terminal/and preamplifier λ
d difference excitation width amplifier is applied to one input. The output of the differential amplifier 3 is taken out as the senna output vol and is also applied to one addition input of the addition circuit B.
差動増幅器3及び加算回路乙の他方の入力には零点補正
値eが与えられる。加算回路乙の出力はA / D変換
器7の変換入力にされる。ラッチ回路rはA / D変
換器7の定検データを一時記憶するために取込む。D
/ A変換器りはラッチ回路rの記憶データをアナログ
信号に変換して零点補正値として出力する。コントロー
ル回路IOは変F’ b 7tり及びラッチ回路rの変
揄タイミング及びラッチタイミングを零点補正指令用ス
イッチlOAの投入で発生する。The zero point correction value e is given to the other input of the differential amplifier 3 and the adder circuit B. The output of the adder circuit B is input to the A/D converter 7. The latch circuit r takes in periodic test data of the A/D converter 7 for temporary storage. D
/ The A converter converts the data stored in the latch circuit r into an analog signal and outputs it as a zero point correction value. The control circuit IO generates the variable F'b7t and the variable timing and latch timing of the latch circuit r by turning on the zero point correction command switch 1OA.
こうした構成に′おいて、7〜IOからなる記憶回路は
加算回路乙の出力をディジタル信号に定押してラッチ回
路tに記憶し、この記憶データに対応するアナログ信号
出力を零点袢正値eとして出力する。そして、ラッチ回
路rの記憶データ更新はスイッチIOAの一時投入に:
つでコントロール回路10がA/D変換器7への変孕指
令、次いでラッチ回路?へのラッチ指令を夫々1回発し
て行なわれる。またD / A変換器2にも定検指令を
発してラッチ回路rの記憶データに対すするアナログ信
号(零点補正値)を直流電圧として出力させる0零点補
正時には検出端/の物理量入力を零にする。例えば、光
センナであればその光入力をしゃ断する。この状態でス
イッチ10 A t″投入て記憶回路の記憶データを更
新する前にはプリアンプλの出力voと差動増幅器3の
出力vo′との関係は次の(1)式になる。In such a configuration, the memory circuit consisting of 7 to IO converts the output of the adder circuit B into a digital signal, stores it in the latch circuit t, and outputs the analog signal output corresponding to this stored data as the zero point plus value e. do. Then, the data stored in the latch circuit r is updated by temporarily turning on the switch IOA:
Then the control circuit 10 issues a conversion command to the A/D converter 7, and then the latch circuit? This is done by issuing a latch command to each one once. A periodic inspection command is also issued to the D/A converter 2 to output an analog signal (zero point correction value) for the data stored in the latch circuit r as a DC voltage.During zero point correction, the physical quantity input at the detection end is set to zero. do. For example, if it is an optical sensor, its optical input is cut off. In this state, before the switch 10 A t'' is turned on to update the data stored in the storage circuit, the relationship between the output vo of the preamplifier λ and the output vo' of the differential amplifier 3 is expressed by the following equation (1).
V6’=V(1−e + e d−111,(1)ここ
で1 θdは差動増幅器3のドリフト分である。V6'=V(1-e+e d-111, (1) where 1 θd is the drift of the differential amplifier 3.
次に、スイッチ10Af投入すると、記憶データは加算
回路乙の出力になるV6’+eに更新されて新しい零点
補正@eNになる。Next, when the switch 10Af is turned on, the stored data is updated to V6'+e, which is the output of the adder circuit B, and becomes the new zero point correction @eN.
LA N = Vo’ + e −・” (2)この両
式(1)l(2)からθを消去するとvo−θH+ e
a = 0−− (3)となる。すなわち、更新され
た零点補正値θNに工って差動増@器3の出力vo’=
oになり、検出端/、プリアンプコ及び差動増幅器3
の各ドリフト分を補正した零点補正になる。この零点補
正値eは以後のセンナ動作に連続して与えられ、以後の
測定にドリフト分金無くす。しかも、eは加算回路IG
、A/D変換器7.’f)/A変換器りの変換。LA N = Vo' + e -・" (2) Eliminating θ from both equations (1) and l(2) yields vo-θH+ e
a = 0-- (3). In other words, the updated zero point correction value θN is used to obtain the output vo'=of the differential amplifier 3.
o, detection end/, preamplifier and differential amplifier 3
This is the zero point correction that corrects each drift amount. This zero point correction value e is continuously applied to subsequent sensor operations, thereby eliminating drift in subsequent measurements. Moreover, e is an adder circuit IG
, A/D converter 7. 'f)/A converter conversion.
演算誤差分を含めt補正になるし、ラッチ回路rによる
ディジタル記憶でデータ破壊が起きることはない。The t correction includes calculation errors, and data destruction does not occur in digital storage by the latch circuit r.
発明の効果
本発明によれば、零点補正値をディジタル貴で記憶保持
するため、従来のコンデンサの充電電圧によるアナログ
量記憶に較べて記憶内容の変化や記憶更新の手間(記憶
操作頻度)9時間の問題が解消される。また、零点補正
値は出力端からのフイードバック系を持つため、差動増
幅器のドリフト分及び記憶回路の各部ドリフト分も含め
た補正値になって精度良い補正を得ることができる。Effects of the Invention According to the present invention, since the zero point correction value is stored digitally, it takes 9 hours less time to change the stored contents and to update the memory (memory operation frequency) compared to the conventional analog quantity storage using the charging voltage of the capacitor. problem is solved. In addition, since the zero point correction value has a feedback system from the output end, the correction value includes the drift of the differential amplifier and the drift of each part of the memory circuit, so that highly accurate correction can be obtained.
先回面の簡単な説明
第1図は本発明の一実施例を示す回路図、第2図(A)
及び第2図(B)はセンサ変換器全例示する回路図、第
3図は従来の零点補正センサ回路図である。Brief explanation of the previous section Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 (A)
2(B) is a circuit diagram showing an example of a sensor converter, and FIG. 3 is a circuit diagram of a conventional zero point correction sensor.
l・・・検出端、λ・・・プリアンプ、3・・・差動増
幅器、t・・・加算回路、7・・・A / D変換器、
?・・・ラッチ回路、り・・・D / A変換器、10
・・・コントロール回路、10k・・・零点補正指令用
スイッチ。l...detection end, λ...preamplifier, 3...differential amplifier, t...addition circuit, 7...A/D converter,
?・・・Latch circuit, ri...D/A converter, 10
...Control circuit, 10k...Switch for zero point correction command.
第1図Figure 1
Claims (1)
をプリアンプで信号処理可能なレベルまで増幅するセン
サ変換器と、この変換器の出力と零点補正信号との差を
センサ出力とする差動増幅器と、前記センサ出力と零点
補正信号との和をとる加算回路と、この加算回路の出力
を零点補正時にディジタル信号に変換して記憶しこの内
容をアナログ信号に戻して前記零点補正信号として出力
する記憶回路とを備えたことを特徴とする零点補正セン
サ回路。A sensor converter that converts the physical quantity to be detected into an electrical signal at the detection end and amplifies this signal to a level that can be processed by a preamplifier, and a differential sensor that uses the difference between the output of this converter and the zero point correction signal as the sensor output. an amplifier, an adder circuit that sums the sensor output and the zero point correction signal, and the output of this adder circuit is converted into a digital signal during zero point correction and stored, and this content is returned to an analog signal and output as the zero point correction signal. 1. A zero point correction sensor circuit comprising: a memory circuit for storing data;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59187050A JPS6165113A (en) | 1984-09-06 | 1984-09-06 | Sensor circuit with zero point compensation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59187050A JPS6165113A (en) | 1984-09-06 | 1984-09-06 | Sensor circuit with zero point compensation |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6165113A true JPS6165113A (en) | 1986-04-03 |
JPH0572525B2 JPH0572525B2 (en) | 1993-10-12 |
Family
ID=16199295
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59187050A Granted JPS6165113A (en) | 1984-09-06 | 1984-09-06 | Sensor circuit with zero point compensation |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6165113A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004093442A (en) * | 2002-09-02 | 2004-03-25 | Polymatech Co Ltd | Output value correction method of analog switch, computer program and analog switch |
WO2016166824A1 (en) * | 2015-04-15 | 2016-10-20 | 理化工業株式会社 | Sensor signal converter and sensor signal converting method |
-
1984
- 1984-09-06 JP JP59187050A patent/JPS6165113A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004093442A (en) * | 2002-09-02 | 2004-03-25 | Polymatech Co Ltd | Output value correction method of analog switch, computer program and analog switch |
WO2016166824A1 (en) * | 2015-04-15 | 2016-10-20 | 理化工業株式会社 | Sensor signal converter and sensor signal converting method |
Also Published As
Publication number | Publication date |
---|---|
JPH0572525B2 (en) | 1993-10-12 |
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