JPS63260527A - Endoscopic apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an endoscope apparatus in which a signal processing unit with a connector is replaceably provided to correspond to scopes with different electrical signal processing.

[Prior art 1] In recent years, by inserting an elongated insertion section into a body cavity,
It is possible to observe the internal parts of the body cavity without making an incision, and to perform therapeutic treatment using treatment tools as necessary. J
21! became widely used.

In addition to the optical endoscope (fiberscope) that uses an image guide as an image transmission means, the endoscopes mentioned above include
Electronic endoscopes (hereinafter referred to as electronic endoscopes or electronic scopes) using solid-state imaging means such as D have come into practical use.

Advances in manufacturing technology for the CCD solid-state image sensing device described above are remarkable, and devices with a larger number of pixels and higher sensitivity are being developed one after another.

[Problems to be solved by the invention] Therefore, when an electronic endoscope is constructed by incorporating these, a camera control unit (referred to as CCLJ) that performs dedicated signal processing corresponding to the solid-state image sensor to be incorporated is required. .

), which would be inconvenient for the user.

The present invention was made in view of the above-mentioned points.
The object of the present invention is to provide an endoscope device that can be used with scopes with different X-air signal processing by simply replacing the camera control unit of the connector (j!).

[Means and effects for solving the problems] In the present invention, a camera control unit with a connector is covered with a video processor configured to be replaceable to correspond to scopes that require different signal processing. The number of signal processing parts to be replaced is small, and it is possible to economically cope with scopes that require different signal processing.

[Example 1 Hereinafter, the present invention will be specifically explained with reference to the drawings.

1 to 10 relate to a first embodiment of the present invention, FIG. 1 is an original configuration diagram of the first embodiment, and FIG. 2 is a configuration of a video processor 1 in iI3 of the first embodiment. Figure 3 is the circuit diagram of the scope/CCU match determination circuit, Figure 4 is the COD
A block diagram showing the drive circuit, Figure 5 is a block diagram of the clamp/sampling pulse generation circuit, and Figure 6 is a block diagram of the clamp/sampling pulse generation circuit.
7. Timing chart diagram for explaining the operation of Fig. 5 and Fig. 5.
Figure 8 is a configuration diagram of the low-pass filter, Figure 8 is a configuration diagram of the main control circuit, Figure 9 is a configuration diagram of the horizontal contour correction circuit, and Figure 1 is a configuration diagram of the horizontal contour correction circuit.
FIG. 0 is a waveform diagram for explaining the operation of FIG.

The internal mirror device 1 of the first embodiment shown in FIG. 2
Represented by I. 21, a video processor (one-layer image device main body) 3 that supplies illumination light and processes signals, and a color processor that is connected to the output end of this video processor 3 and displays input video signals in color. It is composed of a monitor 4.

The video processor 3 includes a light source section 5 that supplies illumination light to each scope 2I, and a signal processing section 6, which is connected to the scopes 2A, 2B, and 2C, respectively.
, Dedicated signal processing unit or camera control unit (hereinafter referred to as CCU) in which the part that performs signal processing specific to 2D is made into a replaceable unit 7△, 7B, 70.7
D, and a common CCU 8 which is a part that performs common signal processing for each squaw 12.

The CC1J7Δ, 7B, 7G, and 7D have signal connector receivers 9A, 9B, 9C, and 9D, respectively, while the CCU9A with corresponding η to each space]-12, 2B, 2G, and 2D.
, 9B, 9C, 9D signal connector 1
1A, 118.11G.

It is equipped with 11Dtfi.

Each scope 21 has an elongated insertion section 12 so as to be inserted into a body cavity, and a signal cable 13 and a light guide cable 14 are extended from an operation section at the rear end of this insertion section 2. A signal connector 111 is provided at the end of the signal cable 13, and a light source connector 16 that can be attached to the light source connector receiver 15 of the light source section 5 is provided at the end of the light guide cable 14.

Each of the above scopes 2I is shown in Fig. 2, for example.
As in case A, a light guide 21 that transmits illumination light is inserted into the insertion section 12, and this light guide 21
By attaching the rear end to the light source section 15, the light source section 1
5, red, green, and blue illumination light is sequentially supplied from the tip of the light guide 21 to the subject side through the light distribution lens 22.
I can finish 4.

The light source section 5 that supplies illumination light to the proximal end surface of the light guide 21 is arranged to face the light source lamp 23, a collimator lens 24 that converts the illumination light of the light source lamp 23 into a parallel beam, and the collimator lens 24, light guide 2
It consists of a condenser lens 25 that condenses and irradiates light on one end surface of the lens 24, a rotary filter 26 interposed in the optical path between these two lenses 24 and 25, and a motor 27 that rotationally drives the rotary filter 26.

The light source lamp 23 is a white light source such as a xenon lamp, while the rotating filter 26 is a red light source.

Red, green, and blue transmission filters 26R926G, 26 that transmit green and blue multiwave light, that is, R, G, and B, respectively.
B is formed in a fan shape, and by rotating the rotary filter 26, these R and G.

It is designed to illuminate sequentially with 8 lights of B3 primary colors. The rotation of the motor 27 that rotates the rotary filter 26 is controlled by a rotation servo circuit 29.

The rotation servo circuit 29 includes a frequency reference signal generator and a phase reference generator, and the rotation of the motor 27, whose rotation is controlled by the rotation servo circuit 29, is at the frame frequency of the video signal. .97H
7).

The object illuminated sequentially with the above six lights of R, G, and B is
An image is formed on the image plane of the CCD 321 by the objective lens 31 disposed at the tip of the scope 2I.

The above CCD 32I has blocks 2A, 2B, 20.2D.
The number of bichords differs depending on the number of chords.

(In FIG. 2, the scope 2Δ is shown, so in this case it is the CCD 32Δ.) The CCD 32A is photoelectrically converted by applying a drive pulse for transfer and reading by the COD drive circuit 33A in the CCU 7A. The signal is read out. still,
This drive pulse and the signal from the rotation servo circuit 29 are input to a synchronization signal generator 34, and a synchronization signal for displaying the read signal is generated.

The output signal of the CCD 32A is amplified by a preamplifier 35 forming the CCU common section 8, and is input to a double sampling circuit 37 via an isolation circuit 36 that protects the patient from electric shock. This double sampling circuit 37 performs double sampling to remove 1/f and reset noise contained in the CG'D output signal, and removes noise components to produce a signal with improved S/N.

The double sampling circuit 37 receives clamp pulses and sampling pulses from a clamp/sampling pulse generation circuit 38A to which the output signal of the synchronizing signal generator 34 is input. The signal number from which the above noise component was removed is the low-pass filter (LPF) in CCU 7Δ.
39A, unnecessary high frequencies such as COD carriers are removed, and the signal is input to the γ correction circuit 40 in the CCU common section 8, where it is subjected to γ correction. In other words, when displaying on a display tube, the nonlinearity (usually γ = 2.2) of the electrical/optical conversion system is corrected, and the A/
The signal is input to the D converter 41. The A/D converter 41 converts the signal into a digital signal, and the signal transferred under the sequential illumination is stored in the frame memories 42R and 4.
2G, 42B, the signal read from CCD 32A is 1
It is written one frame at a time. That is, for example, an image is captured under illumination with red light through the red transmission filter 26R, and the read signal is written into the frame memory 42R. Therefore, each frame memory 42R, 42G, 42B has one
When one frame's worth of image data is written, they are simultaneously read out, converted into analog signals by the D/A converter 43, and then passed through the low-pass filter 44 in the CCU 7A.
Each is input to A. Unnecessary high frequencies are removed by each low-pass filter 44A, and each signal is input to a horizontal contour correction circuit 45A. Above A/D converter 4
1 conversion speed and each frame memory 42R, 42G.

Loading and reading of data into and from CCU 42B is controlled by an output signal from memory control circuit 46A within CCU 7A.

The output signal of this memory control circuit 46A is generated in synchronization with the synchronization signal of the synchronization signal generator 34.

The signals subjected to the horizontal contour correction in the horizontal contour correction circuit 45Δ are each amplified by the output amplifier 47, and the R, G, B signals with an output impedance of 75Ω, for example, are
It is designed so that it can be output from the RGB output terminal 48 as three primary color signals. Further, the composite synchronization signal of the synchronization signal generator 34 is also outputted from the synchronization signal output #A50 through the output amplifier 49.

The R, G, and B outputs passed through each of the output amplifiers 47 and the synchronization signal output passed through the output amplifier 49 are inputted to the RG8 compatible color monitor 4, so that the subject image can be displayed in color.

The video processor 3 having the above configuration includes a CCU 71 that is plugged in and installed, and a CCU 71 that is installed.
Is the connected scope 2I suitable, that is, the CCU?
A scope/CCU matching determination circuit 51 is provided for determining whether scope/CCU matching is established or not, and whether or not the scope 2 (2) which is capable of signal processing at 71 is connected is connected.

This (scope/CCU) match determination circuit 51
The type signal generation 3521 in the U7I and the type signal output from the type signal generator 531 of the scope 2I are taken in, and it is determined whether they match.

The above-mentioned type signal generators 52I and 53I connect the CCD of the scope 2I between each two terminals connected to the match determination circuit 51.
It is constructed by connecting a resistor R1 having a value set corresponding to the number of pixels, 321, etc.

On the other hand, the match determination circuit 51 has a configuration shown in FIG. 3, for example.

One end of the two terminals 61a, 61a into which the type signal is input is connected to the power supply terminal (for example, +5V) Vc, and the narrow end is grounded via the resistor r, and the three comparators 62
It is connected to each non-inverting input terminal of a, 63a, and 64a.

Each of the inverting input terminals of these comparators 62a, 63a, and 64a has a voltage E1. E2. E3 (El>E2>E3) is applied.

These comparators 62a, 63 . The outputs of a and 64a are exclusive OR (EX-OR>circuits 65 and 66
．． It is input to one input end of 67.

On the other hand, two terminals 61b into which the other type signal is input.
, 61b, three comparators 62b, 63b
, 64b are configured in a similar circuit, and the outputs of these comparators 62b, 63b, and 64b are also input to the other input terminal of EX-OR circuits 65, 66, and 67, respectively. The outputs of these EX-OR circuits 65 are input to a three-man OR circuit 68, and if the output of this A-A circuit 68 is "HII", it outputs a signal that does not match, and if it matches, it outputs an IN signal.
It becomes 111.

Furthermore, CCD of scope 2■ in each CCIJ7I
The configuration of each circuit set corresponding to H.321 will be described below. .

First, the COD drive circuit 33I is shown in FIG.

The clock output of the synchronization signal generator 29 is passed through the 1/N frequency divider 71
(■ is omitted because it is common), and this divided clock is input to the waveform generation circuit 72, passes through the 1/M frequency divider 73, is further divided, and then the waveform It is also input to the generation circuit 74.

The above 1/N frequency divider 71 and 1/M frequency divider 73 have N and M (CCDs 32A, 32B, 32G).

32D) CCU7A, 7B, 70.7
It is determined according to D.

The waveform generation circuit 72 generates horizontal transfer pulses φH1, φH
2. Output a reset pulse and use the other waveform generation circuit 74
is the vertical transfer pulse V1. Outputs V2.

Moreover, the clamp/sampling pulse generation circuit 38I is
As shown in FIG. 5, the output signal of the synchronizing signal generator 34 (I is abbreviated) is input to the 1/N frequency divider 75,
After being frequency-divided by N, the signal is input to the waveform shaping circuit 76. This waveform shaping circuit 76 outputs a clamp pulse and a sampling pulse.

The operation of the COD drive circuit 33I and clamp/sampling pulse circuit 38I shown in FIGS.
Illustrated in the diagram.

Based on the clock output of the 11 signal generator 34, COD
The waveform generation circuit 72 of the drive circuit 331 is shown in FIG. 6(a).
A reset pulse as shown in FIG. 3 and a horizontal transfer pulse φt11 as shown in FIG. 10B are output, and a COD output signal as shown in FIG. On the other hand, the waveform generating circuit 76 to which the clock of the 1/N frequency divider 71 is input and forming the clamp/sampling pulse generating circuit 38A generates clamp pulses and pulses as shown in FIGS. 6(d) and (e). Output sampling pulse.

In other words, using the reset pulse and horizontal transfer pulse, C
The output signal 2) read from the CD 32I has a reset pulse portion and a field through portion mixed into the signal portion, as shown in FIG. 6(C). For this reason, a clamp pulse whose phase is delayed by f phase from the reset pulse and a limp ring pulse synchronized with a signal portion whose phase is further delayed from this clamp pulse are generated, and these clamp pulses and sampling pulses are applied to the double sampling circuit 37. This improves the S/N ratio by removing noise components such as reset pulses.

The clock of the 1/N frequency divider 71 is further input to the waveform generation circuit 74 via the j/M frequency divider 73, and a vertical transfer pulse corresponding to the number of vertical pixels is generated.

Also, as the number of pixels of the CCD 321 increases, the frequency of the pulse increases, so the CO output with that pulse increases.
The signal band of the D image signal becomes wider, and therefore the highest frequency becomes higher. Therefore, it is necessary to raise the cutoff frequency of the pass filter 441, and if there are few prime numbers, the cutoff frequency is lowered and unnecessary. It is desirable to prevent harmonics from entering the signal. Moreover, each memory 42R, 42
G.

After reading the image O signal data written in 42B, D/
The same thing can be said about the signal when A-converted.

For this reason, each CCU 71 has a CCD 321 for signal processing.
A low-pass filter 391 whose filter characteristics correspond to the above is used.

For example, the low-pass filter 391 has a configuration as shown in FIG. A signal inputted from the input terminal via the double sampling circuit 37 passes through the buffer 1 amplifier 81, and then is inputted to the low-pass filter 821 connected in series with the resistor R'I.

[The output terminal of the corpus filter 821 is connected to a matching resistor R'
It is connected to ground via I, and a signal is output to the next stage via buffer 83.

The above-mentioned low-pass filter 391 is connected to each CCD 32.
For one pixel count, unnecessary harmonics are removed by cutting off frequencies higher than the highest frequency component included in the signal determined by the drive pulse used for readout according to the sampling theorem.

The configuration of the memory control circuit 461 that controls the memories 42R, 42G, and 42B is shown in FIG. The signal is input to the read pulse generating section 92 and the write/read control section 93 as well as the read pulse generating section 92 and the write/read control section 93.

The write pulse generating section 91 generates a write pulse corresponding to the number of pixels, and inputs the write pulse to the read/write switching circuit 95. This read/write switching circuit 95 has two digital input terminals and two digital output terminals (each having a plurality of bits), and is controlled by the output signal of the write/read control circuit 93 from the write pulse switching circuit 94 side. The write pulse inputted from the side of the read pulse generation circuit 92 and the read pulse inputted from the read pulse generation circuit 92 side can be switched and outputted from two output terminals. For example, when signal data imaged under R illumination is input through the A/D converter 41, the signal data is written in the R first memory 97at;
To the first memory 97a (for example, when a write mode signal is applied from the write/read control circuit 93)
A write pulse is applied to its address end. In this state, the other R second memory 77b is in a state where the read pulse from the read pulse generator 92 can be applied, and the read pulse is applied at a predetermined timing (when the R first memory is in the read mode). 1-mode) and the written signal data is read out. Each memory 97a, 97
b is composed of an IC such as a dynamic RAM such as a tri-state or a static RAM.

R 1st. Output selection circuits 98a and 98b are provided at the data output terminals of the R-second EIJs 97a and 97b, respectively, and are controlled to turn on or off by, for example, H or L11 from the write/read control circuit 93. These output selection circuits 98a and 98b are turned on during read mode after being set to write mode, and the read signal data is converted to serial data via output selection circuit 98a or 98b, and is then sent to the next stage D/A. It is output to the converter 43 side. These output circuits 98a and 98b are also composed of tri-state ICs and the like.

Note that the memory control at the time of reading is determined by the signal format such as NTSC, regardless of the scope having a different number of pixels.
may be fixed.

Furthermore, R 1. The memory capacity of the second memories 97a and 97b is such that it will not be insufficient even in the case of the maximum number of pixels.
In the case of a small number of pixels, a part of the memory capacity 4 is used.

Note that the read pulse generator 92 is connected to the G memory control circuit 90.
A common circuit is also used for the G and B memory control circuits 90B. In other words, in the read mode, the signal data written in the R, G, and B memories 42R, 42G, and 42B are read out at the same time. ,42G,
42B is provided with two memories as described above so that rewrite and read operations can be performed independently.

The above read mode is R, G, [3 memory 421,
Since this is performed simultaneously for 42G and 42B, one may be used in common without installing three read pulse generating sections 92.

Note that the write pulse generating section 91. The read pulse generator 92 is determined depending on the scope 2I.

The signal data simultaneously read out from each memory 42R, 42G, and 42B is converted into an analog signal by the D/A converter 43 whose conversion clock number is controlled by the memory control circuit 461, and is inputted to the respective low-pass filters 4/II. .

Each low-pass filter 441 has a circuit configuration similar to that shown in FIG. 7, and is band-controlled to a band corresponding to the number of pixels and input to the horizontal contour correction circuit 45I. Each horizontal contour correction circuit 45I is also designed to perform appropriate contour correction according to the number of pixels, and its configuration is shown in FIG. The signal input from the input terminal via the low-pass filter 441 is
After being delayed by, for example, Ti in the second delay line 101, the second delay line 102 is also delayed by Ti. Note that this Ti is determined according to the scope 2I. Therefore, if the signal applied to the input terminal is as shown in FIG.
), as shown in (c).

The signal input from the input terminal and the second delay line 10
The signal delayed in step 2 is added in the first adder 103, resulting in the signal shown in FIG. 10(d), and this signal is
The signal is passed through the coefficient unit 104 which makes it 2 and becomes the signal shown in FIG. The signal that has passed through the first delay line 101 is also input to this adder 105, and these are added to form the signal shown in FIG. The signal that has passed through the first delay line 101 is also input to this adder 107, and these signals are added to produce a horizontal contour-corrected signal as shown in FIG. 10 (0). and is output from the output end to the next stage.

Note that the amount of delay caused by the delay lines 101 and 102 is set in advance to an appropriate value depending on the number of pixels.

According to the first embodiment configured in this way, if the dedicated CCLI 7I is plugged in or installed in the video processor 3 according to the scope 2 to be used, the color monitor 4
Can be displayed in color.

Therefore, it can be handled more economically than when a dedicated video processor (in its entirety) must be prepared for Scope 2 (2).

Also, when using a scope with a different number of pixels, (,C
This can easily be done by removing U71 and replacing it with the dedicated CCU71.

In the first embodiment described above, the C
Although there is only one CU, in the second embodiment, as shown in FIG. 11, the video processor 111 has two CCLIs (
For example, 7A and 7B) are arranged side by side so that they can be attached and detached.

It should be noted that it can also be configured so that three or more CCUs can be installed.

Incidentally, in the above embodiment, an electronic scope with a field sequential imaging method is attached and used, but the present invention is an electronic scope with a simultaneous imaging method in which a mosaic filter is arranged in front of the imaging surface of a CCD 32I under white illumination. The method can be similarly applied to cases where the number of pixels is different.

It should be noted that a unit may also be provided for the light source section 15, etc., and this unit may be integrated with the video processor or may be separate. Furthermore, when it is made into a unit, it can be installed in a video processor by replacing it in the case of a frame-sequential type and the case of a simultaneous type.

Furthermore, the CCU common part within the video processor can also be made into a unit so that it can be converted between frame-sequential and simultaneous formats.

Although a scope/CCU matching judgment counter path is provided, it would be unnecessary if the shape of the signal connector of the scope and the connector receiver on the CCU side could be connected only when the scope and CCU match. Depending on the scope, the connector (shape, number of bins, shape of bins, arrangement W)
It can also handle cases where the values are different.

[Effects of the Invention] As described above, according to the present invention, the signal processing section, which must perform different signal processing depending on the number of pixels of the scope, etc., is made into a unit, so all that is required is to replace the unit part. It can be economically applied to scopes with different numbers of pixels.

[Brief explanation of drawings]

Figures 1 to 10 relate to one embodiment of the present invention;
Figure 2 is a block diagram showing the basic configuration of the first embodiment, Figure 2 is a configuration diagram showing the configuration of the video processor, Figure 3 is a circuit diagram showing the configuration of the scope/CCU match determination circuit, and Figure 4 is the COD. The drive circuit is not shown. Figure 5 is a block diagram of the clamp/sampling pulse generation circuit. Figure 6 is a block diagram of the clamp/sampling pulse generation circuit.
The figure is a timing diagram for explaining the operation of Fig. 5, Fig. 7 is a 71 block diagram showing the structure of the low-pass filter, Fig. 8 is a block diagram without showing the structure of the memory control circuit, and Fig. 9 is a horizontal contour correction FIG. 10 is a waveform diagram for explaining the operation of FIG. 9, and FIG. 11 is a configuration diagram showing a second embodiment of the present invention. 1... Endoscope neck 2... (electronic) scope 3... Video processor 4... Color monitor 5.
...Light source part 6...Signal processing part 7A, 7B
, 70.7D...Camera controller 1-roll unit (C
CU) 8...CCLJ common part 9A...Signal connector receiver 11A...Signal connector 15...Light source connector receiver 16...Light source connector 32A...C0D 33A...COD drive Circuits 39A, 44A...O-pass filter 45...Horizontal contour correction circuit 46A...Memory control circuit Fig. 1, Fig. 6, Fig. 7, 39I L, w Fig. 11

Claims (1)

[Scope of Claims] A scope that uses solid-state imaging devices with different numbers of pixels as imaging means can be attached, and has a video processor that processes signals input from the imaging means and can display them on a monitor device. An endoscope apparatus, characterized in that a signal processing section that requires different signal processing for scopes having different numbers of pixels is formed into a unit and is replaceably mounted on a video processor.