JP2547226B2 - Electronic endoscopic device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an electronic endoscope apparatus that can be used in an electronic scope using a solid-state image pickup device having a different number of pixels.

[Prior Art] In recent years, an imaging device using a solid-state imaging device such as a charge-coupled device (hereinafter referred to as CCD) as an imaging means has been widely used.

Also, in the field of endoscopes, instead of an optical endoscope (referred to as a fiberscope) using an image guide for transmitting an optical image, an electronic type using a CCD without using an image guide. Endoscopes (referred to as electronic scopes) have come into practical use.

The use of the electronic scope has an advantage that the captured image can be easily recorded and reproduced.

Since the outer diameter of the insertion part of the electronic scope is restricted by the size of the CCD, a CCD having a different size is used depending on the insertion site.

[Problems to be Solved by the Invention] Since the number of pixels varies depending on the size of the CCD, in the conventional example, at least the signal processing circuit section is fixed in the apparatus main body section to which the electronic scope is connected. However, there was a drawback that it could only be used for electronic scopes using CCDs of the same type and specifications.

The applicant of the present invention has filed a patent application as a technology related to the present application.
In No. 7472, we proposed that the scope and the drive pulse generation circuit are built in the scope so that they can be used in a common device body. In this related art example, since the above-described oscillator and the like are built in each electronic scope, there is a possibility that the cost may be increased or the size may be increased, and there is room for improvement.

The present applicant has proposed in Japanese Patent Application No. 61-55512 a unitized drive pulse generation circuit that can be attached to and detached from an apparatus main body that houses a video processor. In this related art example, it is necessary to use a unit corresponding to a scope as a pair, and in the case of many types, the operation becomes complicated, there is a possibility of erroneous operation, and there is room for improvement.

The present invention has been made in view of the above points, and an object of the present invention is to provide an electronic endoscope apparatus that can be used with a simple operation with one apparatus main body for an electronic scope having a different number of pixels. I do.

[Means and Actions for Solving Problems] According to the present invention, an electronic endoscope apparatus including a plurality of electronic scopes having different numbers of pixels and a main body apparatus to which the electronic scopes can be connected is built in the electronic scope. The electronic scope to be connected is provided with a pixel number detecting means for automatically detecting the number of pixels of the solid-state image pickup device, and signal processing means for setting a frequency characteristic corresponding to the pixel number in response to the output of the detecting means. The signal processing suitable for the number of pixels is performed.

EXAMPLES The present invention will be specifically described below with reference to the drawings.

1 to 9 relate to one embodiment of the present invention.
FIG. 1 is a block diagram showing a configuration of one embodiment, FIG. 2 is a configuration diagram of an automatic pixel number detection circuit, FIG. 3 is an explanatory diagram showing that there are three types of CCDs as the number of pixels, and FIG. FIG. 5 is a timing chart for explaining the operation of the double sampling circuit, FIG. 6 is a block diagram showing the configuration of the low-pass filter, and FIG. 7 is a block showing the configuration of the memory control circuit. 8 and 9 are configuration diagrams of the horizontal contour correction circuit, and FIG. 9 is a waveform diagram for explaining the operation of FIG.

As shown in FIG. 1, an electronic endoscope apparatus (electronic scope apparatus) 1 according to one embodiment includes an electronic endoscope (electronic scope) 2 having an image pickup means incorporated therein, and this electronic scope 2 (and A light source unit 3 for supplying illumination light to different electronic scopes,
A signal processing unit 4 that converts a signal captured by the electronic scope 2 into a video signal that can be displayed on a display device, determines the number of pixels of the mounted electronic scope 2, and performs signal processing corresponding to the mounted electronic scope 2. The main body device 6 accommodates the control means for performing the operation.

The electronic scope 2 has an elongated insertion section 7 formed so as to be easily inserted into a body cavity. An objective lens 8 and a CCD 9 serving as a solid-state imaging device are arranged at the distal end side of the insertion section 7, and imaging means is incorporated. Have been.

A light guide 11 for transmitting illuminating light is inserted into the insertion section 7 to transmit the illuminating light supplied from the light source section 3 and to emit the illuminating light from the front end face. The lens 12 is expanded to illuminate the subject 13 side.

The light source unit 3 that supplies the illumination light to the end face of the light guide 11 on the hand side includes a light source lamp 4, and a lens 15 that collects and illuminates the illumination light of the light source lamp 14 onto the end face of the light guide 11.
It comprises a rotary filter 16 interposed in the optical path between the lens 15 and the end face of the light guide 11, and a motor 17 for driving the rotary filter 16 to rotate.

The light source lamp 14 is a white light source such as a xenon lamp, while the rotary filter 16 is light in each wavelength range of red, green and blue, that is, red, green and blue which respectively transmit R, G and B. Each transmission filter 16R, 16G, 16B of is formed in a fan shape,
By rotating the rotary filter 16, these R, G, B3
It is decided to illuminate each of the primary colors in a frame-sequential manner. The motor 17 that rotates the rotary filter 16 includes a rotary servo circuit 19
The rotation is controlled by. The motor 17 includes a pulse generator for detecting the number of rotations and a pulse generator for detecting the rotation phase. The rotation servo circuit 19 allows the motor 17
The rotation of is synchronized with the frame frequency of the video signal (29.97Hz in the case of NTSC system).

The subject 13 illuminated by the R, G, and B lights in a plane-sequential manner is imaged on the imaging surface of the CCD 9 by the objective lens 8, and is applied by a drive pulse for transferring and reading by the CCD drive circuit 21. The photoelectrically converted signal is read. The drive pulse and the rotary servo circuit 19 operate in synchronization with the reference signal supplied from the synchronization signal generator 22.

The output signal of the CCD 9 is amplified by a preamplifier 23 forming the signal processing unit 4 and passes through an isolation circuit 24 which protects the patient from electric shocks and the like.
Entered in 25. This double sampling circuit 25 is a CCD
Double sampling is performed to remove 1 / f and reset noise included in the output signal, and a baseband signal is obtained from the carrier signal, and at that time, noise components are removed to produce a video signal with improved S / N. . This signal is
After passing through a low pass filter (LPF) 26, it is converted into a baseband signal from which unnecessary harmonics such as CCD carrier are removed. Since the output signal of the double sampling circuit 25 is basically subjected to the signal processing using the clamp means, the DC component is also reproduced, and the DC component is also reproduced in the output through the LPF 26. . The signal passed through the LPF 26 is input to the γ correction circuit 27 and γ corrected. In other words, the non-linearity (normally γ = 2.2) of the electric / optical conversion system for displaying on the display tube is corrected and input to the A / D converter 28. This A / D
A signal which is converted into a digital signal by the converter 28 and imaged under frame-sequential illumination is stored in the frame memory 29R,
The signals read from the CCD 9 are written in 29G and 29B for each frame. That is, for example, a signal read out and imaged while being illuminated with red light through the red transmission filter 16R is written in the frame memory 29R. Then, when one frame of image data is written in each frame memory 29R, 29G, 29B, these are read at the same time, converted into analog signals by the D / A converter 31, respectively, and unnecessary high frequencies are removed by the LPF 32. The horizontal contour correction circuit 33
Is input to The conversion speed of the A / D converter 28 and writing / reading of data to / from each frame memory 29R, 29G, 29B are controlled by an output signal from the memory control circuit 34.
The output signal of the memory control circuit 34 is generated in synchronization with the sync signal of the sync signal generator 22.

The signals that have undergone horizontal contour correction in the horizontal contour correction circuit 33 are amplified by the output amplifiers 35, respectively, so that they can be output from the output end as R, G, B3 primary color signals with an output impedance of 75Ω, for example. is there. The composite synchronizing signal of the synchronizing signal generator 22 is also output from the synchronizing signal output terminal through the output amplifier 36.

By inputting the R, G, B outputs through the output amplifiers 35 and the synchronizing signal outputs through the output amplifier 36 to an RGB-compatible monitor, the subject image can be displayed in color.

By the way, when each electronic scope 2 is attached (connected) to the main body apparatus 6, it is necessary to perform signal processing corresponding to the number of pixels of the electronic scope 2 to be connected. An automatic detection circuit 40 is provided and LPF2
The signal passed through 6 is input.

The pixel number automatic detection circuit 40 detects the number of pixels of the CCD 9 in the connected electronic scope 2, and changes the frequency characteristics of the LPF 32 and the horizontal contour correction circuit 33 or the memory control circuit 34 according to the detected output signal. The control is performed so that the optimum characteristics are set for the detected number of pixels.

The pixel number automatic detection circuit 40 basically drives the CCD 9 with the same clock frequency, and the horizontal width (pixel number) or horizontal line number (vertical width (pixel number) of the output signal of the CCD 9 at that time. )) Is detected, and in this embodiment, the number of pixels in both the horizontal and vertical directions is identified in order to improve the detection accuracy.

When the CCD 9 is driven, "full surface" white "" is the best subject, but the maximum value is detected in the first embodiment, so the present invention is not limited to this. Further, in the case of an "entire surface" white "subject, for example, in an electronic endoscope apparatus configured to perform white balance adjustment at the time of use, the operation can be performed at the same time.

A specific configuration of the pixel number automatic detection circuit 40 is shown in FIG.

Here, in this embodiment, as shown in FIG.
A case will be described in which there are CCDs (three electronic scopes having CCDs) having different numbers of pixels 9A, 9B, and 9C (9A <9B <9C).

As shown in FIG. 2, the video signal V passed through the LPF 26 is
Reference voltage level V applied to one (non-inverting) input terminal of the comparator 41 and applied to the other input terminal of the comparator 41
Compared with _REF , the input video signal V is converted into a TTL level or the like that can be easily processed in the subsequent stage. (Note that the pulse width is the same as the input video signal.) The pulse-shaped signal whose waveform has been shaped by this comparator 41 is applied to the count enable terminal of the horizontal counter 42 and the count enable terminal of the vertical counter 44 via the integrating circuit 43. While the pulse signal is "1", the clock Cf having the frequency f and the horizontal synchronizing signal HD 'applied to the clock input terminal are counted, and the counted value is output from the output terminal.

A horizontal synchronizing signal HD is applied to the reset terminal by the timing shown in FIG. 4 (A), and the horizontal counter 42 counts the clock Cf input during the period between these HDs.

The clock Cf uses, for example, a CCD read signal in this embodiment, but other clock signals such as a sync signal generator are used.
A synchronized clock (for example, subcarrier f = 3.57945 MHz) that meets the condition of the frequency of HD << f generated by 22 may be used. Then, this clock Cf is set to the horizontal counter 42.
Output by counting the pulse width of the video signal V. Similarly, the vertical counter 44 also counts the horizontal synchronizing signal HD ′ by the pulse width in the vertical direction of the video signal during the period from resetting to the next resetting by the vertical synchronizing signal VD applied to the reset terminal. The count output, that is, the number of H lines in the vertical direction is detected. Note that the integration circuit 43 in the preceding stage of the vertical counter 44 has a time constant of integration of about 1H, and if a video signal exists within each horizontal period, it is connected beyond the horizontal period (at the "1" level). It becomes a video signal and is used as a pulse for detecting the number of H lines.

The horizontal synchronizing signal HD 'is set near the center of the minimum number of pixels in the horizontal direction. (This setting is to ensure reliable detection in order to operate the electronic scope 2 so that the observed subject is generally displayed in the center of the screen, but this is not always the case. However, the count outputs of the horizontal and vertical counters 42 and 44 are respectively a pair of horizontal digital comparators 45 and 4, respectively.
It is input to 6 and a pair of vertical digital comparators 47 and 48, and it is determined which one of the pixel numbers 9A, 9B and 9C shown in FIG.

The digital values applied to the reference input terminals of the comparators 43, 44 and 45, 46 are set as follows for AH, BH and AV, BV.

(1) AH and AV: Horizontal and vertical set values that are larger than the minimum number of pixels 9A (horizontal and vertical values thereof) and up to the next number of pixels 9B.

(2) BH and BV: Horizontal and vertical set values that are larger than the number of pixels 9B and are up to the number of pixels 9C.

The output terminals of the horizontal digital comparators 45 and 46 are
The outputs x1 and x2 of the comparators 45 and 46 are x1> connected to the input terminals of the flip-flops (FF) 51 and 52, respectively, and hold the output values of the comparators 45 and 46 and read them out multiple times (for CCD). It is determined that AH or x2> BH will occur even once, that is, the value of x1> AH or x2> BH is preferentially taken in.

By providing the flip-flops 45 and 46, means for reducing the light distribution characteristic and reducing an error due to reading at a low temperature are provided.

In the horizontal direction, the number of pixels is determined using flip-flops 45 and 46, but in the vertical direction, the number of pixels is determined using vertical digital comparators 47 and 48 (without using flip-flops). I do.
That is, the output y1 of the comparator 47 determines whether y1> AV, and the output y2 of the comparator 48 determines whether y2> BV.

The output of the flip-flop 51 and the output of the comparator 47 are selected by the OR circuit 53 so that the value of the number of pixels determined to be the largest in the horizontal and vertical directions is prioritized, and the light distribution is narrow also by this means. Even if the illuminance is low, the detection error is reduced.

Similarly, the output of the flip-flop 52 and the comparator
The output of 48 is also determined by the OR circuit 54 so that the value of the number of pixels determined to be the largest is prioritized with respect to the pixel number determination results in the horizontal and vertical directions.

FIG. 4A shows the relationship between the signal input to the horizontal counter 42 and the horizontal synchronizing signals HD and HD 'when the number of pixels is three.

In the case of the minimum number of pixels 9A, the count value NA counted by the horizontal counter 42 is smaller than the set value AH (of course smaller than BH). That is, NA <AH, NA <BH, and the outputs of the comparators 45 and 46 are “0” and “0”. Also, the number of pixels
In the case of 9B, the count value counted by the horizontal counter 42
NB is larger than the set value AH and smaller than the set value BH. That is, NB> AH, NB <BH, and the comparators 45,46
Output is "0", "1".

Similarly, when the number of pixels is 9C, the count value of the horizontal counter 42
NC becomes larger than both set values AH and BH. That is, the outputs of the comparators 45 and 46 are "1" and "1".

Incidentally, FIG. 4 (a) also shows (for easy understanding) a horizontal synchronizing signal HD 'set near the center of the minimum pixel number 9A.

On the other hand, FIG. 4 (B) shows that the number of pixels can be similarly determined in the vertical direction as well, and the number of pixels can be determined in the same manner as described in FIG. 4 (A). The description is omitted. (That is, comparator 47,4
8, when the number of pixels is 9A, 9B, 9C, "0", "0";
“1”, “0”; “1”, “1” is output.

Therefore, when the number of pixels is 9A, 9B, 9C, the output of the OR circuits 53, 54 outputs "0", "0";"1","0";"1","1". . Therefore, when the number of pixels differs depending on the outputs of the two OR circuits 53 and 54, it is used as a switching signal for switching a portion that needs to be switched to a characteristic suitable for the number of pixels. Instead of the integrating circuit 43 in FIG. 2, a retrigger type monostable multivibrator may be used to change the video signal into a continuous signal over a 1H period. (Of course, it becomes 0 after the video signal is not output.) By the way, in this embodiment, even if the number of pixels is different, CC
The clock frequency of the drive signal to D9 is the same, and the signals are read with the same clock. With this drive signal, the signal read from the CCD 9 is double-sampled by the double sampling circuit 25 by the pulse of the clamp pulse / sampling pulse generating circuit 56 and output. This is shown in FIG.

The CCD drive circuit 21 includes a reset pulse as shown in FIG. 5 (a) and a horizontal transfer pulse φH1 as shown in FIG. 5 (b).
Etc. and outputs the CCD output signal as shown in FIG.
Output from 9. On the other hand, the waveform generating circuit which receives the clock from the synchronizing signal generator 22 and forms the clamp pulse / sampling pulse generating circuit 56 outputs the clamp pulse and the sampling pulse as shown in FIGS. 5 (d) and 5 (e). To do.

That is, using the reset pulse and the horizontal transfer pulse
The output signal read from the CCD 9 has a reset pulse portion and a feed-through portion mixed in the signal portion as shown in FIG. 5 (c). Therefore, a clamp pulse slightly delayed in phase from the reset pulse and a sampling pulse synchronized with a signal portion further delayed in phase from this clamp pulse are generated, and these clamp pulses and sampling pulses are applied to the double sampling circuit 25. S / N by removing noise components such as reset pulse
Has been improved.

The clock shown in FIG. 5 (b) is divided by a frequency divider or the like to generate a vertical transfer pulse.

Then, the double sampling circuit 25, LPF26,
R, G, B memory via γ correction circuit 27, A / D converter 28, etc.
It is written in 29R, 29G, 29B. This R, G, B memory 29R, 29G,
29B is controlled by the memory control circuit 34, and the memory control circuit 34 changes the frequency of the read clock according to the number of pixels at the time of reading by the output signal of the pixel number automatic detection circuit 40. Then, these R, G, B memories 29R, 29
G and 29B are read out at the same time, converted into analog signals by the D / A converter D31, and unnecessary harmonics are removed by the low-pass filters 32, respectively. Each low pass filter 32 has a structure as shown in FIG. The signal input from the input terminal through the D / A converter 31 passes through the buffer amplifier 61 and then the first, second and third low pass filters 62a, 62b, 62b connected to the resistors Ra, Rb, Rc, respectively. Input to 62c. The output ends of the low-pass filters 62a, 62b, 62c are grounded via the matching resistors Ra, Rb, Rc, and are connected to the contacts 63a, 63b, 63c of the analog switch 63. The contacts 63a, 63b, 63c of the analog switch 63 are electrically connected to the switching contact 63d by the switching signal of the pixel number automatic detection circuit 40,
The signal is led to the next stage via the buffer amplifier 64.

The first, second, and third low-pass filters 62a, 62b, 62c
According to the method, unnecessary frequencies are removed by cutting off a frequency higher than a highest frequency component included in a signal determined by a driving pulse used for reading out according to a sampling theorem.

The switching signal output from the pixel number detection circuit 40 is input to the memory control circuits 34R, 34G, 34B shown in FIG. 7 and written in the R, G, B memories 29R, 29G, 29B, respectively. The data read timing is switched to one that corresponds to the number of pixels. Although FIG. 7 illustrates the memory control circuit 34R for controlling the R memory 29R, for example, other memory 29
The configurations of G and 29B and the memory control circuits 34G and 34B for controlling them have the same configuration.

The master clock of the reference clock generator in the synchronizing signal generator 22 forms the R memory control circuit 34R.
While being input to the read pulse generators 71a, 71b, 71c,
It is input to the write pulse generator 72 and the write / read control circuit 73.

The first, second, and third read pulse generators 71a, 71b, 71c
Generates a read pulse corresponding to the number of pixels and is input to the read pulse switching circuit 74, respectively. The read pulse switching circuit 74 selects the read pulse to be output according to the switching signal from the pixel number automatic detection circuit 40, and the selected read pulse is input to the read / write switching circuit 75. The read / write switching circuit 75 has two digital input terminals and two digital output terminals (each having a plurality of bits), and a read pulse switching circuit 74 is provided by an output signal of the write / read control circuit 73.
Side read pulse and write pulse generator
The write pulse input from the 72 side is switched from two output terminals so that it can be output. For example, when the signal data captured under the R illumination is input via the A / D converter 28, the signal data is input to the R first memory, for example.
As written in 77a, a write pulse from the write pulse generator 72 (for example, a write mode signal is applied from the write / read control circuit 73) is applied to the address end of the R first memory 77a. . In this state, the other R second memory 77b has the read pulse switching circuit 74
The read pulse from the read pulse generator 71i (i = a, b, or c) selected in step 7 can be applied, the read pulse is applied at a predetermined timing, and the (R first memory 77a writes In the read mode during the mode)
The written signal data is read. Each memory 77a, 77b
Is composed of IC such as dynamic RAM or static RAM.

Output selection circuits 78a and 78b are provided at the data output terminals of the R-first and R-second memories 77a and 77b, respectively.
Off is controlled. These output selection circuits 78a and 78b are turned on in the read mode after being set to the write mode, and the read signal data is output to the D / A converter 31 side of the next stage via the output selection circuit 78a or 78b. .

The R first and second memories 77a and 77b have a memory capacity that does not become insufficient even in the case of the maximum number of pixels, and a part of the memory capacity is used in the case of a small number of pixels.

The write pulse generator 72 is common to the G memory and B memory control circuits 34G and 34B.
It may be switched and used via a multiplexer or the like according to the writing to R, 29G, 29B.

Since each memory 29I (I = R, G, B) has a pair of memories as described above, the write operation and the read operation can be performed independently.

Since the read mode is simultaneously performed for the R, G, B memories 29R, 29G, 29B, the read pulse generator 71a,
Instead of providing three sets of 71b, 71c and the read pulse switching circuit 74, one may be used in common.

The signal data simultaneously read from each of the memories 29R, 29G, and 29B is converted into an analog signal by the D / A converter 31 whose conversion clock frequency is controlled by the memory control circuit 34, and is input to the LPF 32 to correspond to the number of pixels. Band control is performed in each of the above bands, and each band is input to the horizontal contour correction circuit 33. Each horizontal contour correction circuit 33 is also adapted to perform a proper contour correction according to the number of pixels, and its configuration is shown in FIG. The signal input from the input terminal through the LPF 32 is delayed by the first delay line 81 by, for example, Ta, and then the second delay line 82.
But it is delayed by Ta. Therefore, if the signal applied to the input terminal is, for example, that shown in FIG.
The signals passed through 2 are as shown in FIGS. As the delay lines 81 and 82, those having taps are used, and each tap is connected to a contact point of the analog switches 83 and 84, respectively, and both analog switches 83 and 84 switch the pixel number automatic detection circuit 40. A signal is applied and the tap selected by using this switching signal as a control signal is determined.
The tap selected by this control signal, that is, the delay amount is set in advance to an appropriate value according to the number of pixels.

The signal input from the input terminal and the signal delayed by the second delay line 82 are added by the first adder 85 to be a signal shown in FIG. 9 (d), which is -1 / The signal shown in (e) of the figure is passed through the coefficient unit 86 for setting to 2, and then input to the second adder 87. This adder 87 has a first delay line
Signals are also input via 81, and these are added to form a signal shown in FIG. 9 (f), and this signal is input to the third adder 89 via the variable resistors 88 for adjusting respective correction amounts. The signals that have passed through the first delay line 81 are also input to this adder 89, and these are added to form a signal whose horizontal contour has been corrected as shown in FIG. 9 (g), from the output end to the next stage side. Is output.

Instead of the tap-type delay lines 81 and 82 used for the above-mentioned delay, a delay-type variable resistance may be used by a voltage.

In the first embodiment described above, the number of pixels is different from three, but two or four or more pixels can be similarly configured. In the case of a larger number of different pixels, each of the two digital comparators 45, 46 and 47, 48 in FIG. 2 is three or more (when detecting only one, three comparators of only one are used. Above).

By the way, in the above-mentioned first embodiment, the one in which the electronic scope of the frame-sequential imaging system can be mounted and used is explained, but the present invention is a system with a built-in filter in which a mosaic filter or the like is arranged in front of the imaging surface of the CCD 9 under white illumination. The same can be applied to the electronic scopes having different numbers of pixels.
In this case, the read drive signal is once stored in the memory when the clock having the same frequency is used even when the number of pixels is different. On the other hand, when the memory is not used, it is desirable to change the drive frequency according to the number of pixels to obtain a predetermined video signal.

In the first embodiment, the CCD read frequency is constant (same) even when the number of pixels is different, but the present invention is not limited to this, and the previous application by the present applicant ( As described in Japanese Patent Application No. 62-17982), the readout frequency of the CCD may be changed according to the number of pixels.

Further, in the above-described embodiment, when it is not necessary to adjust the horizontal contour or the like, the switching depending on the number of pixels may be omitted, or the provision of the contour correction circuit may be omitted. Also, LP
Also for F32, if the deterioration of image quality is not large, it is possible to cut off at a fixed frequency.

Further, a means for automatically detecting which of the frame-sequential type electronic scope and the electronic scope using a mosaic filter is connected is provided, and by this means, signal processing suitable for the connected electronic scope can be performed. It is also possible to switch a part of the signal processing unit so that it can be dealt with. This is, for example, using a light source that can switch between frame-sequential light and white light and output it. First, a "white" subject is imaged under frame-sequential illumination light, and the video signal output at that time is for a 1H period. If the “O” level is regularly set in the area, it is determined that the electronic scope uses a mosaic filter. Further, in the case of continuous video signals, it can be determined that the electronic scope is a frame sequential type electronic scope. (In the case of a striped filter array, it is necessary to detect the levels in adjacent horizontal periods, but it is possible to detect it in the same manner.) Whether or not the mosaic filter is built-in is determined at the same time as the automatic pixel number detection. You may do it.

The present invention can also be applied to an endoscope apparatus in which a TV camera having a solid-state imaging device such as a CCD is externally attached to the eyepiece of an optical endoscope having an image guide.

[Effects of the Invention] As described above, according to the present invention, the automatic detection means for the number of pixels of the solid-state image pickup device in the endoscope using the solid-state image pickup device as the image pickup means is provided. In the case of, it can be used in common without requiring a switching operation or the like.

[Brief description of drawings]

1 to 9 relate to one embodiment of the present invention. FIG. 1 is a block diagram showing the configuration of one embodiment, FIG. 2 is a configuration diagram of an automatic pixel number detection circuit, and FIG. 3 is a CCD. FIG. 4 is an explanatory view showing that there are three kinds of pixel numbers, FIG. 4 is an operation explanatory diagram of the pixel number automatic detection circuit, FIG. 5 is a timing chart diagram for explaining the operation of the double sampling circuit, and FIG. 6 is a low pass filter. FIG. 7 is a block diagram showing the configuration of the memory control circuit, FIG. 8 is a configuration diagram of the horizontal contour correction circuit, and FIG. 9 is a waveform diagram for explaining the operation of FIG. 1 ... Electronic endoscope device, 2 ... Electronic scope 3 ... Light source unit, 4 ... Signal processing unit 6 ... Main device 21 ... CCD drive circuit 25 ... Double sampling circuit 26 ... Low-pass filter 28 ... … A / D converter 29R, 29G, 29B …… Memory 31 …… D / A converter 32 …… Low pass filter 33 …… Horizontal contour circuit 40 …… Pixel number automatic detection circuit 42,44 …… Counter 45,46,47 , 48 …… Digital comparator 51,52 …… Flip-flop 53,54 …… OR circuit

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Masahiko Sasaki 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (72) Inventor Jun Hasegawa 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (72) Inventor Katsuyoshi Sasakawa 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (72) Shinji Yamashita 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd. (56) Reference JP-A-61-61583 (JP, A) JP-A-61-179129 (JP, A)

Claims (1)

(57) [Claims] 1. An electronic endoscope in which a solid-state image pickup device having a different number of pixels is used as an image pickup device, and an output signal of the image pickup device can be processed by a signal processing device to be displayed on a monitor device. In the endoscope device, the solid-state imaging device is driven by the same clock frequency, and a detection means for specifying the number of pixels from the width of the output signal is provided, and the number of pixels in the signal processing device is controlled by the detection means. An electronic endoscope apparatus characterized by performing signal processing according to the above.