JP3411673B2 - Video signal processing device for electronic endoscope - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-dimensional pixel interpolation for a video signal output from a solid-state image pickup device built in the end of an insertion portion of an endoscope. The present invention relates to a video signal processing device of an electronic endoscope for performing. 2. Description of the Related Art In a so-called electronic endoscope using a solid-state image sensor for transmitting an observation image, illumination light for each of the three primary colors is used so that a small solid-state image sensor can secure as many pixels as possible. The image processing of the so-called RGB plane sequential system, in which image signals are transmitted in a time-division manner and sequentially transmitted, is widely used. However, in order to minimize the pain given to the patient to be examined, it is desirable for the endoscope to make the thickness of the insertion portion as small as possible. Therefore, the size of the solid-state imaging device incorporated at the distal end of the insertion portion must be reduced as much as possible, so that the number of pixels cannot be increased much. As a result, the image projected on the monitor screen has a noticeable roughness, and a high-resolution image with high resolution cannot be obtained. Therefore, the number of pixels of the image projected on the monitor screen is determined by using the pixel interpolation technique. It is possible to increase. However, since a field memory having only one output terminal is generally used as a memory for storing a video signal of an electronic endoscope, one of the horizontal scanning periods is required to perform vertical interpolation. It is necessary to connect a delay circuit for delaying by a period, which complicates the circuit. Conventionally, as shown in FIG. 8, for example, as shown in FIG. 8, a multi-port memory 51 having a plurality of output ports is used as a memory for temporarily storing video signals, from which data of a plurality of lines are simultaneously read. The output is serial, and two-dimensional pixel interpolation is performed downstream of the memory. Reference numerals 52 to 55 denote flip-flops and arithmetic circuits (AVE) for performing pixel interpolation in the vertical direction,
56 and 57 are flip-flops and arithmetic circuits for performing horizontal pixel interpolation. However, in the above-described conventional video signal processing apparatus for an electronic endoscope, two-dimensional interpolation is performed only on the subsequent stage from the memory.
When two-dimensional interpolation is performed on video signals of three colors (red), G (green), and B (blue), three sets of interpolation circuits as shown in FIG. 8 must be added. There is a disadvantage that it becomes very large. Therefore, the present invention provides a video signal processing apparatus for an electronic endoscope which can perform two-dimensional pixel interpolation with a simple circuit and can obtain an easy-to-see screen with less noticeable roughness on a monitor screen. The purpose is to provide. In order to achieve the above object, a video signal processing apparatus for an electronic endoscope according to the present invention comprises:
In the video signal processing device for an electronic endoscope, wherein the color video signals are simultaneously read out from the memories for separately and temporarily storing the digital video signals of G and B to obtain a color video, A multi-port memory having a plurality of output ports is used as a memory, and a horizontal interpolation circuit for performing horizontal pixel interpolation on the screen is interposed at a stage preceding the memory, and a vertical interpolation circuit for performing vertical pixel interpolation on the screen is used. An interpolation circuit is interposed at a stage subsequent to the memory. When the R, G, and B color video signals are signals obtained by plane-sequential imaging sequentially captured with a time lag, the color video signals are sent to the memories via a common horizontal interpolation circuit. You should be able to. Embodiments will be described with reference to the drawings. In FIG. 3, reference numeral 1 denotes an electronic endoscope, and reference numeral 10 denotes a video processor which also serves as a light source device. At the tip of the insertion portion of the electronic endoscope 1, for example, C
A solid-state imaging device 2 composed of a CD (Charge Coupled Device) is arranged, an observation image is taken here, and an imaging signal is sent to a video processor 10. Reference numeral 3 denotes a connector for transferring the imaging signal and the drive signal of the solid-state imaging device 2 between the electronic endoscope 1 and the video processor 10. The entrance end of the light guide fiber bundle 4 for illuminating the observation field is connected to a light source section of a video processor 10, and illumination light is supplied from a light source lamp 11. Between the light source lamp 11 and the entrance end of the light guide fiber bundle 4, R (red), G (green), B
A filter disk 12 in which color filters of three colors (blue) are sequentially interposed in the illumination light path is rotated at a constant rotation speed. Accordingly, the observation visual field is sequentially illuminated with each of the three monochromatic lights of R, G, and B, and the solid-state imaging device 2 outputs the imaging signals of each color in order with a time lag.
The G and B planes are sequentially imaged. The signal processor of the video processor 10 has a C for generating a drive signal to be sent to the solid-state imaging device 2.
A CD driver circuit 14 and a CCD process circuit 15 for extracting a video signal from an image signal sent from the solid-state image sensor 2 are provided. The video signal extracted by the CCD process circuit 15 is converted into a digital signal by an analog-to-digital conversion circuit 16 and sent to a memory unit 20. In the memory unit 20, the three color video signals are temporarily stored separately, read out at the same time, converted into analog signals by the digital / analog conversion circuit 17, and then sent to the video processing circuit 18. In the video processing circuit 18, a video signal is generated from the video signal, and the video signal is sent to the monitor 5, and an image observed by the endoscope is displayed on the monitor screen. Reference numeral 19 denotes a timing generator for synchronizing the processing of the video signal and the driving of the solid-state imaging device 2. FIG. 1 and FIG. 2 show a part of the circuit configuration in the memory section 20. Here, an example is shown in which interpolation is performed to enlarge the video signal data twice in the horizontal direction and the vertical direction, but the data expansion rate of the interpolation may be other values. Assuming that the solid-state image pickup device 2 has X pixels in the horizontal direction and Y pixels in the vertical direction, data D ¹ output from the solid-state image pickup device 2 is shown as a matrix in FIG.
As shown in FIG. 5 and D ¹ = {A ¹ x, B ¹ x, C ¹ x,..., P ¹ x,..., Y ¹ x} ^T (P ¹ x = {p1, p2, p3, …, Pl, pm,…, px}). As shown in FIG. 1, three multi-port memories 21 (21R, 21G, 21B) are provided for the R, G, and B color video signals.
The video signal output from the analog-to-digital conversion circuit 16 is first temporarily stored in a FIFO memory 22 (first-in first-out memory). The data D ¹ output from the FIFO memory 22 is received by the first flip-flop 23 to generate data D ¹ ′ at an appropriate timing, and these D ¹ and D ¹ ′ are processed by the arithmetic circuit 24. Calculate in the horizontal direction (X direction)
For example, data D ^{2 corresponding} to data D ¹ as shown in FIG. 6 is created, and is written to the multi-port memory 21 via the second flip-flop 25. The illustration of the clock, the control signal, and the circuit for producing them are omitted. The calculation method is the arithmetic circuit 24 having two input terminals, any line ^{P 1 x = {p1, p2} , p3 of the output data D ¹ of the FIFO memory 22, ..., pl, pm, ..., px} and this is delayed by one clock in the first flip-flop 23
P ¹ x ′ is input, and a line (AVE line) obtained by averaging each pixel is output. Then, the AVE line is controlled by a second flip-flop 25 by a control signal.
As shown in (1), the data is inserted between p1 and pm and written into the multiport memory 21. That is, while the pixels are interpolated in the horizontal direction,
The data amount per line increases to 2X-1. Assuming that the data written in this memory is D ² , D ² = {A ² x, B ² x, C ² x, ..., P ² x, Q ² x, ..., Y ² x} ^T (P ² x = {p1, (p1 + p2) / 2, p2, (p2 + p3) / 2,…, pl, (pl + pm) / 2, p
m,…, px}). When pixel interpolation is not performed, the FIF
The output data D ¹ from the O memory 22 is directly written to the multiport memory 21 via the third flip-flop 26. When the video signal is picked up by the RGB frame sequential method as in this embodiment, the video signals of the three colors R, G and B are sent in order, so that the same interpolation circuits 22 to
25 is output to the three-color multiport memory 21R, 2R.
What is necessary is just to make it input to 1G and 21B in order. Therefore,
Horizontal pixel interpolation of R, G, and B three-color video signals can be performed by a set of interpolation circuits 22 to 25. Each multi-port memory 21 has a RAM
It has two output terminals, a (random access memory) output terminal and a SAM (serial access memory) output terminal. FIG. 2 shows a vertical pixel interpolation circuit connected to the output terminal of the multiport memory 21R for R among the three multiport memories 21. The multiport memory 21G for G, The same interpolation circuit is also provided at the output terminal of the multiport memory 21B for B. In the circuit shown in FIG. 2, first, appropriate two horizontal lines of data are serially output from the two output terminals of the multiport memory 21 and are output to the arithmetic circuit 27.
Creating data D ³ as shown in FIG. 7, for example by calculating the vertical direction in the outputs to the digital-analog conversion circuit 17 via the fourth flip-flop 28. Clocks, control signals, and circuits for producing them are not shown. When the vertical pixel interpolation is not performed, the data output from the multiport memory 21 is set to RA.
Going only from the M port, the fifth flip-flop 29
Is output to the digital-to-analog conversion circuit 17 via the RAM, and when interpolation is performed, data necessary for performing the interpolation is stored in the RAM.
And SAM output independently from both ports. The calculation here is performed by the multiport memory 21
For any line P ² x outputted from the RAM port, is inputted one line shifted Q ² x both lines by output from the SAM port to the arithmetic circuit 27, taking the average for each pixel, which is A vertical AVE line P ³ x is obtained. [0034] When the output data of the interpolation circuit and ^{D 3, D 3 = {A} 3 x, B 3 x, C 3 x, ..., P 3 x, Q 3 x, ..., (Y-1) 3 x } ^T P ³ x = {(p1 + q1) / 2, (p1 + p2 + q1 + q2) / 4, (p2 + q2) / 2,…, (pl + ql) / 2, (pl + pm + ql + qm) / 4, (pm + qm) / 2,…, (px + qx) / 2} Q ³ x = {(q1 + r1) / 2, (q1 + q2 + r1 + r2) / 4, (q2 + r2) / 2,…, (ql + rl) / 2, (q1 + qm + r1 + rm) / 4, (qm + rm) / 2,…, (qx + rx) / 2} . By controlling the control signal of the flip-flop of the interpolation circuit, it is easy to switch the output to the monitor such as the so-called enlarged one-screen mode and the parent-child two-screen mode as well as the normal one-screen mode. According to the present invention, a horizontal interpolation circuit for performing pixel interpolation in the horizontal direction is inserted before the memory, and a vertical interpolation circuit for performing pixel interpolation in the vertical direction is inserted after the memory. Since the horizontal interpolation circuit can be shared by the video signals of each color, the two-dimensional pixel interpolation can be performed using a small-capacity memory with a simple circuit, and coarse interpolation can be performed on the monitor screen. It is possible to obtain an easy-to-see screen that is inconspicuous.

[Brief description of the drawings] FIG. 1 is a block diagram of a horizontal interpolation circuit according to an embodiment. FIG. 2 is a block diagram of a vertical interpolation circuit according to the embodiment. FIG. 3 is a block diagram showing the overall configuration of the embodiment. FIG. 4 is an explanatory diagram of a matrix according to the embodiment. FIG. 5 is an explanatory diagram of a matrix according to the embodiment. FIG. 6 is an explanatory diagram of a horizontal interpolation calculation according to the embodiment. FIG. 7 is an explanatory diagram of a vertical interpolation calculation according to the embodiment. FIG. 8 is a block diagram of a conventional interpolation circuit. [Explanation of symbols] 21 Multi-port memory 22-25 horizontal interpolation circuit 27,28 vertical interpolation circuit

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Claims (1)

(57) [Claims] [Claim 1] The order of planes sequentially imaged with a time offset from each other
A video signal of an electronic endoscope in which color video signals are simultaneously read out from respective memories for separately and temporarily storing R, G, and B three-color digital video signals by the next imaging to obtain a color video. In the processing device, a multi-port memory having a plurality of output ports is used as the memory, and a horizontal interpolation circuit for performing pixel interpolation in a horizontal direction of a screen is interposed at a stage preceding the memory.
Then, each of the color video signals passes through a common horizontal interpolation circuit,
A video signal processing apparatus for an electronic endoscope, wherein a vertical interpolation circuit for performing pixel interpolation in a vertical direction of a screen is interposed at a stage subsequent to the memory, while being sent to each memory .