JPS63254766A - Charge transfer device - Google Patents

Charge transfer device

Info

Publication number
JPS63254766A
JPS63254766A JP62088659A JP8865987A JPS63254766A JP S63254766 A JPS63254766 A JP S63254766A JP 62088659 A JP62088659 A JP 62088659A JP 8865987 A JP8865987 A JP 8865987A JP S63254766 A JPS63254766 A JP S63254766A
Authority
JP
Japan
Prior art keywords
polysilicon
layer
horizontal
transfer
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62088659A
Other languages
Japanese (ja)
Other versions
JPH07120775B2 (en
Inventor
Hideki Muto
秀樹 武藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP62088659A priority Critical patent/JPH07120775B2/en
Publication of JPS63254766A publication Critical patent/JPS63254766A/en
Publication of JPH07120775B2 publication Critical patent/JPH07120775B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14831Area CCD imagers

Abstract

PURPOSE:To prevent the decrease in transfer efficiency even if many picture elements are provided, by forming a horizontal transfer part with polysilicon in a three-layered structure, and constituting horizontal transfer electrodes with the polysilicon layers of a first layer and a second layer. CONSTITUTION:A third polysilicon layer, which constitutes a gate electrode 11, is arranged so as to cross first and second polysilicon layers at the approximately central parts in the vertical direction. The first and second polysilicon layers are divided into two parts in the upper and lower directions. Holes are provided at the parts of the first and second polysilicon layers, which correspond to every other vertical CCDs of, e.g., vertical transfer parts 2, in the crossing regions. The third polysilicon layer is arranged on a substrate. In the hole regions, differences are provided in depth of the potential wells of the holes. A barrier region 16 is formed in this way. The transfer efficiency of the horizontal CCD is not effected even if dispersion in machining of the third polysilicon layer becomes large.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は電荷転送素子に関し、特に多線読み出しされる
電荷転送素子に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a charge transfer device, and more particularly to a charge transfer device that is read out in multiple lines.

(従来技術) 電荷転送素子は、その技術発展の方向の一つとして高解
像力を得るための多画素化があり、最近では4部万画素
クラスのものも開発されている。
(Prior Art) One of the directions of technological development of charge transfer devices is increasing the number of pixels in order to obtain high resolution, and recently, charge transfer devices with 40,000 pixels have been developed.

このような素子の多画素化に伴って微細加工性および高
速動作特性は一層要求されている。この解決策として、
ゲート電極を介して互いに並置接続した複数本の水平C
ODを用いて特性を向上させ九多線読み出し形素子が提
案されている。
With the increase in the number of pixels in such devices, fine processing performance and high-speed operation characteristics are increasingly required. As a solution to this
Multiple horizontal Cs connected in parallel to each other via gate electrodes
A nine-point readout type element has been proposed whose characteristics are improved using OD.

例えば、第4図は、2本の垂直CODに対応して1段を
構成する水平〇0Dを2本並列に配置し、隣り合う垂直
CODからの信号電荷を2本の水平CODに振り合けて
転送する場合を示している。
For example, in Figure 4, two horizontal 〇0Ds forming one stage are arranged in parallel corresponding to two vertical CODs, and the signal charges from adjacent vertical CODs are distributed to the two horizontal CODs. This shows the case where the data is transferred using

処で、このような多線読み出し形素子において、その水
平転送部における従来構造は、3層ポリシリコン構造を
とり、1層目のポリシリコンを水平0(3部間のゲート
電極に、2層目および3層目のポリシリコンを水平ca
p転送電極にそれぞれ用いていた。
However, in such a multi-line readout element, the conventional structure of the horizontal transfer section is a three-layer polysilicon structure, and the first layer of polysilicon is horizontally zero (the gate electrode between the three sections has a two-layer polysilicon structure). The eyes and third layer of polysilicon are horizontally ca.
Each was used as a p-transfer electrode.

(発明が解決しようとする問題点) しかしながら、一般に、ポリシリコンの加工ばらつきは
、1層目より2層目が、2層目より3層目が大きい傾向
にある。従って、前述した従来構造では、3層目のポリ
シリコンの加工ばらつきが大きくなり、その結果、水平
CODの転送効率を下げる等の欠点を有していた。
(Problems to be Solved by the Invention) However, in general, processing variations in polysilicon tend to be larger in the second layer than in the first layer, and larger in the third layer than in the second layer. Therefore, in the conventional structure described above, processing variations in the third layer of polysilicon become large, resulting in a drawback that the horizontal COD transfer efficiency is reduced.

本発明の目的は、上記欠点に鑑みてなされたもので、5
層目のポリシリコンの加工ばらつきが大きくなっても、
水平CODの転送効率に影響を及ぼさない電荷転送素子
を提供することにある。
The object of the present invention has been made in view of the above-mentioned drawbacks, and has five objects.
Even if the processing variations in the polysilicon layer become large,
An object of the present invention is to provide a charge transfer element that does not affect horizontal COD transfer efficiency.

c問題点を解決する念めの手段および作用)すなわち、
本発明の上記目的は、マトリクス状に配置された光電変
換素子の信号を、ゲート電極を介して互いに並置接続し
た少なくとも2本以上の水平CODからなる水平転送部
に振り分けて読み出す電荷転送素子において、前記水平
CODの転送電極を形成する第1層目及び第2層目のポ
リシリコンと、前記2つのポリシリコンと交差して前記
ゲート電極を形成する第3層目のポリシリコンとを有し
、前記交差する領域の前記第1層目及び第2層目のポリ
シリコンの1部が開孔されて前記第3層目のポリシリコ
ンを半導体基板上に配置しており、かつ前記開孔領域下
のポテンシャル井戸の深さが異ってバリア領域が形成さ
れていることを特徴とする電荷転送素子により達成され
る。
(c) precautionary means and actions to solve problems), i.e.
The above object of the present invention is to provide a charge transfer element that distributes and reads out signals from photoelectric conversion elements arranged in a matrix to a horizontal transfer section consisting of at least two horizontal CODs connected in parallel to each other via gate electrodes. a first layer of polysilicon and a second layer of polysilicon that form transfer electrodes of the horizontal COD, and a third layer of polysilicon that intersects with the two polysilicon layers to form the gate electrode; A portion of the first and second layer polysilicon in the intersecting region is opened so that the third layer polysilicon is placed on the semiconductor substrate, and a portion under the opening region is opened. This is achieved by a charge transfer element characterized in that barrier regions are formed with potential wells having different depths.

このように第1層目及び第2層目のポリシリコンで水平
caDを形成することにより、加工ばらつきの少ない転
送電極が設けられ、多画素化しても転送効率を低下させ
ない。また、前記開口領域におけるゲート電極下の埋め
込みチャネルにバリア領域が形成されることにより、1
つの水平CODに供給された信号は前記ゲート電極の制
御により別の水平CCDに転送された後、前記1つの水
平CCDに戻ることなく水平転送される。
By forming the horizontal caD using the first and second layers of polysilicon in this way, transfer electrodes with less processing variation can be provided, and the transfer efficiency will not decrease even when the number of pixels is increased. Furthermore, by forming a barrier region in the buried channel under the gate electrode in the opening region, 1
A signal supplied to one horizontal COD is transferred to another horizontal CCD under the control of the gate electrode, and then horizontally transferred without returning to the one horizontal CCD.

(実施例) 以下、本発明の実施例を図面に基づいて詳細に説明する
(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

第1図は本発明による電荷転送素子の1実施例を示す図
であり、本実施列では、互いに並置接続され、2相駆動
される2つの水平aOD(HCaD)を有するインター
ライン転送形00D(工L−0CD)について述べる。
FIG. 1 is a diagram showing one embodiment of a charge transfer device according to the present invention. In this embodiment, an interline transfer type 00D ( (L-0CD) will be described.

この工L−0(!Dは、マトリクス状に配置した複数の
受光素子から成る受光部1と、受光素子の垂直列に対応
した垂直00Dから成る垂直転送部2が配置されており
、この垂直転送部2の出力端にはゲート電極5を通して
水平転送部10が配置されている。
This process L-0(!D) includes a light receiving section 1 consisting of a plurality of light receiving elements arranged in a matrix, and a vertical transfer section 2 consisting of vertical 00D corresponding to the vertical rows of the light receiving elements. A horizontal transfer section 10 is arranged at the output end of the transfer section 2 through a gate electrode 5 .

前記水平転送部10はゲート電極11を介して互いに並
置接続された2つのHOCDl 2.15により構成さ
れており、前記HOOD12.15は2本1組になって
多数配列された水平転送電極14.15によりクロック
信号φAlφBにより2相駆動される。
The horizontal transfer section 10 is composed of two HOCDs 2.15 that are connected in parallel to each other via the gate electrodes 11, and the HOODs 12.15 include a large number of horizontal transfer electrodes 14.15 arranged in sets of two. 15, it is driven in two phases by the clock signal φAlφB.

前記ゲート電極11及び前記水平転送電極14゜15は
3層構造のポリシリコンによって設けられており、1層
目及び2層目のポリシリコンが前記水平転送電極14.
15を、また3層目のポリシリコンが前記ゲート電極1
1をそれぞれ構成している。
The gate electrode 11 and the horizontal transfer electrodes 14 and 15 are made of polysilicon with a three-layer structure, and the first and second layers of polysilicon form the horizontal transfer electrodes 14 and 15, respectively.
15, and the third layer of polysilicon is the gate electrode 1.
1 respectively.

前記ゲート電極11ft:構成する第3層目のポリシリ
コンは、1層目及び2層目のポリシリコンとその垂直方
向の略中央部で交差するように配置され%1層目及び2
層目のポリシリコンを上下方向に2分している。また、
前記交差する領域の第1層目及び第2層目のポリシリコ
ンの1部、本実施列では前記垂直転送部201本おきの
垂直CODに対応し九第1層目及び第2層目のポリシリ
コンが開孔されて、第3層目のポリシリコンが半導体基
板(図示せず)上に配置されるように設けている。
The gate electrode 11ft: The third layer of polysilicon is arranged to intersect with the first and second layers of polysilicon at approximately the center in the vertical direction.
The polysilicon layer is divided into two vertically. Also,
A portion of the first and second layer polysilicon in the intersecting region, in this example column, a portion of the first and second layer polysilicon corresponding to the vertical COD of every 201 vertical transfer sections. A hole is formed in the silicon so that a third layer of polysilicon is placed on a semiconductor substrate (not shown).

また、前記開口領域では、そのポテンシャル井戸の深さ
くポテンシャル・エネルギー)に差異カ設けられてバリ
ア領域16t−形成している。すなわち、この差異は、
第3図から明らかなとおり、前記ゲート電極11により
分割されて形成される下方側HOCD13に面した領域
の不純物濃度を上方側HOOD12に面した領域より高
くして、同一ゲート電圧下でもポテンシャル井戸の深さ
が深くなるようにしである。
Further, in the opening region, a barrier region 16t is formed by providing a difference in depth (potential energy) of the potential well. That is, this difference is
As is clear from FIG. 3, the impurity concentration of the region facing the lower HOCD 13 formed by being divided by the gate electrode 11 is made higher than that of the region facing the upper HOOD 12, so that even under the same gate voltage, the potential well The depth is increased.

なお、前記開口領域間はチャネル・ストップ17にエリ
分離されている。
Note that the opening areas are separated by a channel stop 17.

次に、このように構成された本発明による電荷転送素子
の動作について、第2図及び第3図を参照して説明する
Next, the operation of the charge transfer device according to the present invention configured as described above will be explained with reference to FIGS. 2 and 3.

受光部1に被写体の儂が結像され、被写体の輝度に対応
した電荷が得られると、この電荷は垂直転送部2により
転送され、第1のゲート電極3を介して第1の1110
(!DI 2に送り込まれる。電荷が第10HOOD1
2の埋込みチャネルに送9込まれると同時に■レベルと
なって導通するFICOD間のゲート電極11111(
より、前記第10HOC!D12に供給された電荷の1
部は前記ゲート電極11下に移される。すなわち、前記
第10HOCD12のうち前記開口領域を形成する水平
転送電極151 、15. 、  ・・・下の電荷が移
される。この際、前記開口領域を形成しない水平転送電
極’ s、、 p ’ s!I  ・・・下の電荷はそ
のまま第10TICCD12に留まっている。このとき
のタイミンクは第2図のt=tlに相当し、その様子を
第3図の点線で示す。次いで、前記ゲート電極11がL
レベルに、また前記開口領域を形成する第2のHCOD
l 5の転送電極がRレベルになると2前記間口領域下
に移された電荷は第2のHOCD13へ送り込まれる。
When the image of the subject is formed on the light receiving section 1 and a charge corresponding to the brightness of the subject is obtained, this charge is transferred by the vertical transfer section 2 and transferred to the first 1110 through the first gate electrode 3.
(! is sent to DI 2.The charge is sent to the 10th HOOD1
The gate electrode 11111 (
From the 10th HOC! 1 of the charge supplied to D12
portion is moved below the gate electrode 11. That is, among the tenth HOCDs 12, the horizontal transfer electrodes 151, 15. , ...The charge below is transferred. At this time, the horizontal transfer electrode's,,p's! does not form the opening area. I... The lower charge remains in the 10th TICCD 12 as it is. The timing at this time corresponds to t=tl in FIG. 2, and the situation is shown by the dotted line in FIG. 3. Then, the gate electrode 11 is
a second HCOD on the level and forming the aperture area;
When the transfer electrode 15 becomes R level, the charges transferred under the opening region 2 are sent to the second HOCD 13.

このときのタイミングは第2図の1=1.に相当し、そ
の様子を、第3図の実線で示す。この間、第1のH(I
CDI 2の電荷はそのままでいる。以上のようにして
、2本のHCCDI 2,13に振り分けられた電荷は
、従来どおりの2相駆動法により、それぞれの水平転送
電極14.15によって水平方向に順次転送されて読み
出される。この際、前記ゲート電極11はチャネル障壁
として作用し、かつ前記開口領域にはバリア領域16が
形成され工いるため、それぞれのHOCDl 2,15
に振り分けられた電荷は互いに干渉されず独立に転送で
きる。
The timing at this time is 1=1 in FIG. The situation is shown by the solid line in FIG. During this time, the first H(I
The charge on CDI 2 remains the same. The charges distributed to the two HCCDIs 2 and 13 as described above are sequentially transferred and read out in the horizontal direction by the respective horizontal transfer electrodes 14 and 15 using the conventional two-phase drive method. At this time, since the gate electrode 11 acts as a channel barrier and a barrier region 16 is formed in the opening region, each HOCDl 2, 15
The charges distributed to each other can be transferred independently without interfering with each other.

なお、前記開口領域下の井戸の深さの違いの形成方法と
しては、例えばイオン拡散を2回行うことによシ達せら
れる。すなわち、例えばn型不純物としてム8をイオン
注入するのに% 1回目は開口領域の全域に亘って注入
し、次の2回目は不純物濃度を高くしたい領域、本例で
は下方側の水平CCD13に面し友下部領域にのみイオ
ン注入を行う。
The difference in the depth of the wells under the opening region can be achieved, for example, by performing ion diffusion twice. That is, for example, when ion-implanting Mo8 as an n-type impurity, the first implantation is performed over the entire opening region, and the second implantation is performed in the region where the impurity concentration is desired to be high, in this example, into the horizontal CCD 13 on the lower side. Ion implantation is performed only in the lower part of the facing region.

なお、不純物濃度の絶対値に関しては既に周知の値であ
れば良く、ここでの記載は省略する。
Note that the absolute value of the impurity concentration may be a well-known value and will not be described here.

また、ポテンシャル井戸の深さは上述の不純物濃度の差
異の他に、前記開口領域上の酸化膜厚によって行うこと
もできる。
Further, the depth of the potential well can be determined not only by the difference in impurity concentration described above but also by the thickness of the oxide film on the opening region.

(発明の効果) 以上記載したとおり、本発明の電荷転送素子によれば、
水平転送部が5層構造のポリシリコンにより形成されて
おり、第1層目及び第2層目のポリシリコンで水平転送
電極を構成することによシ。
(Effects of the Invention) As described above, according to the charge transfer device of the present invention,
The horizontal transfer section is formed of polysilicon with a five-layer structure, and the horizontal transfer electrodes are formed from the first and second layers of polysilicon.

加工ばらつきの少ない電極が設けられる。従って、多画
素化した際にも転送効率の低下しない素子が製作できる
An electrode with less processing variation is provided. Therefore, it is possible to manufacture an element whose transfer efficiency does not deteriorate even when the number of pixels is increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の1実施例を示す構成図、第2図は動作
説明する九めのタイミング図、第3図は同じく動作説明
するために挙げたポテンシャル・プロファイル、第4図
は従来の多線読み出し形素子を説明するデバイス構成図
である。 1・・・受光部、2・・・垂直転送部% 6,11・・
・ゲート電極、10・・・水平転送部、12.13・・
・HOCD 。 14.15・・・水平転送電極、16・・・バリア領域
、17・・・チャネル・ストップ
Fig. 1 is a configuration diagram showing one embodiment of the present invention, Fig. 2 is a ninth timing diagram to explain the operation, Fig. 3 is a potential profile also cited to explain the operation, and Fig. 4 is a conventional FIG. 2 is a device configuration diagram illustrating a multi-line readout element. 1... Light receiving section, 2... Vertical transfer section % 6, 11...
・Gate electrode, 10...Horizontal transfer section, 12.13...
・HOCD. 14.15...Horizontal transfer electrode, 16...Barrier region, 17...Channel stop

Claims (1)

【特許請求の範囲】[Claims]  マトリクス状に配置された光電変換素子の信号を、ゲ
ート電極を介して互いに並置接続した少なくとも2本以
上の水平CCDからなる水平転送部に振り分けて読み出
す電荷転送素子において、前記水平CCDの転送電極を
形成する第1層目及び第2層目のポリシリコンと、前記
2つのポリシリコンと交差して前記ゲート電極を形成す
る第3層目のポリシリコンとを有し、前記交差する領域
の前記第1層目及び第2層目のポリシリコンの1部が開
孔されて前記第3層目のポリシリコンを半導体基板上に
配置しており、かつ前記開口領域下のポテンシャル井戸
の深さが異つてバリア領域が形成されていることを特徴
とする電荷転送素子。
In a charge transfer element that distributes and reads out signals from photoelectric conversion elements arranged in a matrix to a horizontal transfer section consisting of at least two horizontal CCDs connected in parallel to each other via gate electrodes, the transfer electrodes of the horizontal CCDs are a third layer of polysilicon that intersects with the two polysilicon layers to form the gate electrode; Parts of the first layer and second layer polysilicon are opened to place the third layer polysilicon on the semiconductor substrate, and the depths of the potential wells under the opening regions are different. A charge transfer device characterized in that a barrier region is formed with a barrier region.
JP62088659A 1987-04-13 1987-04-13 Charge transfer device Expired - Fee Related JPH07120775B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62088659A JPH07120775B2 (en) 1987-04-13 1987-04-13 Charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62088659A JPH07120775B2 (en) 1987-04-13 1987-04-13 Charge transfer device

Publications (2)

Publication Number Publication Date
JPS63254766A true JPS63254766A (en) 1988-10-21
JPH07120775B2 JPH07120775B2 (en) 1995-12-20

Family

ID=13948949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62088659A Expired - Fee Related JPH07120775B2 (en) 1987-04-13 1987-04-13 Charge transfer device

Country Status (1)

Country Link
JP (1) JPH07120775B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5194751A (en) * 1989-07-17 1993-03-16 Sony Corporation Structure of solid-state image sensing devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5194751A (en) * 1989-07-17 1993-03-16 Sony Corporation Structure of solid-state image sensing devices

Also Published As

Publication number Publication date
JPH07120775B2 (en) 1995-12-20

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