JPS6325437B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to memory output reading circuits for reading data from memory. Generally, in order to read data from a semiconductor memory, such as a read-only memory ROM, a sense amplifier detects data led from a memory cell to a data line. However, in the past, the sense (inversion) level margin decreased due to fluctuations in power supply voltage, temperature changes, variations in transistor threshold voltage, etc., making it difficult to obtain stable characteristics under various conditions when reading ROM data. Katta. The present invention was made in view of the above circumstances, and
Worst reference level HMIN of input data,
A reference circuit is provided that can set LMAX arbitrarily, and the reference level from this reference circuit is
By using a circuit configuration that includes a sense amplifier circuit that can set the inversion (sense) level of output data from HMIN and LMAX, it is possible to eliminate variations in the threshold voltage of memory cell transistors, power supply voltage, and temperature when reading data from memory. It is an object of the present invention to provide a memory output reading circuit that can prevent a decrease in the inversion level margin due to fluctuations such as the above, and obtains stable data detection operation characteristics. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In Fig. 1, 1 is a ROM in which a plurality of memory cells are arranged in a matrix and a memory cell is selected by address input, and 2 is a ROM that uses two memory cells identical to the memory cells of ROM1, and uses reference data. This is a reference circuit that sets the potential level of . One of the memory cells of this reference circuit 2 has the lowest potential of the data high level "1".
HMIN and other memory cells output reference data such that the data has a maximum potential LMAX of low level "0". 3 sets the intermediate potential between the reference data levels LMIN and LMAX from the reference circuit 2 as an inversion (sense) level, and uses this inversion level as a reference to set the ROM data read from the ROM1 to the data line DL to "0". This is a sense amplifier that detects whether the signal is present or "1" in synchronization with the clock. That is, as shown in the time chart of FIG. 2, data read from the ROM selected by the address input is input to the sense amplifier 3 via the data line DL.
Sense amplifier 3 reads these signals in synchronization with the clock signal.
Accepts the ROM data, determines the intermediate potential between the reference data levels HMIN and LMAX from the reference circuit 2, sets this as an inverted level, and detects "1" and "0" of the accepted ROM data based on this inverted level. Then, it is sent to the external circuit as ROM output data. FIG. 3 shows a detailed circuit diagram of the reference circuit 2 shown in FIG. In this reference circuit 2, 2 _{1 and} 2 ₂ are reference memory cells each consisting of N data transistors T ₁ to TN connected in series. A precharge transistor Tp whose gate is connected to the drain, a select transistor TS for selecting a memory cell, and the reference memory cell ₂₁ are connected in series between the power supplies V _DD and V _SS . There is.
Similarly, a precharge transistor Tp, a select transistor TS, and the reference memory cell 2 ₂ are connected in series between the power supplies V _DD and V _SS . In the reference memory cells 2 ₁ and 2 ₂ , the gates of the second and subsequent transistors T ₂ to TN are connected to each other, so that the first data transistor T ₁ is turned off and the second and subsequent data transistors T ₂ to TN are turned off. Set to on state. As shown in FIG. 4, the threshold voltage of the data transistors T ₂ to TN of the memory cell 2 ₁ at this time is TH ₁ , the on-resistance thereof is RON ₁ , the threshold voltage of the data transistor T ₁ is TH ₂ , Let the off-resistance be _ROFF2 . Similarly, the threshold voltage of data transistor T ₁ of memory cell 2 ₂ is
Let TH ₁ be the off-resistance, ROFF ₁ be the off-resistance, TH ₂ be the threshold voltage of the data transistors T ₂ to TN, and RON ₂ be the on-resistance. Furthermore, if the on-state resistance of each select transistor TS is RONS, and the resistance value of the pull-up resistor is Rp, then the output level HMIN (minimum high level value) of one memory cell 2 ₁ and the other memory cell 2 ₂ The output level LMAX (maximum low level) is expressed by the following formula. Further, if the inversion (sense) level of the data read from the ROM 1 at this time is SE, then this inversion level SE is expressed by the following equation. SE=HMIN+LMAX/2...(2) FIG. 5 is a detailed circuit diagram of the sense amplifier 3 and the memory cells of the ROM1. The memory cells of ROM1 are connected in parallel to the data line DL by the number of address lines (2 ^m) . In this case, data transistors T ₁ to TN are individually driven on and off. The sense amplifier 3 is a transistor whose one end is connected to the data line DL and whose gate is driven by a clock signal via an inverter _I1.
Tr ₁ and Tr ₂ are each gate driven by the above clock signal, and one end is connected to the above reference level signal.
HMIN, LMAX, the other end is the above transistor
Transistor Tr ₃ connected to the other ends of Tr ₁ and Tr ₂ ,
Tr ₄ , capacitors C ₁ and C ₂ whose one ends are respectively connected to the other ends of the transistors Tr ₄ and Tr ₄ ,
An inverter I ₂ whose input end is connected to the other ends of the capacitors C ₁ and C ₂ , a transistor Tr ₅ connected in parallel to this inverter I ₂ and whose gate is driven by the above clock signal, and an output of the above inverter I ₂ It consists of a buffer _B1 connected between the terminal and the circuit output terminal OUT. In the sense amplifier circuit 3 above, the current data line
The input voltage at the connection point with DL is I, the transistor
The connection points of Tr ₁ and Tr ₂ and transistors Tr ₃ and Tr ₄ are respectively HS and LS, and the connection point of capacitors C ₁ and C ₂ is S, and the value of the VS point when the clock signal is at the “1” level is B. Let B' be the value of the VS point when the clock signal is at the "0" level. When the clock signal is at the “1” level, the transistors Tr ₃ ,
Tr ₄ is turned on, and reference level voltages HMIN and LMAX are applied to the HS and LS points, respectively.
At this time, transistor Tr ₅ is also turned on at the same time, and VS
The value of the point is fixed at B (the inversion level of inverter _I2 ). Then, the charge charged in the capacitor _C1 is (HMIN-B) _C1 , and the charge charged in the capacitor _C2 is (B-LMAX) _C2 .
Next, when the clock signal goes to "0" level, transistors Tr ₁ and Tr ₂ turn on, so HS,
The potential VI of the data read from ROM1 is applied to the LS point, and therefore the value B' at the S point is becomes. However, the capacitor C ₁ =C ₂ . Therefore,
Data input potential I and sense (inverted) level potential

The relationship with [formula] is

When [formula] is satisfied, the output data from the output terminal OUT becomes logic “1”, and vice versa.

When [Formula] is satisfied, the output data from the output terminal OUT becomes logic "0". In other words
When B′>B, the output data becomes “1”,
When B'<B, the output data becomes "0". In other words, in the above circuit, the data inversion level is HMIN, as shown in Figure 6a.
Since it is set to the intermediate value of LMAX, when the potential of data read from ROM1 through the data line DL is higher than the inversion level like I ₁ and I ₂ , the sense amplifier is activated as shown in Figure 6b. The output data from sense amplifier 3 becomes logic "1", and when the data potential is lower than the inversion level like VI ₃ and I ₄ , the output data from sense amplifier 3 becomes logic "0" as shown in FIG. 6b. ” becomes. The relationship between the value of point S and B and B' at that time is shown in FIG. 6b. In this way, according to the above circuit, the high-level minimum potential HMIN and the low-level maximum potential LMAX of data can be set by the reference circuit 2, which is made up of the same memory cells as the ROM cells, and the sense amplifier 3 Here, the intermediate potential between these potentials HMIN and LMAX is set as the inverted level (sense level) of the output data of ROM1. In other words, since the inversion level can be set for each individual sample device and can be set between the actual data output levels H and L of ROM1, the threshold voltage of each transistor in the memory cell
It is possible to prevent the inversion level margin from decreasing due to variations in TH, and to obtain stable operating characteristics even against fluctuations in external factors such as power supply voltage and temperature. In the above circuit, since a large number (2 ^m ) of memory cells are connected in parallel to the same data line, the cutoff resistance value of the transistor of the unselected memory cell (maximum number 2 ^m - 1) is the selected one. It is necessary to satisfy a relationship such that the resistance value is sufficiently larger than the resistance value of the transistor of the memory cell. Also,
When the number of address inputs (2 ^m ) is large, it is desirable to connect several stages of selection transistors TS in series, and it is desirable that the reference circuit has a similar configuration. Note that the present invention is not limited to the ROM of the above embodiment;
Although it is applicable to ROMs with other configurations, and the present invention is suitable for ROM output reading circuits,
It can also be applied to a RAM output reading circuit. As explained above, according to the present invention, a reference circuit is provided which can arbitrarily set the worst reference levels HMIN and LMAX of input data, and the reference levels HMIN and LMAX from this reference circuit are provided.
A sense amplifier circuit is provided that can set the inversion (sense) level of output data from LMAX, so when reading data from memory, the inversion level is affected by variations in the threshold voltage TH of memory cell transistors, fluctuations in power supply voltage, temperature, etc. It is possible to provide a memory output reading circuit that prevents margin reduction and obtains stable data detection operating characteristics.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory output reading circuit according to an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a detailed diagram of a reference circuit to FIG. 4 is a diagram showing the relationship between the threshold voltage of the transistor and the resistance to explain the circuit operation of FIG. 3, and FIG. 5 is a detailed circuit diagram of the ROM and sense amplifier circuit shown in FIG. 6a and 6b are diagrams for explaining the circuit operation of FIG. 5. 1...ROM, 2...reference circuit, 3...sense amplifier, DL...data line, Tp...precharge transistor, TS...select transistor,
_T1 to TN...data transistor, _Tr1 to _Tr5 ...transistor, _I1 , _I2 ...inverter, _B1 ...buffer, _C1 , _C2 ...capacitor.

Claims (1)

[Scope of Claims] 1. In a memory output reading circuit that detects data output from a semiconductor memory onto a data line and sends it to an external circuit as output data, the lowest potential of the high level of the input data of the semiconductor memory
a reference circuit that sets a reference level between HMIN and the maximum low-level potential LMAX;
Reference level from this reference circuit
The sense (inversion) level of the output data sent to the outside from HMIN and LMAX is set, and based on this sense level, the high and low levels of the data read from the semiconductor memory onto the data line are detected and the output data is and a sense amplifier circuit for obtaining a memory output reading circuit. 2 The reference circuit is composed of two memory cells having the same configuration as the memory cells of the semiconductor memory, one memory cell sets the reference potential level HMIN, and the other memory cell sets the reference potential level LMAX. 2. The memory output reading circuit according to claim 1, wherein the memory output reading circuit is configured to be set. 3. The sense amplifier circuit includes first and second transistors having one end connected to the data line and whose gates are driven by a clock signal via a first inverter, and one end connected to the other ends of the first and second transistors. are connected to each other and the other end is connected to the reference potential.
The third and fourth transistors are connected to HMIN and LMAX and whose gates are driven by clock signals, respectively, and one end of each is connected to the interconnection point of these first and third transistors and the interconnection point of the second and fourth transistors. a second inverter whose input ends are connected to the other ends of the first and second capacitors and whose output end is connected to an external output terminal via a buffer; 2
2. The memory output reading circuit according to claim 1, further comprising a fifth transistor connected in parallel to the inverter and whose gate is driven by the clock signal.