JPS5819795A - Memory output reading circuit - Google Patents

Memory output reading circuit

Info

Publication number
JPS5819795A
JPS5819795A JP11874281A JP11874281A JPS5819795A JP S5819795 A JPS5819795 A JP S5819795A JP 11874281 A JP11874281 A JP 11874281A JP 11874281 A JP11874281 A JP 11874281A JP S5819795 A JPS5819795 A JP S5819795A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
level
sense
data
reference
based
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11874281A
Other versions
JPS6325437B2 (en )
Inventor
Hitoshi Matsuda
Akira Suzuki
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Abstract

PURPOSE:To prevent the reduction of the sense level margin which is caused by the variance of the threshold voltage within a memory cell and the fluctuation of the power supply voltage/temperature, by setting the sense level of an output data based on the reference level given from a reference circuit. CONSTITUTION:A reference circuit 2 consisting of a memory cell which is equal to an ROM cell 1 sets the reference level between the minimum potential VHMIN of a high level and the maximum potential VLMAX of a low level of data. Based on this reference level, a sense amplifier 3 sets the sense level of the output data to the outside. Based on this sense level, the high or low level is detected for the data which is read out of the ROM1 onto a data line. Thus an output level is obtained.
JP11874281A 1981-07-29 1981-07-29 Expired JPS6325437B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11874281A JPS6325437B2 (en) 1981-07-29 1981-07-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11874281A JPS6325437B2 (en) 1981-07-29 1981-07-29

Publications (2)

Publication Number Publication Date
JPS5819795A true true JPS5819795A (en) 1983-02-04
JPS6325437B2 JPS6325437B2 (en) 1988-05-25

Family

ID=14743933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11874281A Expired JPS6325437B2 (en) 1981-07-29 1981-07-29

Country Status (1)

Country Link
JP (1) JPS6325437B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4677590A (en) * 1981-12-29 1987-06-30 Fujitsu Limited Nonvolatile semiconductor memory circuit including dummy sense amplifiers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4677590A (en) * 1981-12-29 1987-06-30 Fujitsu Limited Nonvolatile semiconductor memory circuit including dummy sense amplifiers

Also Published As

Publication number Publication date Type
JPS6325437B2 (en) 1988-05-25 grant

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