JPS63253597A - Read only storage device - Google Patents

Abstract

PURPOSE:To reduce electric current consumed by a readout-only storage device, by connecting an inverter to the gate of a PMOS transistor constituting a ROM cell and the gate of an NMOS transistor and data lines with the drain of one of the two transistors. CONSTITUTION:A P-channel MOS transistor (TR) 1 and N-channel MOS TR 2 constitute a ROM cell. The source of the TR 1 is connected with a high- voltage power source 6 and that of the TR 2 is connected with a low-voltage power source 7. To the gates of the TRs 1 and 2, address signals having different logic levels are inputted by means of the inverter 5. The drain of the TR 1 is not connected with a data line 3, but the drain of the TR 2 is connected with data line 4. Then the lines 3 and 4 are connected with each other and used as a ROM output 13. When an address line 10 is selected, a low voltage becomes the output 13 and, when address line 11 is selected, a high voltage becomes the output 13. Therefore, the electric current consumption of this read only storage device can be reduced and ROM codes can be set during the course of its manufacturing process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MO8LSI memory circuit, and particularly to a static read-only memory (hereinafter referred to as ROM).

[Conventional technology]

Conventionally, in this type of static ROM, as shown in FIG. The source of the cell N-channel MOS transistor 15 was connected, and the drain was optionally connected to the ROM output 13 or not connected.

When the address line 10 connected to the gate of the N-channel MOS transistor 15 for ROM cell is selected, the drain is connected to the ROM output 13, so P
A voltage determined by the voltage division ratio with channel MOS transistor 14 is output.

Also, when the address line 11 is selected, the drain is not connected to the ROM output 13, so the ROM output 13
The same potential as the high voltage voltage ff16 is output. Also, P
A read signal is input to the gate of channel MO8 transistor 14, and P-channel MOS transistor 14 is turned on when operating as a ROM.

[Problem that the invention seeks to solve]

The conventional static type ROM mentioned above is P telenel M
When the OS transistor and the N-channel MOS transistor are turned on at the same time, current flows from the high voltage power supply to the low voltage power supply, resulting in a disadvantage that current consumption increases.

[Means for solving problems]

The read-only memory device of the present invention has a ROMt transistor with a P-channel MoS transistor and an N-channel MO8t-transistor.
? The source of the P-channel MOS transistor is connected to a high-voltage power supply, the source of the N-channel MOS transistor is connected to a low-voltage power supply, and the source of the P-channel MOS transistor is connected to a low-voltage power supply.
An inverter is provided so that address signals of different logic levels are input to the gate of the S transistor and the gate of the N channel MOS transistor.
The drain of the transistor and the data line or N′
Only one of the drain of the ft/channel MOS transistor and the data line is connected.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a static ROM of the present invention. P-channel MOS transistor 1 and N-channel MOS transistor 2 are transistors that constitute a ROM cell. The source of P-channel MOS transistor 1 is connected to a high voltage power supply 6, and the source of N-channel MOS transistor 2 is connected to a low voltage power supply 7. Address signals having different logic levels are inputted to the gates of the connected P-channel MOS transistor 1 and N-channel MOS transistor 2 by an inverter 5.

The drain of P-channel MOS transistor 1 and data line 3 are not connected, and the drain of P-channel MOS transistor 1 is not connected to the data line 3.
The drain of the data line 4 is connected to the data line 4. The data line 3 and the data line 4 are connected to form a ROM output 13.

Next, the operation of this embodiment will be explained. When address line 10 is selected, in this embodiment, N-channel MO
Since the S transistor 2 and the data line 4 are connected, the data line 4 has the same voltage as the low voltage power supply 7, and a low voltage is output to the ROM output 13. Similarly, when the address line 11 is selected, the same potential as the high voltage power supply 6 is applied to the RO
It is output to M output 13.

FIG. 2 is a circuit diagram showing an example of application of this embodiment. This is a two-stage configuration of the configuration shown in FIG.
A transistor 9 is connected between the data line 3 and the data line 4, and the gates of the upper output stage P-channel and N-channel MOS transistors 8 and 9 transmit the read signal 16 to the lower output stage P-channel and N-channel MOS transistors. The gates of transistors 8 and 9 connect read signal 12,
The readout signal 16 is turned on when the upper stage is selected, and the readout signal 12 is turned on when the lower stage is selected. Although a two-stage configuration has been described here, it is clear that the output side may be connected in the same manner in a three-stage or more configuration.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which either the P-channel or N-channel MOS transistor is turned on during its operation, so that the current consumption can be extremely reduced, and the wiring between the ROM cell and the data line can be Since the ROM code is set based on the presence or absence of the ROM code, there is an effect that the ROM code can be set at the stage of M vapor deposition, which is the final step of the IC manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the ROM of the present invention, FIG. 2 is a circuit diagram of an application example of the ROM of FIG. 1, and FIG. 3 is a circuit diagram of a conventional general ROM. DESCRIPTION OF SYMBOLS 1... P channel MOS transistor of ROM cell, 2... N channel MOS transistor of ROM cell, 3.4... Data line, 5... Inverter, 6
...High voltage power supply, 7.Low voltage power supply, 8.
... Output stage P-channel MOS transistor, 9... Output stage N-channel MOS transistor, 10.11...
Address line, 12.16...Read signal, 13...ROM output, 14...P channel MOS transistor for bias, 15...N channel MOS transistor of ROM cell.

Claims (1)

[Claims] In a read-only memory device, a ROM cell is composed of a P-channel MOS transistor and an N-channel MOS transistor, the source of the P-channel MOS transistor is connected to a high voltage power supply, and the source of the N-channel MOS transistor is connected to a low voltage power supply. An inverter is connected to the voltage power supply and is provided so that address signals of different logic levels are input to the gate of the P-channel MOS transistor and the gate of the N-channel MOS transistor,
A read-only memory device characterized in that only one of the drain of a channel MOS transistor and a data line or the drain of an N-channel MOS transistor and a data line are connected.