JPS63250152A - Layout of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To optimize a channel width of a transistor for each gate inside a functional block and to prevent a shape of a layout block of the functional block from being distorted and becoming big by a method wherein the width of a channel region for all transistors included in each functional block is determined. CONSTITUTION:At a first step 11 a width W in a channel region 3 for all transistors inside a number of irregular functional blocks (circuits) is determined; at a next step 12, an average value Wt of the width W of these channels is determined. Then, at a step 13 it is judged whether the width W of the channel for a prescribed transistor is bigger than the average value Wt. First, if the width W of the channel is smaller than the average value Wt, only one transistor having this width W of the channel is arranged. If the width W of the channel is bigger than the average value, W/Wt=n is calculated at a step 15; (n) pieces of transistors which are connected in parallel are arranged. By this setup, a shape of the transistor is decided automatically; the shape of a block is not distorted or is made wastefully big.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a layout method for semiconductor integrated circuits, and in particular to a CAD method for automatically performing layout using a computer or the like.
This invention relates to a layout method for arbitrarily determining the shape of a transistor (computer-aided design).

[Conventional technology]

2. Description of the Related Art In recent years, research and development of means for automatically laying out functional blocks, etc. within a semiconductor integrated circuit device has been actively conducted.

In this case, functional blocks such as ROM, RAM, and PLA can function by combining regular transistor arrangements, but non-regular analog circuits include many types of functional blocks.

Conventional layout methods include the placement of tigers and jistas,
Various methods have been developed for wiring, but most methods use a uniform shape for the transistor shape, and even if there is some flexibility, the relative shape is constant, and the channel width of the transistor, This is achieved using a layout method that uses the channel length as a variable.

[Problem that the invention seeks to solve]

Since the conventional layout method described above fixes the transistor shape, it is not possible to secure the optimal transistor dimensions for each gate in the target functional block, and it is not possible to ensure that the characteristics such as operating speed of each functional block are fully satisfied. There is a drawback that it cannot be done. In addition, even in a layout method that uses channel width and channel length as variables, the relative shape is constant, so the size of each transistor shape differs due to the difference in channel width of transistors of various gates in each block. This has the disadvantage that the shape of the layout block becomes distorted, waste space is created in the layout, and the layout block becomes larger.

An object of the present invention is to eliminate such drawbacks, to provide a semiconductor integrated circuit in which the 1-transistor channel width of various gates in a functional block is optimized, and the shape of the layout block of the functional block is not distorted or enlarged. The purpose is to provide a layout method.

[Means for Solving the Problems] The configuration of the present invention provides a layout method for a semiconductor integrated circuit including a plurality of irregular circuit blocks, in which the widths of the channel regions of all transistors included in each circuit block are For transistors with a channel width smaller than the average channel width, one channel region with this channel width is arranged, and for transistors with a channel width larger than the average channel width, the average value of these channel widths is determined. It is characterized in that channel regions having the following channel widths are connected in parallel and arranged, or channel regions having a channel width less than or equal to the average channel width are arranged in an L-shape.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a flow diagram explaining one embodiment of the present invention, FIGS. 2(a) and (b) are transistor layout diagrams showing transistor shape models used in this embodiment, and FIG. 3(a)
-(d) are layout diagrams of transistors to which this embodiment is applied in four cases. In the transistor shape model shown in FIG. 2, 1 is a gate electrode region, 2 is a drain region, 3 is a channel region with a channel length and a channel width W1,
4 indicates a source area.

In this embodiment, first, in the first step 11, the width W of the channel region 3 of all transistors in a large number of irregular functional blocks (circuits) is determined, and in the next step, the average value of these channel widths W is calculated. Find Wt. Next, in step 13, it is determined whether the channel width W of a predetermined transistor is larger than the average value Wt.

First, when the channel width W is smaller than the average value Wt,
In step 14, as shown in the shape model of FIG. 2(a),
In other words, the transistor arrangement is such that the channel width W is only one.

Next, if the channel width W is larger than the average value, W/W t = n is determined in step 15, and W/N = W' is determined by rounding up the decimal point of n to the integer N, as shown in Fig. 2. As shown in the shape model shown in (b), N transistors are arranged in parallel.

FIGS. 3(a) and 3(b) are layout diagrams of the transistors arranged as shown in FIG. 2(a), and FIG.
c) and (d) are cases where the channel width is greater than Wt, and the second
A layout diagram of the transistors arranged as shown in FIG. 3(b), FIG. 3(C) shows the case where N=2, and FIG. 3(d) shows the case where N=4.

FIGS. 4(a) to 4(C) are layout diagrams of transistors illustrating another embodiment of the present invention. Figure 4(a), (
C) is the same as in FIGS. 3(a) and (d), but in FIG. 4(b), the channel width W of the transistor is larger than the average channel width Wt, and W/Wt is less than 2. It shows the arrangement of cases. In this case, the channel region 3 is arranged in an inverted or L-shape. That is, in this case, the channel W is the sum of the channel Wt and the channel width W11, and in this case, the layout area can be made smaller than in the case of FIG. 3(c).

〔Effect of the invention〕

As explained above, when using CAD for LSI design, the present invention automatically determines the shape of a transistor in a functional block that has a plurality of transistors with different channel lengths, and also automatically determines the shape of a transistor in a functional block that has a plurality of transistors with different channel lengths.
This has the effect of not increasing the size unnecessarily.

[Brief explanation of the drawing]

FIG. 1 is a flow diagram explaining one embodiment of the present invention, FIGS. 2(a) and (b) are layout diagrams of two transistor shape models used in this embodiment, and FIGS. 3(a) to (d). ) is a transistor shape diagram in which this embodiment is applied to four cases, and Fig. 4 (
a) to (C) are diagrams of transistor shapes to which other embodiments of the present invention are applied. 1... Gate electrode region, 2... Drain region, 3...
...Channel region, 4...Source region, 5...Diffusion region, 11-15...Step, W...Channel width, Ll...Channel length, L2...Gate electrode protrusion length , L3... Source and drain region width. Agent Patent Attorney Susumu Uchihara 74mm

Claims (1)

[Claims] In a layout method for a semiconductor integrated circuit including a plurality of irregular circuit blocks, the widths of the channel regions of all the transistors included in each circuit block are determined, the average value of these channel widths is determined, and from this average channel width, A transistor with a small channel width is arranged with one channel region having this channel width, and a transistor with a channel width larger than the average channel width is arranged with channel regions having a channel width less than or equal to the average channel width connected in parallel. A layout method for a semiconductor integrated circuit, characterized in that channel regions having a channel width less than or equal to the average channel width are arranged in an L-shape.