JPS63249225A - Data retrieving device - Google Patents

Abstract

PURPOSE:To execute a retrieval processing of an address at a high speed by processing a retrieval of an address of a retrieval designating data by an additional circuit. CONSTITUTION:A comparator 5 compares successively a data which is read out successively from a multi-port memory 3, and a retrieval designating data which is read out of a register 4, by synchronizing with a comparison timing signal outputted from a comparison control means 20, and when the data which is read out of the multi-port memory 3, and the retrieval designating data which is read out of the register 4 coincide, a coincidence signal is outputted. As a result, stepping of a counter is stopped, a switching signal is outputted from a bus switching control means 22, the counter 2 and a computer 1 are connected through an output data signal bus 14 and a data bus 11 and the count number of the counter 2 is read into the computer 1 as an address of the retrieval designating data. In such a way, the address of the retrieval designating data can be retrieved at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data retrieval device used for data retrieval in data processing systems, database systems, etc., table retrieval for routing in network systems, etc. .

(Prior Art) Conventionally, this type of data retrieval device has a configuration as shown in FIG. 3 to retrieve data stored in the main memory of a computer.

(a) Search method by successive comparison in a certain direction, (b
) Methods of speeding up search processing based on the calculation results of defined hash functions, etc., have been put into practical use.

(Problems to be Solved by the Invention) However, in the conventional data search device, the search process was entirely performed by software, so there was a problem in that the search required a large amount of time.

For example, when performing a table search using successive approximation for routing in a network system, etc., (a) There are 500 pieces of data shown in Figure 3.

(b) Processor calculation speed is 1.5 microseconds.

(c) Assuming that the length of one piece of data is 48 bits, the time required for the search process is approximately 750 microseconds. This poses a significant barrier for networks with transmission speeds of 10 to 100 Mbit/s.

The present invention has been made in view of such good fortune, and an object of the present invention is to provide a data search device that reduces search time.

(Means for Solving the Problems) The present invention includes a counter that sequentially outputs a count number as an address, a multiport memory that reads a large amount of data individually and sequentially each time the address changes, and a register that writes search specification data. , a comparator that sequentially compares the data output from the multi-port memory and the search specified data and outputs a match signal when the two match, and outputs this address to either the multi-port memory or the outside as appropriate. Control consisting of a bus switching circuit, means for controlling a comparator using a comparison timing signal, means for controlling a counter using a reset signal, a step start signal and a step stop signal, and a means for controlling the bus switching circuit using a switching signal. Compares the data sequentially output from the multiport memory with the search specified data every time the address changes, and if the two match, the count number of the counter at that time is searched at the address of the specified data. It is read out as .

(Function) Since the search for the address of the search specified data is processed by an additional circuit, the search process becomes faster than processing by software, and while searching for the address of the search specified data, the computer Processing can be done in parallel.

(Example) FIG. 1 shows the configuration of an embodiment of the present invention, and FIG. 2 shows the configuration of a control circuit in an embodiment of the present invention.
is a computer, 2 is a counter that sequentially outputs the count number as an address, and 3 is a multiport memory that writes or reads data (consisting of bit strings) independently to multiple ports. As shown in FIG. 3, a large number of data that have been individually written in advance are individually and sequentially read out each time the address of the counter 2 changes. Note that the multiport memory 3 is connected to the computer 1 via an address bus 10 and a data bus 11. Reference numeral 4 denotes a register in which data specified for searching in the computer 1 (consisting of a bit string (hereinafter referred to as search specified data)) is written, and this register 4 is connected to the computer 1 via an address bus 10 and a data bus 11. . Reference numeral 5 denotes a comparator that sequentially compares the data sequentially read from the multi-port memory 3 and the search specified data and outputs a match signal when the two match. 3 and the register 4 via an output data signal bus 13, respectively. 6 is counter 2
This bus switching circuit 6 outputs the address output from the multiport memory 3 or the computer 1 as appropriate to either the multiport memory 3 or the computer 1. are connected to the multiport memory 3 and to the computer 1 via a data bus 11, respectively. 7 is computer 1
When a search signal is input from the comparator 5, a comparison timing signal is output to start the comparison operation of the comparator 5, and when a match signal is input from the comparator 5, the output of the comparison timing signal is stopped and the comparison operation of the comparator 5 is started. □When a search signal is input from the comparison control means 20 to stop and the computer 1, a reset signal is output to reset the counter 2 to the initial value, and an upper 1 step start signal is output, and the counter 2 starts incrementing. and when a match signal is input from the comparator 5, it outputs a step stop signal to stop the counter 2 from advancing.When a search signal is input from the computer 1, it outputs a switching signal. Bus switching control means that inputs the address of the counter 2 to the multi-port memory 3, and when a match signal is input from the comparator 5, outputs a switching signal and causes the computer 1 to read the address of the counter 2 as the address of search specified data. 22, a comparison control means 20. Counter control means 21 and bus switching control means 22 are connected to computer 1 via address bus 10 and data bus 11, respectively.

In this embodiment configured in this way, when the search designation data is read into the register 4 from the computer 1 and a search signal is output from the computer 1, a switching signal is output from the bus switching control means 22, and the counter 2 and the multiport memory 3 are connected via the output data signal bus 14 and the address bus 15, and at the same time, a reset signal is output from the counter control means 21, and the counter 2 is reset to the initial value. Then, the counter control means 21 outputs an increment start signal, the counter 2 starts counting, and each time the counter 2 increments, a large amount of data written in the multi-port memory 3 is individually transferred. are read out sequentially. Therefore, the comparator 5 uses the data sequentially read from the multiport memory 3 and the register 4.
The comparison control means 2 compares the search specification data read from the
They are compared in sequence in synchronization with the comparison timing signal output from 0, and when the data read from the multiport memory 3 and the search specification data read from the register 4 match, a match signal is output. . Then, the comparison timing signal is no longer output from the comparison control means 20, and the operation of the comparator 5 is stopped.

A step stop signal is output from the counter control means 21,
Counter 2 stops advancing. Then, a switching signal is output from the bus switching control means 22, and the counter 2 and the computer 1 switch between the output data signal bus 14 and the data bus 1.
1, and the count number of the counter 2 is read into the computer 1 as an address of search designation data.

As a result, according to the conventional data search device that searches for the address of search specified data using software, the search time is about 750 microseconds, but according to the data search device of the present invention, under the same conditions, the search time is about 750 microseconds. The processing time is about 100 microseconds.

(Effects of the Invention) As explained above, according to the present invention, since the search for the address of the search specified data is processed by the additional circuit, the address search processing becomes faster than the processing by software, in other words, the search This has the effect that the time required to search for specified data is shortened, and that the computer can perform other processes in parallel while searching for the address of search specified data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a control circuit in an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a memory storing search data. FIG. 1...computer, 2...counter, 3
...Multi-port memory, 4 ... Register,
5... Comparator, 6... Bus switching circuit, 7
...Control circuit, 20...Comparison control means, 21...
Counter control means, 22...bus switching control means. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2

Claims (1)

[Scope of Claims] A counter that sequentially outputs a count number as an address; a multi-port memory that sequentially reads out a large number of pre-written data each time the address changes; a register that writes search designation data; a comparator that sequentially compares the data sequentially read from the port memory and the search specification data and outputs a match signal when the two match; and a comparator that outputs the address to either the multiport memory or the outside as appropriate. a bus switching circuit; a comparison control means for starting the comparison operation of the comparator when the search signal is input and stopping the comparison operation of the comparator when the match signal is input; and a comparison control means for starting the comparison operation of the comparator when the search signal is input; counter control means that resets the counter to an initial value and starts the increment of the counter, and stops the increment of the counter when the match signal is input; and when the search signal is input, the address is a control circuit comprising bus switching control means for inputting the address into a port memory and, when the match signal is input, reading the address to the outside as the address of the search designation data. Search device.