JPS63248157A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63248157A JPS63248157A JP8231087A JP8231087A JPS63248157A JP S63248157 A JPS63248157 A JP S63248157A JP 8231087 A JP8231087 A JP 8231087A JP 8231087 A JP8231087 A JP 8231087A JP S63248157 A JPS63248157 A JP S63248157A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resistor
- hydrogen
- polysilicon
- grown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 17
- 239000001257 hydrogen Substances 0.000 abstract description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 15
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract 3
- 238000005516 engineering process Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特にポリシリ
コンからなる抵抗体を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a semiconductor device having a resistor made of polysilicon.
従来この種の半導体装置は、ポリシリコンの抵抗体を形
成後、ＣＶＤ法により酸化膜を形成し、ＰＲ技術により
抵抗体の両端の酸化膜にコンタクトのための穴を開けた
後Ａρを配線し、半導体装置の最終保護膜としてプラズ
マＣＶＤ法によシリコン窒化膜を成長していた。Conventionally, in this type of semiconductor device, after forming a polysilicon resistor, an oxide film is formed using the CVD method, and holes for contact are made in the oxide film at both ends of the resistor using PR technology, and then Aρ is wired. , a silicon nitride film was grown by plasma CVD as the final protective film of a semiconductor device.
プラズマＣＶＤ法によるシリコン窒化膜（以後Ｐ−８ｉ
Ｎと記す）は、シラン（ＳｉＨ＋）ガスと、アンモニア
（ＮＨｓ ）ガスから成長するが、膜中にＳｉ −Ｈ。Silicon nitride film (hereinafter referred to as P-8i) by plasma CVD method
(denoted as N) grows from silane (SiH+) gas and ammonia (NHs) gas, but Si-H is present in the film.
Ｎ−Ｈ結合の形で多量の水素を含んでいる。このような
膜を最終保護膜として成長した後に、半導体装置に４５
０℃以上の温度で熱処理を行なうと、ポリシリコン抵抗
の抵抗値が減少するという問題を生じる。It contains a large amount of hydrogen in the form of N-H bonds. After growing such a film as a final protective film, a semiconductor device is coated with 45
If heat treatment is performed at a temperature of 0° C. or higher, a problem arises in that the resistance value of the polysilicon resistor decreases.
この理由は、熱処理によってＰ−８ｉＮ膜中のＳｉ −
Ｈ，Ｎ−Ｈ結合が切れて、遊離した水素がポリシリコン
中に入り、ポリシリコンのグレインバウンダリーに存在
するシリコンのダングリングボンドと結合し、ダングリ
ングボンドが減少するためである。The reason for this is that Si − in the P-8iN film is reduced by heat treatment.
This is because H, N--H bonds are broken, and liberated hydrogen enters the polysilicon and combines with silicon dangling bonds existing in the grain boundaries of the polysilicon, thereby reducing the number of dangling bonds.
本発明の半導体装置の製造方法は、ボリシリコン抵抗を
形成後、Ｐ−８ｉＮ膜の最終パッシベーション膜を形成
する前に、Ｐ−８ｉＮ膜中の水素が、ポリシリコン抵抗
中に入シ込むことを防ぐために、水素の移動に対してバ
リア膜として働らく、スパッタリングによるシリコン窒
化膜を形成するという工程を有している。The semiconductor device manufacturing method of the present invention prevents hydrogen in the P-8iN film from penetrating into the polysilicon resistor after forming the polysilicon resistor and before forming the final passivation film of the P-8iN film. In order to prevent this, there is a step of forming a silicon nitride film by sputtering, which acts as a barrier film against the movement of hydrogen.
シリコン窒化膜は元来、緻密な膜であるためのパッシベ
ーション膜として広く使われている。特にプラズマＣＶ
Ｄ法Ｋ ヨ７） Ｐ−８ｉＮｐと、ＬＰＣＶＤ（Ｌｏｗ
Ｐｒｅｓｓｕｒｅ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ
Ｄｅｐｏｓｉｏｎ 琺による５ｉ３Ｎｚ膜が使われてい
る。Ｐ−８ｉＮ膜は前述の通り、ＳｉＨ４とＮＨ３で成
長するため成長中に水素を発生したり、膜中に水素を含
有する。ＬＰＣＶＤのＳｉ３Ｎ４膜は膜中に水素を含ま
ないが、成長中に水素を発生する。一方、スパッタリン
グによるＳｉ、Ｎ４膜は、ＳｉターゲットあるいはＳｉ
３Ｎ４ターゲットとＮ２の反応性スパッタによって成長
するため、水素を発生したシ、膜中に含有せず、ポリシ
リコン抵抗に水素を供給することはない。Silicon nitride film is originally a dense film and is therefore widely used as a passivation film. Especially plasma CV
D method K Yo7) P-8iNp and LPCVD (Low
Pressure Chemical Vapor
Deposition A 5i3Nz film made of enamel is used. As described above, since the P-8iN film is grown using SiH4 and NH3, hydrogen is generated during growth and hydrogen is contained in the film. Although the LPCVD Si3N4 film does not contain hydrogen, it generates hydrogen during growth. On the other hand, Si and N4 films formed by sputtering can be formed using a Si target or Si
Since the film is grown by reactive sputtering using a 3N4 target and N2, hydrogen is not generated or contained in the film, and hydrogen is not supplied to the polysilicon resistor.
底建、本発明について図面を参照して説明する。 The present invention will be explained with reference to the drawings.
第１図は、本発明の製造方法の一実施例の断面図である
。Ｓｉ基板１を酸化し酸化膜２を形成する。FIG. 1 is a sectional view of an embodiment of the manufacturing method of the present invention. A Si substrate 1 is oxidized to form an oxide film 2.
ＬＰＣＶＤ法に！！り厚さ５０００＾のＰｏ１ｙ Ｓｔ
を成長し、ドーズｔ ４ Ｘ １０ ” ｃｒａ″′２
注入エネルギー７０ＫｅＶでリンをイオン注入し、ＰＲ
技術とドライエツチング技術を用いてポリシリコン抵抗
３を形成し、１０００℃でＰｏ１ｙ Ｓｉ表面を薄く酸
化し、ポリシリコン酸化膜４を形成する。Ｐｏ１ｙ Ｓ
ｉのＡρと接触する部分にリンを高濃度〈イオン注入し
熱処理によシ活性化する。スパッタリングによシ厚さ１
０００ ；、−のシリコン窒化膜５を成長する。このス
パッタシリコン窒化ｆｉ（Ｓ−８ｉＮ膜）の成長方法と
しては、ＳｉターケットのＮ２とＡｒガスによるスパッ
タリングと、Ｓｉ３Ｎ４ターゲットのＮ２とＡｒガスに
よるスパッタリングが考えられるが、今回は、Ｓｉター
ゲットを用いて形成した。Ｎ２ガスの分圧は１．６Ｘ
Ｉ Ｑ−３ｍｂａｒ、 Ａｒガスの分圧は５．ｌＸ１０
″″３ｍｂａｒでＳｉ基板を２００℃に加熱しながらパ
ワー１．５ＫＷでＲＦスパッタリングを行なった。成長
速度は２０λ／分である。次にＣＶＤ（Ｃｈｅｍｉｃａ
ｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法によｐ シ
９ ｙ（ＳｉＨ４）と酸素（０２）から５０００に酸化
膜６を成長する。ＰＲ技術とドライエツチング技術忙よ
シコンタクトの穴をあける。スパッタリングによシ１．
０μｍのＭを堆積し、ＰＲ技術とドライエツチング技術
によりＡＱ配線７を形成する。次にプラズマＣＶＤ法に
より５ＩＨ４とＮＨ，から、１．０μｍのＰ−ｓＨｊ膜
ｓを成長する。ＡＯとＰｏ１ｙ ８１のコンタクトのた
め４５０℃で３０分間のＡｆｉアロイを行う。このとき
従来のＳ−８ｉＮ膜５のない構造のポリシリコン抵抗で
あれば、４５０℃の熱処理によってＰ−８ｆＮ膜８の中
から遊離した水Ｍ （Ｈ） ｉ： ５０００ＸｏｃＶＤ
２化１２Ｊ ６ ト、５００＾ノポリシリコン酸化膜４
を透過して、ポリシリコン抵抗８に入り込む。入り込ん
だ水素はポリシリコンのグレインバウンダリーにあるシ
リコンのダングリングボンドと結合する。その結果がダ
ングリングボンドにとらえられていたキャリアが放出さ
れ自由キャリアとなシミ気伝導に寄与するようｊでなる
。自由キャリアがふえるとポリシリコン抵抗の抵抗値が
低下し、設計上要求されていた値からズしてしまい問題
となる。ここでの製造条件は、ポリシリコン抵抗の抵抗
率は６．３Ｘ１０３Ω口から、５Ｘ１０３Ω−に減少す
る。To the LPCVD method! ! Po1y St with thickness 5000^
grow and dose t 4 x 10”cra”’2
Phosphorus was ion-implanted at an implantation energy of 70 KeV, and PR
A polysilicon resistor 3 is formed using the technique and dry etching technique, and the surface of the PolySi is thinly oxidized at 1000° C. to form a polysilicon oxide film 4. Po1y S
Phosphorus is ion-implanted at a high concentration into the portion of i in contact with Aρ, and activated by heat treatment. Thickness 1 for sputtering
A silicon nitride film 5 of 000;, - is grown. Possible methods for growing this sputtered silicon nitride fi (S-8iN film) include sputtering using N2 and Ar gas from a Si target, and sputtering using N2 and Ar gas from a Si3N4 target. Formed. Partial pressure of N2 gas is 1.6X
I Q-3 mbar, partial pressure of Ar gas is 5. lX10
RF sputtering was performed at a power of 1.5 KW while heating the Si substrate to 200° C. at 3 mbar. The growth rate is 20λ/min. Next, CVD (Chemica)
An oxide film 6 is grown to a thickness of 5000 nm from p Si9 y (SiH4) and oxygen (02) by a vapor deposition method. PR technology and dry etching technology are used to create contact holes. For sputtering 1.
M is deposited to a thickness of 0 μm, and AQ wiring 7 is formed by PR technology and dry etching technology. Next, a 1.0 μm P-sHj film s is grown from 5IH4 and NH by plasma CVD. Afi alloying is performed at 450° C. for 30 minutes for contact between AO and Poly 81. At this time, in the case of a conventional polysilicon resistor having a structure without the S-8iN film 5, water M (H) i released from the P-8fN film 8 by heat treatment at 450°C is 5000XocVD.
2 oxide 12J 6 t, 500^ non-polysilicon oxide film 4
and enters the polysilicon resistor 8. The hydrogen that enters combines with the silicon dangling bonds in the polysilicon grain boundaries. As a result, the carriers trapped in the dangling bonds are released and become free carriers, which contribute to the air conduction. When the number of free carriers increases, the resistance value of the polysilicon resistor decreases, causing a problem as it deviates from the value required in the design. The manufacturing conditions here are such that the resistivity of the polysilicon resistor decreases from 6.3×10 3 Ω to 5×10 3 Ω.
本発明の製造方法によるとポリシリコン抵抗３とＰ−８
ｉＮ膜８の間にＳ−８ｉＮ膜５が存在するため、熱処理
によってＰ−８ｉＮ膜８から水素が遊離しても、Ｓ−８
ｉＮ膜が水素のバリアとなりポリシリコン抵抗８には致
達せず、従ってポリシリコン抵抗の抵抗値も変化しない
。According to the manufacturing method of the present invention, polysilicon resistors 3 and P-8
Since the S-8iN film 5 exists between the iN films 8, even if hydrogen is liberated from the P-8iN film 8 by heat treatment, the S-8iN film 5
The iN film acts as a barrier for hydrogen and does not reach the polysilicon resistor 8, so that the resistance value of the polysilicon resistor does not change.
第２図は２つめの実施例を示すもので、８−８ ｉ Ｎ
膜がポリシリコン酸化膜ではな（、ＣＶＤ酸化膜上に形
成されている。この場合も、Ｐ−８ｉＮ膜とポリシリコ
ン抵抗の間に、Ｓ−８ｉＮ膜が存在することから、実施
例１と同様に、ポリシリコン抵抗の抵抗値は変動し々い
。Figure 2 shows the second embodiment, in which 8-8 i N
The film is not a polysilicon oxide film (it is formed on a CVD oxide film). In this case as well, since there is an S-8iN film between the P-8iN film and the polysilicon resistor, it is different from Example 1. Similarly, the resistance value of polysilicon resistors tends to fluctuate.
以上説明したように本発明の製造方法によると、ポリシ
リコン抵抗とＰ−８ｉＮ膜の間に、水素の移動に対し阻
止能力のあるスパッタシリコン窒化膜が存在するための
ポリシリコン抵抗の抵抗値は変動しない。As explained above, according to the manufacturing method of the present invention, the resistance value of the polysilicon resistor is Does not change.
第１図、第２図は本発明の製造方法によるポリシリコン
抵抗の断面図である。
１・・・・・・Ｓ五基板、２・・・・・・シリコン酸化
膜、３・・・・・・ポリシリコン、４・・・・・・ポリ
シリコン酸化膜、５・・・スパッタシリコン窒化膜、６
・・・・・・ＣＶＤ法によるシリコン酸化膜、７・・・
・・・Ａ１配線、８・・・・・・プラズマＣＶＤ法によ
るシリコン窒化膜。
第２図1 and 2 are cross-sectional views of a polysilicon resistor manufactured by the manufacturing method of the present invention. 1... S5 substrate, 2... Silicon oxide film, 3... Polysilicon, 4... Polysilicon oxide film, 5... Sputtered silicon Nitride film, 6
...Silicon oxide film by CVD method, 7...
...A1 wiring, 8...Silicon nitride film by plasma CVD method. Figure 2
Claims (1)
リシリコンの抵抗体を形成後、スパッタリングによりシ
リコン窒化膜を成長する工程を含むことを特徴とする半
導体装置の製造方法。1. A method for manufacturing a semiconductor device having a polysilicon resistor, the method comprising the step of growing a silicon nitride film by sputtering after forming the polysilicon resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8231087A JPS63248157A (en) | 1987-04-02 | 1987-04-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8231087A JPS63248157A (en) | 1987-04-02 | 1987-04-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63248157A true JPS63248157A (en) | 1988-10-14 |
Family
ID=13770986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8231087A Pending JPS63248157A (en) | 1987-04-02 | 1987-04-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63248157A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02303154A (en) * | 1989-05-18 | 1990-12-17 | Fujitsu Ltd | Manufacture of semiconductor device |
| WO1993009599A2 (en) * | 1991-10-30 | 1993-05-13 | Harris Corporation | Analog-to-digital converter and method of fabrication |
| JPH05326849A (en) * | 1992-05-20 | 1993-12-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US5356825A (en) * | 1989-12-26 | 1994-10-18 | Sony Corporation | Method of manufacturing semiconductor devices |
| US5500553A (en) * | 1992-08-12 | 1996-03-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
| US6180479B1 (en) | 1998-05-21 | 2001-01-30 | Nec Corporation | Method of etching to form high tolerance polysilicon resistors |
| US7838962B2 (en) | 2007-12-21 | 2010-11-23 | Denso Corporation | Semiconductor device having capacitor, transistor and diffusion resistor and manufacturing method thereof |
-
1987
- 1987-04-02 JP JP8231087A patent/JPS63248157A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02303154A (en) * | 1989-05-18 | 1990-12-17 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5356825A (en) * | 1989-12-26 | 1994-10-18 | Sony Corporation | Method of manufacturing semiconductor devices |
| WO1993009599A2 (en) * | 1991-10-30 | 1993-05-13 | Harris Corporation | Analog-to-digital converter and method of fabrication |
| JPH05326849A (en) * | 1992-05-20 | 1993-12-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US5500553A (en) * | 1992-08-12 | 1996-03-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
| US5956592A (en) * | 1992-08-12 | 1999-09-21 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
| US6180479B1 (en) | 1998-05-21 | 2001-01-30 | Nec Corporation | Method of etching to form high tolerance polysilicon resistors |
| US7838962B2 (en) | 2007-12-21 | 2010-11-23 | Denso Corporation | Semiconductor device having capacitor, transistor and diffusion resistor and manufacturing method thereof |
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