JPS63247851A - Control system for read-only memory - Google Patents

Abstract

PURPOSE:To read out a program having its capacity larger than the address space of a microprocessor MPU by latching and decoding the data signal received from the MPU with the address signal received from the MPU and selecting plural read-only memories ROM. CONSTITUTION:A decoder 12 decodes the address signal received from an MPU1 and outputs the signals LATCH, CHANGE and ROMCS with the prescribed address signal value. The latch circuits 13 and 14 latch the data signals 1 and 2 outputted from the MPU1 by the signal secured an AND between signals LATCH and WR via an AND gate 17. Then the latch circuits 15 and 16 latch the signals 1 and 2 latched by the circuits 13 and 14 via an AND secured by an AND gate 23. A decoder 18 decodes the signals 1 and 2 latched by the circuits 15 and 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device glue-only memory control system using a microprocessor. In particular, the present invention relates to a control method for a read-only memory (hereinafter referred to as ROM) of a control device using a microprocessor (hereinafter referred to as MPU) during address expansion.

〔overview〕

The present invention is a ROM control method for a control device using an MPU, in which a data signal from the MPU is latched and decoded to select a plurality of ROMs according to a latch signal and an enable signal obtained by decoding an address signal from the MPU. , it is possible to read programs with a capacity larger than the address space of the MPU.

[Conventional technology]

FIG. 3 is a block diagram of a conventional read-only memory control device.

Conventionally, the read-only memory control method, as shown in FIG. 3, includes an MPU 31, an address signal decoder 22,
The ROM 33 is selected by a signal C8 obtained by decoding the address signal of the MPU 31.

[Problem that the invention seeks to solve]

However, in such a conventional glue-only memory control system, the ROM 33 is selected by the signal C8 which is directly decoded from the address signal of the MPU 31.
A program with a capacity larger than the address space of ROM3
Even if the program is written to MPU 3, there is a drawback that the MPU 31 cannot read out the portion of the program that extends beyond the address space of the MPU 31.

The present invention solves the above-mentioned drawbacks, and aims to provide a read-only memory control system that can read a program with a capacity larger than the address space of an MPU.

Means for Solving Problem c] The present invention provides a one-domain memory control system that includes a one-domain memory connected to the same address and a microprocessor that supplies an address signal and a read signal to the read-only memory and reads out its contents. In this method, there are a plurality of read-only memories, including a first decoder that decodes an address signal output from the microprocessor and outputs a latch signal and an enable signal, and a first decoder that decodes an address signal output from the microprocessor and outputs a latch signal and an enable signal; a plurality of latch circuits that latch data signals, and a second latch circuit that decodes the outputs of the plurality of latch circuits according to the enable signal and outputs a signal for selecting one of the plurality of read-only memories. It is characterized by being equipped with a decoder.

[For production]

The first decoder decodes the address signal output from the MPU and outputs a latch signal and an enable signal. MP by multiple latch circuits according to this latch signal.
Latch the data signal output from tJ. The second decoder decodes the outputs of the plurality of latch circuits according to the enable signal and outputs a signal for selecting one of the plurality of ROMs. By the above operations, it is possible to read a program with a capacity larger than the address space of the MPU.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a read-only memory control device according to an embodiment of the present invention. In FIG. 1, the read-only memory control device inputs the MPUI and the address bus from the MPUI, and receives the signals LATCH1CHANGE and ROMC5.
A decoder 12 outputs a signal LA from the decoder 12.
AND gate 17 which inputs TCH, inputs signal WR from MPUI and outputs the logical product; AND gate 23 which inputs signal CHANGE from the decoder 12, inputs signal WR from MPUI and outputs the logical product. and M
A latch circuit 13.1 inputs data signals 1.2 from the PUI via the data bus 11 to each input terminal, and inputs and latches the output of the AND gate 17 to each input terminal.
4.

Further, the read-only memory control device has a latch circuit 13.
．． Latch circuits 15 and 16 each input the latched data signal 1.2 from the output Q of 14 and input the output of the AND gate 23 to each input E, and the output of the output Q of the latch circuit 15 and 16. are input, and the signal ROMC5 from the decoder 12 is input to the input E, and the signal C
a decoder 18 that outputs 3I, C3z, and C33;
An address signal is input from the MPU II via the address bus 12, a signal RD is input, and the decoder 18
ROMs 19+ to 193 each receive signals C8l, C82, and C83 from the MPUI and output the data signals to the MPUI via the data bus p1.

The operation of the read-only memory control device having such a configuration will be explained. The decoder 12 decodes the address signal from the MPU 1 and outputs the signal LATCH2 signal CHANGE and the signal ROMC5 with a predetermined value of the address signal. Latch circuit 13.14
The data signals 1 and 2 output from the MPUI are connected to the signal L A T CH and the signal W by the AND gate 17, respectively.
The signal obtained by ANDing with R is latched. The latch circuits 15 and 16 each latch the data signals 1 and 2 latched in the latch circuits 13 and 14 using a signal obtained by ANDing the signal CHANGE and the signal WR using an AND gate 23. The decoder 18 decodes the data signal 1.2 latched in the latch circuit 15.16, and outputs the signal R
When OMC5 is output, signal CS, , signal C82
or outputs the signal CS. Signal C8, is ROM19
The signals cs, , and cs3 are signals for selecting ROMs 192 and 193, respectively. ROM1
91-19. are connected to the same address of MPUI.

FIG. 2 is a flowchart of a microprocessor program when switching read-only memories in the read-only memory control device of the present invention. ROM19
In order to perform the switching, it is first necessary to write a program corresponding to the flowchart shown in FIG. 2 from address Xe to address Xe in each of the plurality of ROMs 19 connected to the same address of the MPUI.

When it becomes necessary to switch the ROM 19, jump to address Xe (■). At address Xe, ROM19 is the switching destination.
The data signals 1 and 2 corresponding to the selection are latched in the latch circuits 13 and 14, respectively (■).

At the next address xb, write the start address ADDR at which you want to start the program in the ROM 19 at the switching destination into register A.

At the next address Xe, the signal CHANGE is output (■).

By this signal CHANGE, data signals 1 and 2 are latched by latch circuits 15 and 16, respectively, and input to decoder 18. Data signal 1.2 is the switching destination ROM1
The data corresponds to selection 9. therefore,
When reading an instruction from the next address Xd, the selected ROM 19 has been switched.

At address Xd, the start address ADDR at which the program is to be started in this ROM 19 is read from register A (■). Start address ADD at next Xe address
A jump is made to R (■), and the program for ROM switching ends.

〔Effect of the invention〕

As explained above, the present invention allows programs that require a larger capacity than the address space of the MPU to have multiple ROs.
It has an excellent effect that it can be used by writing in M.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a read-only memory control device according to an embodiment of the present invention. FIG. 2 is a flowchart of a program for switching read-only memories in the read-only memory control device of the present invention. FIG. 3 is a block diagram of a conventional read-only memory control device. 1.2...Data signal, 11...MPU, 12.1
8.32...Decoder, 13-16.32...Latch circuit, 17.23...And gate, 19. ~19
．． ．． 33...ROM, CHANGE, C3+, CS
z, C3z, RD, ROMC8...signal, l,...
...Data bus, 12...Address bus. Patent Applicant: NEC Corporation, Agent: Naotaka Ide, Patent Attorney 1 Embodiment Flowchart Figure 2 Figure 3

Claims (1)

[Claims] (1) In a read-only memory control system that includes a read-only memory connected to the same address and a microprocessor that provides an address signal and a read signal to the read-only memory and reads its contents, the read-only memory may be connected to a plurality of read-only memories. a first decoder (12) that decodes the address signal output from the microprocessor and outputs a latch signal and an enable signal; and a first decoder (12) that latches the data signal output from the microprocessor in accordance with the latch signal. a plurality of latch circuits (13 to 16); and a second decoder (13 to 16) that decodes the outputs of the plurality of latch circuits according to the enable signal and outputs a signal for selecting one of the plurality of read-only memories. 18)
A read-only memory control method characterized by: