JPS63245749A - Main memory device - Google Patents

Abstract

PURPOSE:To send an address abnormal signal from a main memory device by providing the main memory device with an address maximum value detecting circuit. CONSTITUTION:When an external device 2 sends an address signal 'FFFFF' in case the maximum value (the value of mounted maximum main memory address) of addresses mounted on a memory circuit 3 is 'FFFFF' and the maximum value of addresses to be sent from an address line 4 is 'FFFFF', all inputs of AND circuits 91-95 are turned to logic '1'. Since one input of an OR circuit 10 is turned to logic '1', an address abnormal signal of logic '1' is outputted. Since the address abnormal signal can be outputted in case of necessary independently of the value of the mounted maximum main memory address, the device is convenient for testing the operation of an address abnormal signal detecting circuit in the external device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main memory device, and more particularly to a main memory device equipped with a circuit for outputting an address error signal.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional device of this type, in which (1) is the main memory, (2) is an external device that accesses the main memory (1), and (3) is the main memory. Device(
1) is the main component of the memory circuit, (4) is the address line that transmits the address signal to access the memory circuit (3), and (5) is the main component of the memory circuit (3) or the memory circuit (4). A data line (6) is a comparator, (7) is a register, and (8) is an address error signal. The address signal is 2 with 20 bits.
When configured with a decimal code (corresponding to a 5-digit hexadecimal number), the address line (4) consists of 20 signal lines;
Expressed in hexadecimal digits from [0OOOOJ to [FFFF
Address signals with values up to FJ can be transmitted.

The register (7) holds the largest main memory address installed in the main memory (1) (more specifically, in the memory circuit (3) in the main memory (1)).

FIG. 4 is an explanatory diagram showing the configuration of register (7). Using the above numerical example, assuming that the address signal is composed of a 20-bit binary code, register (7) generally stores a 20-bit signal. Memory elements (7-〇 to 7-(n) in the figure)
-1). In the above example, n=20 (note that the intermediate elements are not numbered). Further, since there is no need to change the contents of the register (7) unless the memory circuit (3) is changed, the register (7) can be configured with a ROM (read-only memory). The power supply (7a), pull-up resistor (7b), switch (7C) shown in Figure 4
) can configure each bit signal. Also, when there is no need to change the contents of register (7),
The switch (7C) in FIG. 4 is constituted by a fuse, for example, and can output a logic "0" bit when it is connected, and a logic "1" bit when it is disconnected.

FIG. 5 is a format diagram illustrating an example of the maximum address of data implemented in the memory circuit (3) of FIG.
In the example shown in the figure, when the address is expressed as a 5-digit hexadecimal number, data is implemented in the area from 00000 to BFFFF, and data is not implemented in the area from C00OO to FFFFF.

The operation of the conventional apparatus will be explained below with reference to FIGS. 3, 4, and 5. Address line (4) from external device (2)
If the value of the address sent above is between 00000-BFFFF (in the numerical example shown in Figure 5), the data corresponding to the input address is transferred from the memory circuit (3) to the data line (
5) or the data on the data line (5) is written to the memory location corresponding to the input address. Also, since the numerical value BFFFF is written in the register (7), the value of the address sent on the address line (4) is co
When the value is between ooo and FFFFF, an address error signal (8) is sent from the comparator (6) to inform the external device (2) that the main storage device (1) cannot be accessed.

Also, in this case, it is not necessary to store all bits of BFFFF in register (7), but if only the most significant 4 bits (in the above example, B, or 1011' in binary code) are stored, the foot symbol can be stored. Ru. When the most significant four bits of the address signal on the address line (4) are C, D, E, F, an address abnormality signal (8) is sent out. In many cases, the maximum address of the implementation part of the memory circuit coincides with the change point of the upper bits of the binary code, so the number of bits to be stored in the register (7) is relatively small, and therefore in the comparator (6). The number of bits to be compared is often a relatively small number. Fifth
The right side of the figure shows an example in which a numerical value B (1011'') is stored in a register (7) consisting of 4 bits.

Since the conventional device is configured as described above, if the address of the memory installed in the memory circuit (3) is 00000-
FFFFF, therefore register (7) contains FF
If FFF is stored and there are 20 address lines (4), the address error signal (8) will not be sent out under any circumstances, and therefore the external device (2) will not be able to read the address. There is a problem in that it is difficult to test the operation caused by the abnormal signal (8).

This invention was made in order to solve the above-mentioned problems. Regardless of the relationship between the implemented maximum main memory address value and the maximum value of addresses that can be sent over the address line, The object is to obtain a main memory device that can output an abnormal signal.

[Means for solving problems]

In this invention, a circuit is provided that can output an address abnormality signal when the maximum value of addresses that can be sent out through the address line is sent out from an external device.

[Effect]

Implementation of the main memory device When the value of the maximum main memory address is equal to or exceeds the maximum value of the address that can be sent out by the address line, and for the purpose of testing regarding address abnormal signals, etc., the device of the present invention In this case, an address abnormality signal can be sent from the main memory by sending an address signal indicating the maximum value of the address that can be sent via the address line from an external device.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 1 is a circuit diagram showing an example of the configuration of the address maximum value detection circuit (9) in FIG. 1.

In these figures, the same symbols as in Fig. 3 indicate the same or corresponding parts, (9) is the address maximum value detection circuit, (10)
is an OR circuit, and (91) to (96) are AND circuits forming the address maximum value detection circuit (9).

Maximum address value (
When the maximum implemented main memory address value) and the maximum address value that can be sent through the address line (4) have a relationship as shown in Figure 5, the operation of the device in Figure 1 will be the same as the operation of the device in Figure 3. It is similar to However, if the address on the address line (4) is FFFFF, a logic "1" signal is output from both the comparator (6) and the address maximum value detection circuit (9), and the logical sum of these signals is As a result, an address abnormality signal (8) of logic "1" is output.

Different from the example shown in FIG. 5, if the value of the implemented maximum main memory address is FFFFF and the maximum value of the address that can be sent via the address line (4) is FFFFF, then However, in the device shown in Fig. 1, when the external device (2) sends out the address signal F F F F F on the address line (4), the AND circuit is activated. Since all the inputs of (91) to (95) are logic "1", one input of the OR circuit (10) is logic "1", so the address error signal (8) of logic "1" is Output.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to output an address abnormality signal when necessary, regardless of the value of the implemented maximum main memory address. This is useful when testing operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the maximum address value detection circuit shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional device. Figure 4 is an explanatory diagram showing the configuration of the register in Figure 3, and Figure 5 is an explanatory diagram showing the configuration of the register in Figure 3.
FIG. 3 is a format diagram illustrating an example of the maximum address of data implemented in the memory circuit shown in the figure. (1) is the main memory device, (2) is an external device, (3) is a memory circuit, (4) is an address line, (5) is a data line, (6) is a
) is a comparator, (7) is a register, (8) is an address abnormality signal, (9) is an address maximum value detection circuit, and (1o) is an OR circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A register in which the value of the maximum main memory address implemented in the main memory is set, an address signal input from an external device to access the main memory via an address line, and the contents of the register. and when the numerical value represented by the address signal is greater than the numerical value represented by the contents of the register, a logic "1" is generated.
A comparator that outputs the signal ``, inputs the above address signal, and the input address signal
When indicating the maximum value that the address signal can take, the logic
1, an OR circuit that outputs the logical sum of the output of the address maximum value detection circuit and the output of the comparator as an address abnormality signal. Storage device.