JPS63245750A - Main memory device - Google Patents

Abstract

PURPOSE:To accurately test the operation of an address abnormal signal detecting circuit in an external device by outputting an address abnormal signal by setting up/resetting a flip flop (FF) only when it is necessary. CONSTITUTION:When the maximum value (the maximum value of mounted main memory address) of addresses mounted on a memory circuit 3 is smaller than the maximum value of addresses to be sent by an address line 4, the FF 11 is reset. When the value of the mounted maximum main memory address is 'FFFFF' and the maximum value of addresses to be sent by the address line 4 is 'FFFFF', the FF 11 is set by the external device 2. When an address signal 'FFFFF' is sent to the address line 4, all inputs to AND circuits 91-95, 12 are turned to logic '1' and one input of an OR circuit 10 is turned to logic '1'. Thereby, an address abnormal signal 8 of logic '1' is outputted. Thus, the system is convenient for testing the operation of the address abnormal signal detecting circuit in the external device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main memory device, and more particularly to a main memory device equipped with a circuit for outputting an address error signal.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional device of this type, in which (1) is the main memory, (2) is an external device that accesses the main memory (1), and (3) is the main memory. Device(
1) is the main component of the memory circuit, (4) is the address line that transmits the address signal to access the memory circuit (3), and (5) is the main component of the memory circuit (3) or the memory circuit (4). A data line (6) is a comparator, (7) is a register, and (8) is an address error signal. The address signal is 2 with 20 bits.
When configured with a decimal code (corresponding to a 5-digit hexadecimal number), the address line (4) consists of 20 signal lines;
Expressed in hexadecimal digits from 00000J to [FFFF
Address signals with values up to F'J can be transmitted.

The register (7) holds the largest main memory address installed in the main memory (1) (more specifically, in the memory circuit (3) in the main memory (1)).

FIG. 4 is an explanatory diagram showing the configuration of register (7). Using the above numerical example, assuming that the address signal is composed of a 20-bit binary code, register (7) generally stores a 20-bit signal. Memory elements (7-〇 to 7-(n) in the figure)
-1). In the above example, n=20 (note that the intermediate elements are not numbered). Further, since there is no need to change the contents of the register (7) unless the memory circuit (3) is changed, the register (7) can be configured with a ROM (read-only memory). The power supply (7a), pull-up resistor (7b), switch (7C) shown in Figure 4
) can configure each bit signal. Also, when there is no need to change the contents of register (7),
The switch (7C) in FIG. 4 is constituted by a fuse, for example, and can output a logic rOJ bit when it is connected, and a logic "1" bit when it is disconnected.

FIG. 5 is a format diagram illustrating an example of the maximum address of data implemented in the memory circuit (3) of FIG.
In the example shown in the figure, if the address is expressed as a 5-digit hexadecimal number, ooooo~BFFFF-! , indicates that data has been implemented, and the area JCOOOO-FFFFF indicates that data has not been implemented.

The operation of the conventional apparatus will be explained below with reference to FIGS. 3, 4, and 5. Address line (4) from external device (2)
If the value of the address sent above is between ooooo and BFFFF (in the numerical example shown in Figure 5), the data corresponding to the input address is transferred from the memory circuit (3) to the data line (
5) or the data on the data line (5) is written to the memory location corresponding to the input address. Also, since the numerical value BFFFF is written in the register (7), the value of the address sent on the address line (4) is
When the value is between ooo and FFFFF, an address abnormality signal (8) is sent from the comparator (6) to inform the external device (2) that the main storage device (1) cannot be accessed.

Also, in this case, register (7) does not need to store all bits of BFFFF, but only the most significant 4 bits (B in the above example, i.e. 1011 in binary code) should be stored. Enough. When the most significant four bits of the address signal on the address line (4) are C, D, E, F, an address abnormality signal (8) is sent out. In many cases, the maximum address of the implementation part of the memory circuit coincides with the change point of the upper bits of the binary code, so the number of bits to be stored in the register (7) is relatively small, and therefore in the comparator (6). In many cases, the number of bits to be compared is relatively small. The right side of FIG. 5 shows an example in which a numerical value B (1011) is stored in a register (7) consisting of 4 bits.

[Problem that the invention seeks to solve]

Since the conventional device is configured as described above, if the address of the memory installed in the memory circuit (3) is 0oooo~
It is FFFFF, so register (7) contains FF.
If FFF is stored and there are 20 address lines (4), the address error signal (8) will not be sent out under any circumstances, and therefore the external device (2) will not be able to read the address. There was a problem in that it was difficult to test the operation caused by the abnormal signal (8). The applicant for a patent for this invention has filed a patent application (hereinafter referred to as a separate application) for an invention for solving the above-mentioned problem separately from this application. In this separate application, an address maximum value detection circuit is provided to detect the maximum address value that can be transmitted on the address line (4), and the logical sum of the output of this address maximum value detection circuit and the output of the comparator (6) is calculated. Output as address error signal. However, according to this separately filed device,
There is a problem in that an address abnormality signal may be output even when an external device does not require an address abnormality signal and there is actually no address abnormality, causing confusion.

The invention was made to solve the above problems, and regardless of the relationship between the maximum main memory address value that can be implemented and the maximum value of addresses that can be sent via the address line, It is an object of the present invention to provide a main memory device which can output an abnormality signal and outputs an address abnormality signal only when an actual address abnormality occurs, except when necessary for testing an external device.

[Failure to solve the problem]

In this invention, there is provided an address maximum value detection circuit that can detect when the maximum value of an address that can be sent through an address line is sent from an external device, and an output of this maximum address value detection circuit that is output as an address abnormality signal. A flip-flop is provided to control whether or not to do so.

[Effect]

Implementation of the main memory device When the value of the maximum main memory address is equal to or exceeds the maximum value of the address that can be sent out by the address line, and for the purpose of testing regarding address abnormal signals, etc., the device of the present invention Then, by setting a flip-flop from an external device and sending an address signal indicating the maximum value of the address that can be sent via the address line, it is possible to send an address abnormality signal from the main memory device. Furthermore, if the flip-flop is reset, the address abnormality signal will not be sent unless there is an actual address abnormality.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 1 is a circuit diagram showing an example of the configuration of the address maximum value detection circuit (9) in FIG. 1.

In these figures, the same symbols as in Fig. 3 indicate the same or corresponding parts, (9) is the address maximum value detection circuit, (10)
is an OR circuit, (11) is a flip-flop (hereinafter referred to as F/F)
), (12) is an AND circuit, (91) to (9
6) is an AND circuit constituting the maximum address value detection circuit (9). S, R, and Q of F/F (11) are a set signal input terminal, a reset signal input terminal, and an output terminal, respectively.

Maximum address value (
When the maximum main memory address (implemented maximum main memory address value) and the maximum address value that can be sent via the address line (4) have a relationship as shown in Figure 5, reset the F/F (11) in the device shown in Figure 1. Therefore, the operation of the apparatus of FIG. 1 is similar to that of the apparatus of FIG. Furthermore, when the address on the address line (4) is FFFFF, a logic "1" signal is output from the address maximum value detection circuit (9), but this signal is blocked by the AND circuit (12). and does not affect the address error signal.

Different from the example shown in Fig. 5, if the value of the implemented maximum main memory address is FFFFF and the maximum value of the address that can be sent through the address line (4) is FFFFF, in the conventional device, the address is abnormal. There is no opportunity for signal (8) to be sent out, but in the device shown in Figure 1, external device (2)
Set F (11) and then write F on the address line (4).
When the address signal of FFFF is sent, the AND circuit (91
) to (95) and (12) all inputs are logic “1”
Then, since one input of the OR circuit (10) becomes logic "1", an address abnormality signal (8) of logic "1" is output. F'/F (1
1), the address error signal is output only from the comparator (6), thereby avoiding confusion.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to output an address abnormality signal when necessary, regardless of the value of the implemented maximum main memory address. This is convenient when testing the operation, and when it is not necessary, it can be controlled so that the address error signal is output only from the comparator.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the maximum address value detection circuit shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional device. Figure 4 is an explanatory diagram showing the configuration of the register in Figure 3, and Figure 5 is an explanatory diagram showing the configuration of the register in Figure 3.
Format diagram 0 explaining an example of the maximum address of data implemented in the memory circuit in the figure (1) is the main memory, (2) is the external device, (3) is the memory circuit, (4) is the address line, (5) is the data line, (6
) is a comparator, (7) is a register, (8) is an address error signal, (9) is an address maximum value detection circuit, (10) is an OR circuit, (11) is an F/F, (12) is an AND circuit. . Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A register in which the value of the maximum main memory address implemented in the main memory is set, an address signal input from an external device to access the main memory via an address line, and the contents of the register. and when the numerical value represented by the address signal is greater than the numerical value represented by the contents of the register, a logic "1" is generated.
A comparator that outputs the signal ``, inputs the above address signal, and the input address signal
When indicating the maximum value that the address signal can take, the logic
1", a flip-flop that can be set or reset from the external device, and an AND circuit that outputs the logical product of the output of this flip-flop and the output of the maximum address detection circuit. , an OR circuit that outputs the logical sum of the output of the AND circuit and the output of the comparator as an address abnormality signal.