JPS6324559Y2 - - Google Patents
Info
- Publication number
- JPS6324559Y2 JPS6324559Y2 JP3248378U JP3248378U JPS6324559Y2 JP S6324559 Y2 JPS6324559 Y2 JP S6324559Y2 JP 3248378 U JP3248378 U JP 3248378U JP 3248378 U JP3248378 U JP 3248378U JP S6324559 Y2 JPS6324559 Y2 JP S6324559Y2
- Authority
- JP
- Japan
- Prior art keywords
- input
- time constant
- circuit
- section
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000001514 detection method Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 3
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- 239000003208 petroleum Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- 239000011593 sulfur Substances 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000005251 gamma ray Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Networks Using Active Elements (AREA)
- Control Of Amplification And Gain Control (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Description
【考案の詳細な説明】
本考案は、放射線応用機器等に用いられる時定
数回路に関するものである。[Detailed Description of the Invention] The present invention relates to a time constant circuit used in radiation application equipment and the like.
放射線応用機器においては、統計ノイズが存在
するため大きな時定数（例えば石油硫黄計では50
秒程度、γ線密度計では100秒程度）を持つた時
定数回路が用いられている。この時定数回路によ
る遅れは、プロセスが定常状態で入力信号が大き
く変わらない場合は問題ない（必要だから入れた
のであるから当然である）が、入力信号が急激に
しかも大きく変わる場合は追従性を損うという問
題がある。また石油硫黄計等においては、流路の
切換により一台の検出器に種々のサンプルを周期
的に送り込む場合があり、この場合には遅れによ
り測定時間が増大するという問題が生ずる。 Radiation application equipment has a large time constant (for example, a petroleum sulfur meter has a large time constant of 50
A time constant circuit with a time constant of about seconds (about 100 seconds for gamma ray densitometers) is used. The delay caused by this time constant circuit is not a problem if the process is in a steady state and the input signal does not change significantly (it is natural that it is included because it is necessary), but if the input signal changes suddenly and greatly, the followability may be affected. There is a problem of loss. Furthermore, in petroleum sulfur meters and the like, various samples may be sent periodically to one detector by switching flow paths, and in this case, a problem arises in that the measurement time increases due to delays.
本考案の目的は、入力信号が急激にしかも大き
く変化するような場合に追従性が上がる時定数回
路を提供することにある。 An object of the present invention is to provide a time constant circuit that improves followability when an input signal changes rapidly and greatly.
以下図面によつて本考案を詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.
第１図は本考案に係る時定数回路の一実施例を
示す構成図である。図において、１は入力信号Ei
の変化を検出する入力変化検出部、２は外部から
の指令により大小いずれかの時定数で動作する演
算部、３は入力変化検出部１の出力信号Efが一
定値を越えると小さい時定数で演算部２を動作さ
せる制御部である。ここでは、入力変化検出部１
として、演算部２の入出力信号の差Ei−Eoの絶
対値を検出するようなものを示した。次に各部の
構成を説明する。まず、入力変化検出部１におい
て、Qaは非反転入力端子がコモン点に接続され
た演算増幅器、Ra，Rbは演算増幅器Qaの反転入
力端子に接続された抵抗、Rcは演算増幅器Qaの
出力端子・反転入力端子間に接続された抵抗であ
る。上記演算増幅器Qaおよび抵抗Ra〜RcはEi−
Eoを求める加算回路を形成している（したがつ
て、この実施例ではRa＝Rb＝Rcに選ばれてい
る）。ABSはこの加算回路の出力信号Ei−Eoの絶
対値｜Ei−Eo｜を求める絶対値回路である。こ
の絶対値回路ABSの出力信号が入力変化検出部
１の出力信号となつている。次に演算部２におい
て、Qbは非反転入力端子がコモン点に接続され
た演算増幅器、Rdは演算増幅器Qbの反転入力端
子に接続された入力抵抗、Ca，Cbはコンデンサ
（容量はCa＞Cb）、Sa，Sbはそれぞれ二つの固定
側接点を有し一方の固定側接点がコモン点に接続
されたスイツチ、Reは演算増幅器Qbの負帰還路
の一つを成す抵抗である。コンデンサCa，Cbと
スイツチSa，Sbはそれぞれ直列に接続され、こ
れら直列回路がそれぞれ演算増幅器Qbの負帰還
路を形成している。演算増幅器Qbの出力信号が
演算部２の出力信号となつている。また、制御部
３において、Qcは入力変化検出部１の出力信号
Efを反転入力端子で受けるコンパレータ、Ｅは
コンパレータQcの非反転入力端子に接続された
電源（電源Ｅの大きさは統計ノイズ幅以上の大き
さに設定されている）、CNはコンパレータQcの
出力が低レベルのときスイツチSbを閉じ高レベ
ルのときスイツチSaを閉じる切換回路である。 FIG. 1 is a block diagram showing an embodiment of a time constant circuit according to the present invention. In the figure, 1 is the input signal Ei
2 is an arithmetic unit that operates with either a large or small time constant according to an external command; 3 is a calculation unit that operates with a small time constant when the output signal Ef of input change detection unit 1 exceeds a certain value; This is a control unit that operates the calculation unit 2. Here, input change detection section 1
In this example, the absolute value of the difference Ei-Eo between the input and output signals of the arithmetic unit 2 is detected. Next, the configuration of each part will be explained. First, in the input change detection section 1, Qa is an operational amplifier whose non-inverting input terminal is connected to the common point, Ra and Rb are resistors connected to the inverting input terminal of the operational amplifier Qa, and Rc is the output terminal of the operational amplifier Qa.・This is a resistor connected between the inverting input terminals. The above operational amplifier Qa and resistors Ra to Rc are Ei−
It forms an adder circuit for calculating Eo (therefore, in this embodiment, Ra=Rb=Rc is selected). ABS is an absolute value circuit that obtains the absolute value |Ei-Eo| of the output signal Ei-Eo of this adder circuit. The output signal of this absolute value circuit ABS is the output signal of the input change detection section 1. Next, in the calculation section 2, Qb is an operational amplifier whose non-inverting input terminal is connected to the common point, Rd is an input resistor connected to the inverting input terminal of operational amplifier Qb, and Ca and Cb are capacitors (the capacitance is Ca>Cb ), Sa and Sb are switches each having two fixed contacts, one of which is connected to a common point, and Re is a resistor forming one of the negative feedback paths of the operational amplifier Qb. Capacitors Ca and Cb and switches Sa and Sb are connected in series, and these series circuits each form a negative feedback path for operational amplifier Qb. The output signal of the operational amplifier Qb is the output signal of the arithmetic unit 2. In addition, in the control section 3, Qc is the output signal of the input change detection section 1.
A comparator that receives Ef at its inverting input terminal, E is a power supply connected to the non-inverting input terminal of comparator Qc (the size of power supply E is set to be larger than the statistical noise width), and CN is the output of comparator Qc. This is a switching circuit that closes switch Sb when the level is low and closes the switch Sa when the level is high.
次に本考案回路の動作を第２図を用いて説明す
る。定常状態であつた入力信号（電圧）Eiが第２
図に示すように急激にしかも大きく変化（この特
性曲線においては統計ノイズを考慮していない）
すると、入力変化検出部１の出力信号（電圧）
Efが増加しEf＞Ｅとなり、スイツチSaによつて
コンデンサCaの負帰還路が開かれ、スイツチSb
によつてコンデンサCbの負帰還路が閉じられる。
したがつて、時定数がCa，RdからCb，Rdに短
縮され、出力信号Eoが速やかに入力信号Eiに追
従する。そして、Ef＜Ｅとなると、スイツチSb
によつてコンデンサCbの負帰還路が開かれ、ス
イツチSaによつてコンデンサCaの負帰還路が閉
じられて、再び定常状態の時定数Ca，Rdの動作
に戻る。このため、第２図の立上り時間Ｔが短縮
され、追従性が向上する。 Next, the operation of the circuit of the present invention will be explained using FIG. The input signal (voltage) Ei that was in the steady state is the second
As shown in the figure, there is a sudden and large change (statistical noise is not taken into account in this characteristic curve)
Then, the output signal (voltage) of the input change detection section 1
Ef increases and becomes Ef > E, the negative feedback path of capacitor Ca is opened by switch Sa, and switch Sb
The negative feedback path of capacitor Cb is closed by .
Therefore, the time constants are shortened from Ca, Rd to Cb, Rd, and the output signal Eo quickly follows the input signal Ei. Then, when Ef<E, switch Sb
The negative feedback path of the capacitor Cb is opened by the switch Sa, and the negative feedback path of the capacitor Ca is closed by the switch Sa, and the operation returns to the steady state with time constants Ca and Rd. Therefore, the rise time T shown in FIG. 2 is shortened, and the followability is improved.
なお、上記の説明においては、固定側接点を二
つ有したスイツチについて述べたが、固定側接点
を一つ有するスイツチを二個用いて上記動作を行
わせることもできる。またスイツチは機械的なも
のに限らない。さらに、二つの時定数の選択の場
合について述べたが三以上であつても同様であ
る。また、コンデンサでなく、入力抵抗値Rdを
変えることにより時定数を変えるように構成する
ことができる。 In the above description, a switch having two fixed side contacts has been described, but the above operation can also be performed using two switches each having one fixed side contact. Moreover, the switch is not limited to a mechanical one. Furthermore, although the case of selecting two time constants has been described, the same applies even if three or more time constants are selected. Furthermore, the time constant can be changed by changing the input resistance value Rd instead of using a capacitor.
以上説明したように、本考案によれば、入力信
号が急激にしかも大きく変化するような場合に追
従性が上がる時定数回路を実現することができ
る。 As explained above, according to the present invention, it is possible to realize a time constant circuit that improves followability when an input signal changes rapidly and greatly.
第１図は本考案に係る時定数回路の一実施例を
示す構成図、第２図は第１図回路の動作説明図で
ある。
１……入力変化切換部、２……演算部、３……
制御部、Qa，Qb……演算増幅器、Qc……コンパ
レータ、Ra〜Re……抵抗、Ca，Cb……コンデ
ンサ、S1，S2……スイツチ、Ｅ……電源、CN…
…切換回路、ABS……絶対値回路。
FIG. 1 is a block diagram showing an embodiment of a time constant circuit according to the present invention, and FIG. 2 is an explanatory diagram of the operation of the circuit shown in FIG. 1...Input change switching section, 2...Calculating section, 3...
Control unit, Qa, Qb...Operation amplifier, Qc...Comparator, Ra~Re...Resistor, Ca, Cb...Capacitor, S1 , S2 ...Switch, E...Power supply, CN...
…Switching circuit, ABS…Absolute value circuit.
Claims (1)
と、外部からの指令により二以上の時定数のい
ずれかの時定数で動作する演算部と、前記入力
変化検出部の出力信号に応じて前記演算部に選
択すべき時定数を指令する制御部とを具備し、
前記演算部をコンデンサおよびスイツチでなる
複数の直列回路とこれら直列回路が負帰還路に
並列に接続され反転入力端子に入力抵抗が接続
された演算増幅器とで構成すると共に、前記複
数の直列回路のうち負帰還路として動作してい
ないときの直列回路を構成するコンデンサに、
演算増幅器の出力電圧をチヤージしておくこと
により、入力信号が急激且つ大きく変化しても
該入力信号に出力信号が速やかに追従するよう
に構成したことを特徴とする時定数回路。 (2) 前記入力変化検出部を前記演算部の入出力信
号の差を検出する回路で構成すると共に、前記
入力変化検出部の出力に応じて前記演算部のス
イツチを開閉するように前記制御部を構成して
なる実用新案登録請求範囲第(1)項記載の時定数
回路。[Claims for Utility Model Registration] (1) An input change detection unit that detects a change in an input signal, an arithmetic unit that operates with one of two or more time constants according to an external command, and the input change and a control unit that instructs the calculation unit to select a time constant according to the output signal of the detection unit,
The arithmetic unit is composed of a plurality of series circuits including capacitors and switches, and an operational amplifier in which these series circuits are connected in parallel to a negative feedback path and an input resistor is connected to an inverting input terminal. Among them, the capacitor that forms the series circuit when it is not operating as a negative feedback path,
1. A time constant circuit characterized in that the output voltage of an operational amplifier is charged so that the output signal quickly follows the input signal even if the input signal changes rapidly and greatly. (2) The input change detection section is constituted by a circuit that detects a difference between input and output signals of the calculation section, and the control section is configured to open and close a switch of the calculation section in accordance with the output of the input change detection section. A time constant circuit as set forth in claim (1) of the utility model registration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3248378U JPS6324559Y2 (en) | 1978-03-14 | 1978-03-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3248378U JPS6324559Y2 (en) | 1978-03-14 | 1978-03-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54135948U JPS54135948U (en) | 1979-09-20 |
| JPS6324559Y2 true JPS6324559Y2 (en) | 1988-07-05 |
Family
ID=28886063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3248378U Expired JPS6324559Y2 (en) | 1978-03-14 | 1978-03-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6324559Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5820017A (en) * | 1981-07-30 | 1983-02-05 | Victor Co Of Japan Ltd | Automatic gain controlling circuit |
-
1978
- 1978-03-14 JP JP3248378U patent/JPS6324559Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54135948U (en) | 1979-09-20 |
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