JPS63245286A - Phase comparison circuit - Google Patents

Abstract

PURPOSE:To prevent a servo-turbulence at the time of splice videotaping, by fixing a phase difference detection output at a given value for a specified period at the time of mode changing and by synchronizing, in the meantime, a reference signal with a comparison signal after mode changing. CONSTITUTION:If mode is changed from edit mode to recording mode at the time of splice videotaping, a switch 35 selects a capstan rotational frequency signal C-PG as a reset signal of a reference signal generator 31. Thus, the output phase of said reference signal generator 31 is caused to coincide with the phase of a signal C-PG coming first after timing for mode changing. On the other hand, when a switch 43 is turned, a PWM signal 02 of duty 50% is outputted as a phase error output by said timing for changing. Then, said switch 43 selects as a phase error output a PWM signal 01 of duty corresponding to a phase error by a given timing after a second signal C-PG has arrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention 1 (Field of Industrial Application) This invention relates to a phase comparator circuit used, for example, in a capstan servo circuit of a video tape recorder.

(Prior Art) Generally, in a home VTR, video signals are recorded and reproduced using a rotating magnetic head. Therefore, a head servo circuit is provided, and when recording a video signal, the rotary head is driven in synchronization with the vertical synchronization signal of the video signal to be recorded, and during playback, it is driven in synchronization with a predetermined reference signal. There is.

Furthermore, in a home VTR, a capstan servo circuit is provided to drive the magnetic tape at a constant speed during recording, and during playback, control signals recorded on the magnetic tape ( The CTL signal (hereinafter referred to as a CTL signal) is driven to have a constant phase.

In the above capstan servo circuit, the frequency is such that the frequency of the signal indicating the rotational frequency of the capstan obtained from the FG generation means provided on the capstan rotating shaft (hereinafter referred to as C-FG multiplied signal) is a constant frequency. Control is always in place. Furthermore, during recording, a signal obtained by frequency-dividing the C-FG signal by a predetermined amount (hereinafter referred to as C-PG multiplied signal)
Phase control is performed so that the signal has a constant phase with respect to the reference signal. Further, during reproduction, phase control is performed so that the CTL signal has a constant phase with respect to the reference signal. That is, in the phase control system of the capstan servo circuit, the control target is the C-PG multiplied signal CT during recording and playback.
It can be switched with the L signal. Therefore, when transitioning from playback mode (hereinafter referred to as PLAL mode) to recording mode (hereinafter referred to as REC mode), in so-called splice mode, the tape pattern of the splice portion is connected normally. Consideration is required, and the following techniques are required.

Prison.

In other words, Figure 5 shows the movement of the transition dance, in which the tape is rewound for a certain period of time after recording or playback is paused, and after the pause is released, the capstan servo is turned on for a shorter period than the rewind. locks and starts recording. Hereinafter, the period from pause release to recording start will be referred to as ASB (edit) mode.

FIG. 6' is a block diagram showing the configuration of a conventional capstan-based phase comparator circuit. The illustrated phase comparator circuit has two systems of single signal generators at 1, and in ASB mode,
The output of the reference signal generator (C-O 20) 11 is used as the reference signal, and the phase difference between this and the reproduced foot roll signal is detected. At this time, the other reference signal generator 12 is reset by the C-PG multiplied signal, and the phase difference is set to be the target value. Due to the transition from the ASB mode to the RFC mode, the reference signal is transferred from the output of the reference signal generator 11 to the output of the reference signal generator 12, and the output of the reference signal generator 12 is, as described above, C
- Since the phase difference of the PG multiplied signal is set to a target value in advance, servo disturbance does not occur during mode transition.

In addition, 13.14 is a pattern detection circuit, 15 is an up counter, 16 is an all 1 detection circuit, 17 is a latch circuit,
18 is a PWM conversion circuit, 19°20.21...switch, 22 is a reference signal generator for the Herad servo system, and 23 is an X
Monostable multivibrator (X-MM) for ta correction,
24 is a monostable multivibrator for tracking adjustment (
TRK-MM).

The conventional phase comparison circuit in the capstan servo system has been described above. Although this phase comparison circuit can prevent servo disturbance during mode transition, it requires two reference signal generators for this purpose. There was a problem that the circuit wA model increased.

(Problems to be Solved by the Invention) As described above, in the conventional phase comparator circuit, although it is possible to prevent servo disturbance during continuous shooting,
Since two reference signal generators are required, there is a problem in that the circuit scale becomes large.

Therefore, this invention eliminates the need to add a phase comparator circuit.
It is an object of the present invention to provide a phase comparator circuit capable of preventing servo disturbance during short selling.

[Structure of the Invention] (Means for Solving the Problems) - In order to achieve the above object, the present invention includes means for fixing the phase difference detection output to a predetermined value for a certain period of time when the mode is switched; When the mode is switched, means is provided for synchronizing the reference signal with the comparison signal after the mode switching within the predetermined period and then setting internal synchronization.

(Function) According to the above configuration, when the mode is switched, the phase difference detection output is fixed at a predetermined value for a certain period of time, and during this period, the phase difference between the reference signal and the comparison signal after the mode switch is detected. set to the value. Therefore, one reference signal generator can prevent servo disturbances during mode switching.

(Example) Hereinafter, an example of a real box of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In the figure, 31 is a reference signal generator (C-O 20), which is constituted by, for example, an up counter. This reference signal generator 31 is reset by the output of a tracking adjustment monostable multivibrator (TRK-MM) 32 during playback, and reset by the detection output of a pattern detection circuit 33 (described later) during recording. It is reset by the output of the monostable multivibrator (X-MM) for value correction, and is reset by the C-PG double signal when transitioning from ASB mode to RFC mode. Note that these reset signals are selectively applied via the switch 35.

A pattern of the count output of the reference signal generator 31 is detected by a pattern detection circuit 33. This pattern detection circuit 3
3 generates a reset signal when the output of the reference signal generator 31 becomes a predetermined pattern (predetermined count value), and resets the up counter 36 for trapezoidal wave generation. When all the bits of the counter 36 become 1, the all-1 detection circuit 37 outputs a clock prohibition signal, and the supply of the counting clock to the counter 36 is prohibited.

As a result, the count value of the counter 36 is held at all 1's until it is reset next time, and a trapezoidal wave is formed. Note that the detection output of the all 1 detection circuit 37 is, for example, a high level signal, which is sent to the inverter 38.
By inverting the signal and closing the gate of the AND circuit 39, the input of an O clock to the counter 36 is prohibited.

The count value of the up counter 36 is further supplied to a latch circuit 40, and is latched at the arrival timing of the C-PG multiplied signal in the recording mode REC, and at the arrival timing of the P-CTL signal in other modes. In addition, these C-
The PG multiplied signal P-CTL signal is supplied via the switch 41. This latch data is supplied to the PWM modulation circuit 42, and a pulse width modulation signal (hereinafter referred to as PWM signal). Furthermore, this PWM conversion circuit 42 always outputs a PWM signal 02 with a duty of 50%, and this PWM signal 02 and the above-mentioned PWM signal 01 having a duty according to the phase error are switched according to the control signal C. 43 is alternatively selected.

In addition, 44 is a reference signal generator of the Herad servo system,
For example, it is configured by an up counter.

The operation of the above configuration will be explained with reference to FIG.

When the mode is switched from the ASB mode to the RFC mode during continuous shooting, the switch 35 selects the C-PG multiplied signal as the reset signal for the reference signal generator 31. As a result, the phase of the output of the reference signal generator 31 changes from the C-P that first arrives after the mode switching timing tI.
The rising timing of the G multiplied signal is 0.degree. C.2, and the phase of the C-PG multiplied signal is adjusted. Thereafter, the switch 35 selects the detection output of the pattern detection circuit 31 as the reset signal of the reference signal generator 31. As a result, the reference signal generator 31 enters a self-resetting state.

Next, when the mode is switched, the switch 43 selects the PWM signal 02 as the phase error output from the switching timing until the arrival of the second C-PG multiplied signal. As a result, an output with no phase error can be obtained. Then, at a predetermined timing t3 after the arrival of the second C-PG multiplied signal, the switch 43 selects the PWM signal 01 as the phase error output. This prevents servo disturbances during mode transition.

The overall configuration and operation of the phase comparator circuit of one embodiment have been described above. Here, the configuration for obtaining the control signal C of the switch 43 and the configuration of the switch 43.35 are shown in FIGS. 3 and 4. This will be explained with reference to.

First, the configuration for obtaining the control signal C of the switch 43 will be explained. As shown in FIG. 4, the signal M1 shown in FIG. 3 is switched from the 0-low level to the high level when the mode is switched from the ASB mode to the RFC mode.

As a result, the output of the inverter 51 becomes low level, the reset state of the D flip-flop circuits 52 and 53 is released, and the control signal C of the switch 43, which is the output of the AND circuit 54, becomes high level. As a result, PWM (1ft!!02) is selected in the switch 43.
When the a-times signal arrives, the Q output of the D flip-flop circuit 53 becomes 0-level at the timing of its rising edge. As a result, the control signal C becomes low level, and the switch 43 selects the PWM signal 01.

Next, the configuration of the switch 35 will be explained. This switch 35
is a switch 351 that selectively selects the output of the monostable multivibrator 32, 33 and the detection output of the pattern detection circuit 33; two O flip-flop circuits 352, 35;
3. Consists of an OR circuit 354. The D flip-flop O-tube circuit 352 receives the Q output of the D flip-flop O-tub circuit 52, and its Q output becomes high level at the timing when the first C-PG double signal arrives after switching from ASB mode to REC mode. . This Q output is latched by the D flip-flop circuit 353 at the timing of 0 to GK.

As a result, the Q output of the D flip-flop circuit 353 becomes high level. This Q output passes through an OR circuit 354 and is used as a reset signal when switching from A3B mode to RFC mode.

As detailed above, in this embodiment, when the mode is switched from ASB mode to REC mode, the duty of the phase error output is fixed at 50% for a certain period of time, and during this period, the reference signal generation f131 is multiplied by C-PG. The signal is synchronized, and the synchronization of the reference signal generator 31 is switched to internal synchronization. Therefore, according to this embodiment, the mode is turned off when the reference signal is generated N31! Servo disturbance at the time of ji can be prevented, and an increase in the number of times MMfl will not be caused.

Although one embodiment of the present invention has been described in detail, the present invention is not limited to this embodiment, and it goes without saying that various other modifications can be made.

[Effects of the Invention] As described above, according to the present invention, servo disturbances at the time of mode switching can be avoided in the minimum necessary number of times N#I without adding a reference signal generator.

[Brief explanation of drawings]

FIG. 1 is a 10-step diagram showing the configuration of an embodiment of the present invention.
2 is a timing chart for explaining the operation of the circuit in FIG. 1, FIG. 3 is a circuit diagram showing a specific configuration of a part of an embodiment, and FIG. 4 is a timing chart for explaining the operation of the circuit in FIG. FIG. 5 is a timing chart for explaining, FIG. 5 is a diagram for explaining the connecting weave, and FIG. 6 is a circuit diagram showing the configuration of a conventional phase comparator circuit. 31... Reference signal generator, 32... Monostable multivibrator for tracking adjustment, 33... Pattern detection circuit, 34... XQI stable multivibrator. 35.41.43... Switch, 36... Up counter, 37... All 1 detection circuit, 38... Inverter, 39... AND circuit, 40... Latch circuit, 42... PWM conversion circuit.

Claims (1)

[Scope of Claims] Synchronous reference signal generation means for generating a reference signal for phase comparison; and phase difference detection means for detecting a phase difference between the reference signal and the comparison signal output from the reference signal generation means. , When the first phase comparison mode using the first comparison signal as the comparison signal is switched to the second phase comparison mode using the second comparison signal, the detection of the phase difference detection means is performed for a certain period of time. detection output fixing means for fixing the output to a predetermined value; and when the phase comparison mode is switched, the reference signal generation means is synchronized with the second comparison signal within the fixed period, and then the synchronization is stopped. A phase comparator circuit comprising: synchronization switching means for switching to synchronization using self-output.