JPH04285747A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To realize a consecutive recording with always stable condition by correcting the data of a reference signal used in a recording mode so as to made it almost equal to phase difference detecting data at the time of preliminary reproducing mode. CONSTITUTION:The phase difference(A)between a capstan reference signal REF immediately after a command to transfer from the preliminary reproducing mode to the recording mode is received and a reproduced control signal PCTL, and the phase difference (B) between the capstan reference signal REF and a CPG signal frequency-dividing a capstan FG signal are obtained respectively in 1st and 3rd counter circuits 6,8. The data adding the (+B-A) to the capstan reference signal after transferred to the recording mode are inputted as the phase reference data, and also the signals frequency-dividing the capstan FG signal are inputted as the capstan data, to a phase detector 3 by an arithmetic device 11. By these phase difference output data, a phase control of the capstan driving system is performed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a magnetic recording/reproducing device (
The present invention relates to a VTR (hereinafter referred to as a VTR), and more specifically relates to an improvement of a continuous shooting device thereof.

0002

2. Description of the Related Art Conventionally, as a running control method for a VTR, a method using a control signal which is tape position information is known. In this running control system, a control track is provided on the magnetic tape in addition to the video signal track, and the running of the tape is controlled by recording and reproducing control signals using this control track. In such a VTR, recording is temporarily stopped during the recording mode (hereinafter referred to as recording pause mode), and then the recording pause mode is canceled and the recording mode is switched again to continue recording on the tape. "
When performing continuous shooting, continuity of control signals before and after the continuous shooting must be maintained.

Therefore, when a recording pause operation is performed, the capstan shaft for running the tape is reversed, the tape is rewound for a certain period of time, and then stopped, and when an operation to cancel the recording pause mode is performed, The above capstan shaft is rotated in the normal direction to drive the tape and enter the playback mode. During this playback mode, the phase of the control signal corresponding to the video signal to be recorded next and the control signal being played is matched. The method used is to restart recording after adjusting the drive of the capstan shaft.

FIG. 5 is a timing chart of this continuous shooting method. In FIG. 5(a), when the recording pause operation is performed at time t0, as shown in FIG. 5(b) and (c), time t0 to time t1, the capstan shaft is reversed, the tape is rewound, and then stopped.
When the pause release operation is performed at 2, the control signal is played back in playback mode until time t3.
During this time, the drive of the capstan shaft is adjusted and recording is restarted. Hereinafter, the playback mode from time t2 to time t3 after the pause is released will be referred to as the preliminary playback mode.

FIG. 6 is a block circuit diagram of the main parts of a conventional VTR that performs the above-mentioned ``continuous shooting'' operation. In the figure, 1 is a capstan reference signal generator, and 2 is a recording control signal generator. , 3 is a phase detector, 4 is a speed detector, 5 is a deviation amplifier, 9 is a frequency divider, and S1 and S2 are switches.

Next, the operation after the pause is released will be explained with reference to the timing chart shown in FIG. The capstan reference signal generator 1 receives a signal in synchronization with a video signal to be recorded next, such as a vertical synchronization signal (hereinafter referred to as a VS signal), and generates a drum reference signal DR for drum rotation control. A synchronized capstan reference signal (hereinafter referred to as REF signal) as shown in FIG. 7(a) is output.

This REF signal is input to the recording control signal generator 2 and a control signal for recording is output, but the switch S1 remains open until recording resumes after time t2 in FIG. 5(a). Therefore, no recording control signal is supplied to the control head (not shown).

At the same time, the REF signal is input to the phase detector 3, and the phase detector 3 receives the reproduction signal as shown in FIG. 7(b) during the preliminary reproduction mode from time t2 to time t3 in FIG. A control signal (hereinafter referred to as PCTL signal) is input via switch S2, and the phase detector 3
outputs phase difference detection data DP corresponding to the phase difference between the rising edge of the REF signal and the rising edge of the PCTL signal.

During this time, the capstan FG signal (hereinafter referred to as CFG signal) shown in FIG. 7(c), which is input as a clock to the frequency divider 9, is reset every time the PCTL signal is input. As shown in FIG. 7(d), a capstan position signal (hereinafter referred to as a CPG signal) synchronized with the PCTL signal is output. and,
When transitioning to the recording mode at time t3 in FIG. 5, the switch S2 is switched and the CPG signal is supplied to the phase detector 3, but the phase difference between the rising edges of the PCTL signal and the CPG signal is at most Since the deviation is only by one cycle, the phase detection data DP output from the phase detector 3 does not deviate significantly.

FIGS. 7(e), (f), and (g) show the PCTL signal, CFG signal, and CPG in the preliminary reproduction mode.
This is an enlarged view of the relationship between the signals.As is clear from the figure, the PCTL signal and CFG signal are in an asynchronous relationship, so there is a maximum CFG difference between the rising edges of both signals.
There is a phase difference of one signal period TO (generally PCTL
(signal frequency<CFG signal frequency), as a result, the phase shift TE between the CPG signal and the PCTL signal, which are the outputs of the frequency divider 9, also becomes maximum TO.

On the other hand, the CFG signal is input to the speed detector 4 to output speed detection data DF, and is input to the deviation amplifier 5 together with the above-mentioned phase detection data DP to output a control signal to the capstan shaft drive system. It is outputting.

0012

[Problems to be Solved by the Invention] Conventional VTRs are configured as described above, and when transitioning from the preliminary playback mode to the recording mode during continuous shooting, the CPG signal, which is the comparison signal of the phase detector 3, and the preliminary playback mode The amount of phase shift from the PCTL signal at the time depends on the frequency of the CFG signal. The rotational speed of the capstan shaft is generally low, and there is a limit to increasing the frequency of the CFG signal, so as a result, TO of one cycle of the CFG signal actually becomes a fairly large value. Therefore, the error in the phase detection data DP becomes large before and after changing from the preliminary reproduction mode to the recording mode.

Moreover, if the amplifier gain of the deviation amplifier 5 in the subsequent stage is also taken into account, the error in the control output to the capstan shaft drive system becomes even larger. therefore,
The continuity between the control signal recorded after restarting recording and the previously recorded control signal becomes poor, and tracking is lost during normal playback, resulting in image distortion and S/N.
There was a problem that the deterioration of

[0014] Furthermore, in a segment VTR in which one field of video signal is divided into a plurality of tracks and recorded, it is necessary to restore the divided image during recording to the original pre-divided signal during playback. Therefore, if tracking loss occurs during normal playback due to discontinuity in the control signal before and after splicing, there is a high possibility that the screen restoration operation during playback will fail, and the playback image will become larger. The problem is that it gets messy.

[0015] This invention was made to solve the above-mentioned problems, and its purpose is to provide a VTR that can always realize stable continuous shooting without increasing the frequency of the CFG signal. That is.

[0016]

[Means for solving the problems] The present invention relates to a VTR.
is the phase difference A between the capstan reference signal REF and the reproduced control signal CPTL immediately after receiving the command to shift from the preliminary reproduction mode to the recording mode, and the phase difference C obtained by dividing the capstan reference signal REF and the capstan FG signal.
Means for determining the phase difference B with respect to the PG signal, and (+B-
The data obtained by adding A) is input as phase reference data, and the signal obtained by dividing the frequency of the capstan FG signal is input to the phase comparator as comparison data, and the output data of the phase difference is used to control the phase of the capstan drive system. It is characterized by being configured as follows.

[0017]

[Operation] According to the present invention, the phase difference detection data between the data of the new reference signal input to the phase comparator after shifting to the recording mode and the capstan position data as a comparison signal is the phase difference in the preliminary reproduction mode. Since the data of the reference signal used in the recording mode is corrected so that it is almost equal to the detected data, there is almost no fluctuation in the running of the tape when transitioning from the preliminary playback mode to the recording mode. The continuity of the tape position signal represented by the control signal can be maintained with high precision.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram of the main parts of a VTR according to an embodiment of the present invention.
Since 3, 4, 5, and 9 are the same as those in the conventional example shown in FIG. 5, they are given the same reference numerals and their explanation will be omitted.

In FIG. 1, 6, 7, 8 are the first, second,
In the third latch circuit, 10 is a cyclic counter, 11 is an arithmetic unit composed of a microprocessor, and 12 is a drum reference signal generator.

Next, the operation of the above configuration will be explained. Of the operations during continuous shooting, the same portions as those in the conventional example shown in FIG. 6 are as described above, and therefore, description thereof will be omitted.

In FIG. 1, a capstan reference signal generator 1 and a drum reference signal generator 12 are inputted with a signal, for example, a VS signal, which is in synchronization with the video signal to be recorded after the preliminary playback mode. Signal generator 1
2, a drum reference signal DR for controlling the rotational phase of the rotary drum is output in synchronization with the REF signal.

On the other hand, the REF signal is input to the recording control signal generator 2 to generate a recording position signal (hereinafter referred to as an RCTL signal), and the phase of the rotating drum whose rotational phase is controlled by this RCTL signal and the DR signal. are in a synchronous relationship.

The first latch circuit 6 receives the REF signal, the second latch circuit 7 receives the PCTL signal, and the third latch circuit 7 receives the PCTL signal.
The CPG signal is input as a latch pulse to the latch circuit 8, and these first, second,
The third latch circuits 6, 7, and 8 each receive a count value obtained by counting clock pulses of several MHz by the cyclic counter 10 as count data, and the first latch circuit 6 inputs this count data. The arithmetic unit 1 latches each rising edge of the REF signal and uses the data as reference latch data as shown in FIG. 2(e).
Output to 1. This arithmetic unit 11 is composed of, for example, a one-chip microcomputer, and stores the input reference latch data in a built-in random access memory.

The second latch circuit 7 latches the count value every rising edge of the PCTL signal, and the arithmetic unit 11
stores the latch data in memory. Further, the third latch circuit 8 latches the count value at every rising edge of the CPG signal, and the arithmetic unit 11 stores the latch data in the memory.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG. 1, and FIG. 2(a) shows the operation button (
(not shown), FIG. 2(b) is the REF signal output from the capstan reference signal generator 1, and FIG. 2(c) is the REF signal output from the capstan reference signal generator 1.
shows a PCTL signal, and FIG. 2(d) shows a CPG signal. In addition, FIG. 2(e) shows the reference latch data, and for each rising edge of one period of the REF signal, R2,
It changes like R1, N1, N2, . . .

A CFG signal is input to the speed detector 4,
Speed detection data DF is detected. At the same time, the CFG signal is input to the frequency divider 9, and the CFG signal is input to the frequency divider 9.
A CPG signal as shown in FIG. 2(d), which has the same frequency as the TL signal but does not have a synchronous relationship, is output. This CPG signal is one of the PCTL signals in the preliminary playback mode.
It is obtained only once during the period in the same period as the PCTL signal,
The signal is input to the third latch circuit 8 as a latch pulse. This third latch circuit 8 latches the count data input at every rising edge of the CPG signal, and outputs this latch data to the arithmetic unit 11.

Furthermore, the mode signal, PCTL signal, and CPG signal input to the arithmetic device 11 are
The contents of the standard data and comparison data output from
It is used as a timing control signal for switching in response to transition from preliminary reproduction mode to recording mode. That is, in the arithmetic unit 11, after time T1 when the mode signal changes from high level to low level, the CPG of FIG.
The count data is latched in the third latch circuit 8 by the signal A of the first pulse of the signals, and until the arithmetic unit 11 stores the latch data in the memory, the process is as shown in FIG. 2(f). Then, the reference latch data R2, R1 outputted from the first latch circuit 6 is output as is as the reference data R2, R1. At the same time, the count data latched by the PCTL signal in the second latch circuit 7 is output as is as comparison data P2, P1, as shown in FIG. 2(g). That is, after time T1, the phase detector 3 operates in the preliminary reproduction mode until the first pulse CPG signal A, and the phase detector 3 operates as shown in FIG.
) and the reference data R2, R1 shown in FIG. 2(f) are output as phase difference detection data DP as shown in FIG. 2(h).

Therefore, the phase difference detection data DP in the preliminary reproduction mode is always RE as shown in FIG. 2(h).
The value A corresponds to the time difference TA between the F signal and the PCTL signal. Note that since the calculation device 11 also calculates the data A corresponding to the time difference TA, it is also possible for the calculation device 11 to perform the function of the phase detector 3.

When the arithmetic unit 11 detects the first CPG signal A after time T1, the count data latched by the third latch circuit 8 and the first latch circuit 6 are A data difference B between the reference latch data N1 latched by the REF signal E immediately before the CPG signal A is calculated. Here, the above-mentioned difference data B is data corresponding to the time difference TB between the REF signal E and the CPG signal A.

By the way, if data B corresponding to the time difference TB obtained by the arithmetic unit 11 and data A corresponding to the time difference TA are used, the latch data latched by the CPG signal after transition to the recording mode can be used as comparison data. It is possible to calculate the value of the reference data corresponding to the case where it is used as

This means that when the latched data in the third latch circuit 8 based on the CPG signal after the first pulse CPG signal A after time T1 is used as comparison data C1 and after, the data difference from the reference data The arithmetic unit 11 calculates and outputs new reference data so that the data A is almost equal to the data A in the preliminary reproduction mode.

That is, the arithmetic unit 11 which stores the reference latch data N1 latched by the REF signal E immediately before the CPG signal A calculates the data shown in FIG. The new reference data NR1 shown in f) is calculated and output based on the following equation. NR1=N1+B-A

If this reference data NR1 is the new reference data immediately after transitioning from the preliminary reproduction mode to the recording mode, the value of the phase difference detection data with the comparison data C1 using the data obtained by latching with the CPG signal A is as follows. , is almost equal to the known data A in the preliminary reproduction mode, so there is almost no change in the phase difference detection data before and after the transition from the preliminary reproduction mode to the recording mode.

Then, the arithmetic unit 11 that has stored the reference latch data N2 latched by the REF signal O following the REF signal E calculates the reference data NR2 by the calculation of N2+B-A. The phase detector 3 uses this reference data NR2 as new reference data and uses data A as phase difference detection data between it and the next comparison data C2 latched by the CPG signal.
Detect. From now on, the above operations are repeated.

As described above, almost the same data A is obtained as the phase difference detection data DP before and after the transition from the preliminary reproduction mode to the recording mode, and this phase difference detection data DP and the rotational speed of the capstan shaft CF that detected
Speed detection data D obtained by inputting the G signal to the speed detector 4
F is input to the deviation amplifier 5, which is composed of a low-pass filter and a summing amplifier, for example, and the capstan shaft for tape running output from the deviation amplifier 5 before and after the transition from the preliminary playback mode to the recording mode. There is almost no change in the control signal that drives the.

In the above explanation, the reference latch data N1 latched by the REF signal E immediately before the CPG signal A, the data A, and the data B are used to
1+B-A was calculated to obtain new data NR1, but since the comparison data C1, which is the latched data in the third latch circuit 8 based on the CPG signal A, is C1=N1+B, only the calculation of NR1 can be performed. Only NR1=C1
-A may be used for calculation. However, for the new reference data NR2 and later, as in the previous explanation, the reference latch data by the REF signal (+B-A)
New reference data is calculated by adding .

By the way, since there is no synchronous relationship between the PCTL signal and the CPG signal, continuous shooting may be performed at the timing shown in FIGS. 3 and 4. First, in FIG. 3, after time T1 which instructs transition from preliminary playback mode to recording mode, R
The reference latch data R1 obtained by latching in the first latch circuit 6 with the EF signal E is stored in the PC in the pre-reproduction state.
The count data latched in the second latch circuit 7 by the TL signal C is used as is as the comparison data P1, as shown in FIG. 3(f).

After time T1, when the first CPG signal A is detected, this CPG signal A causes the count data latched by the third latch circuit 8 and the first CPG signal In the latch circuit 6, a data difference B between the reference latch data R1 latched by the REF signal E immediately before the CPG signal A is calculated. And NR0=R
The data NR0 calculated based on 1+(B-A) is used as the new reference data, and the count data obtained by latching with the CPG signal A is used as the comparison data C shown in FIG. 3(g).
0, phase difference detection data DP that is approximately equal to data A is detected. The reference data NR1 used when the latch data by the CPG signal A following the CPG signal A is used as the comparison data C1 is output by adding (+B-A) to the reference latch data N1 obtained by latching with the REF signal O. be done. In the subsequent steps as well, the above operations are repeated as in the case of FIG. 2, and in this case as well, the same effects as in the embodiment shown in FIG. 2 are achieved.

Next, in the case of FIG. 4, it is assumed that after time T1, a PCTL signal C exists between the first CPG signal A and time T1. The reference latch data N1 obtained by latching with the REF signal E immediately before the CPG signal A is compared with the latch data with the PCTL signal C. P0
In this case, as shown in FIG. 4(f), the data is used as is as the reference data R0. After time T1, data B, which is the difference between the count data latched by the first CPG signal A and the above-mentioned reference latch data N1, is calculated, and NR1 obtained by the calculation of N1+(B-A) is used as the new As reference data, count data latched by CPG signal A is used as comparison data C1. That is,
Even if the PCTL signal comes before the first CPG signal after time T1, the same effect as in the embodiment shown in FIG. 2 can be achieved.

By the way, when transitioning from the preliminary playback mode to the recording mode, the timing to start recording the RCTL signal created by the recording control signal generator 2 on the tape is the same as the transition from the preliminary playback mode to the recording mode. After the time T1 when commanded, the data latched by the first rising edge of the CPG signal A is transferred to the arithmetic unit 11.
Any timing is acceptable as long as the timing is such that the control signal is not lost after the control signal is stored in the internal memory and before and after continuous shooting.

[0041]

As described above, according to the present invention, the capstan position signal of the first pulse obtained by dividing the capstan FG signal after a command to shift from the preliminary reproduction mode to the recording mode. In the preliminary reproduction state that continues until reaching CPG, the reproduced control signal PCTL
and the capstan reference signal REF, and the phase difference B between the CPG signal of the first pulse and the immediately preceding capstan reference signal REF after the command to shift from the preliminary reproduction mode to the recording mode. is calculated, and the phase of the REF signal immediately before the first pulse of the CPG signal is set to (+B-A
) is used as new reference data, and this first pulse CPG signal is input to the phase comparator as comparison data, and the phase difference detection data is used to control the phase of the capstan drive system. Since there is almost no change in the difference between the comparison data input to the phase comparator and the reference data, that is, the phase difference detection data before and after transitioning from preliminary playback to recording, the tape It is possible to almost eliminate running fluctuations, and it is possible to realize highly accurate continuity of the control signal, which is the tape position signal, before and after splicing. As a result, there is almost no change in tracking during playback before and after continuous shooting, and a good playback image can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a capstan drive control system during continuous shooting in a VTR according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of this embodiment.

FIG. 3 is a timing chart for explaining the operation of another embodiment.

FIG. 4 is a timing chart for explaining the operation of another embodiment.

FIG. 5 is a timing chart showing basic operations during continuous shooting.

FIG. 6 is a block circuit diagram showing a capstan drive control system during continuous shooting in a conventional VTR.

FIG. 7 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

1 Capstan reference signal generator 3 Phase detector 4 Speed detector 6 First latch circuit 7 Second latch circuit 8 Third latch circuit 9 Frequency divider 10 Counter 11 Arithmetic device

Claims (2)

[Claims] 1. In a preliminary reproduction state that continues until the first pulse signal obtained by frequency division of the capstan FG signal after a command to transition from the recording pause mode to the preliminary reproduction mode to the recording mode, Means for determining the phase difference A between the capstan reference signal for tape running control synchronized with the position control signal of the rotating drum and the reproduced tape position signal, and means for separating the capstan FG signal after the command to shift to the recording mode. Means for calculating the phase difference B between the first pulse signal and the capstan reference signal immediately preceding it, and the period until calculating the phase difference B are used as a comparison signal with the capstan reference signal. After supplying the phase difference between the playback tape position signal and the playback tape position signal to the capstan drive control system and calculating the phase difference B, the capstan FG signal is separated after issuing a command to transition to the recording mode via the preliminary playback mode. The reference signal obtained by adding (+B-A) to the phase of the capstan reference signal immediately before the first first pulse signal obtained by repeating the rotation and the first first pulse as a comparison signal. 1. A magnetic recording and reproducing apparatus, comprising means for supplying a phase difference between the signal and the capstan drive control system. [Claim 2] The phase difference A and the phase difference B are determined by a single means, or the phase difference A and the phase difference B are determined by a single means and the phase difference between the reference signal and the comparison signal is also detected. The magnetic recording and reproducing apparatus according to claim 1, characterized in that: