JPS63245254A - Switching regulator - Google Patents

Abstract

PURPOSE:To reduce ripple and noise, by limiting the range of pulse width control of each pulse width control circuit within the input period of synchronous pulse signals, and by shifting each input synchronous pulse signal. CONSTITUTION:A switching regulator is composed of the first and second regulator sections 11 and 12 of the same constitution. With a synchronous pulse signal generator 14 two-phase synchronous pulse signals CP1-CP2 in opposite phase each other at 50% of duty are produced, which are supplied to each PWM circuit A1-A2. For the PWM circuits A1-A2 for each regulator section 11 and 12, each pulse width control range is limited within the input period of synchronous pulse signals. No dead time control circuit is required to be added to each regulator section 11 and 12, because the duty is limited to 50%, so that the circuit is simplified and the reliability improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a switching regulator used in, for example, a VTR (video tape recorder).

(Prior art) In a switching regulator with multiple outputs,
If the switching frequency of each regulator section is set individually by a separate oscillation circuit, a beat may occur in the output noise, and the noise may become larger or smaller. Similarly, ripples may also occur. Since the frequency generated by the beat is as low as several hertz to several tens of hertz, it is extremely difficult to attenuate it with a filter, and when used in a VTR, the quality of the video signal may deteriorate.

If control intervals are performed individually in this way, beat formation will occur and affect other circuits, so generally each switching control interval is synchronized.

FIG. 3 shows its configuration, where 11 is a first regulator section, 12 is a second regulator section, and 13 is a synchronizing signal generator. First and second regulator sections 111
2 have the same configuration, and have switching transistors Q that input the same DC voltage V[n and perform switching output.
1, Q2, diodes Di, D2 for smoothing the output voltage of this switching transistor, inductor LiL2 and capacitors C1, C2, switching transistor Q1. By properly controlling the switching pulse width of Q2, the smoothed voltage Vout 1., V
It consists of a pulse width control (PWM') circuit AI, A2 that adjusts each smoothing voltage Voutl,
Vout 2 is designed to be combined and output.

That is, the synchronization signal generator 13 outputs a synchronization signal CPO as shown in FIG. 4(a), and each PWM circuit A
The on time of L and A2 is tl, respectively.

Assuming that the switching transistors Ql and Q2 are set to C2, the on-periods of the switching transistors Ql and Q2 are as shown in FIG. 4(b).
, (c), the on-timing (or off-timing in some cases) is synchronized by inputting a synchronizing signal. In this case, each transistor Q1. Q2 output current II.

■2 is caused by the induced current in inductors LL and L2 as shown in Figure 4 (
As shown in d) and (e), each leg' rake part 11
．． The 12 additional currents 11+12 are as shown in FIG. 4(f).

(Problems to be Solved by the Invention) However, in the conventional switching/7-f switching regulator as described in 1-, the switching timings overlap, so that the transistors are turned on ( There is a disadvantage that the noise generated when (or Yahoo) becomes large and the absolute value of the noise is large. In addition, since the on-time of each regulator section is inevitably different, the peak current of the input current is thicker than the peak current of each regulator section. becomes.

In the circuit shown in Figure 3, since it is a forward chopper type 1/guulator, there is no restriction on the duty of the transistor, or in the case of a boost chopper or a flybeck chopper, it is necessary to limit the duty to about 50%. Therefore, it is necessary to attach a digital time control circuit to each regulator section, resulting in a complicated circuit and low reliability.

This invention was made to solve the above-mentioned problems; it does not generate ripples or noise due to beats, the effective input current is small, and the circuit layout is simple.17.・The purpose is to provide a regulator.

[Structure of the Invention] (7'7. Means for Solving the Problems) In order to achieve the object, the switching regulator according to the present invention includes a switching element that outputs a DC voltage as a switch leg; A plurality of pulse width control circuits include a smoothing circuit that smoothes and outputs the output voltage of the switching element, and a pulse width control circuit that arbitrarily controls the switching pulse width for the switching element to adjust the output voltage of the smoothing circuit. The same two DC voltages are manually applied to the regulator section [7. In the Sui-Sotinge regulator, which obtains an output with a stabilized tQ number by arbitrarily controlling each pulse width control circuit at a fixed synchronization interval, the position where they do not overlap with each other is A synchronous pulse signal h main circuit that generates N number of synchronous pulse signals with non-uniform pulse widths; ,! A pulse width control sub-stage is provided for supplying pulse width control circuits to each pulse width control circuit of the 4-taper section, shifting the synchronous control timing thereof, and limiting the pulse width control range to 1 during the synchronous pulse signal input period. configured.

(Function) The switching regulators and receivers due to the two-j configuration 1 are limited to the pulse width control range of the famous pulse width control circuit or the synchronous pulse signal input period, and are further limited to the pulse width control circuit. Confirmation of input synchronization pulse.

Since the switching elements are separated by 15f', the on-times of the switching elements do not overlap.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a configuration in which the present invention is applied to the circuit shown in FIG. 3. In FIG. 1, the same parts as in FIG. 3 are denoted by the same reference numerals, and the explanation thereof will be omitted.

That is, in this switching regulator, the synchronizing pulse signal generator 14 generates two-phase synchronizing pulse signals (hereinafter referred to as first and second synchronizing pulse signals) CPI with a duty of 50% and mutually opposite phases.

Generating CF2. The first synchronizing pulse signal CP1 is supplied to the PWM circuit AI of the first regulator section 11, and the second synchronizing pulse signal CP2 is supplied to the PWM circuit A2 of the second regulator section 12. Each regulator section 11. The pulse width control range of each of the twelve PWM circuits Al and A2 is limited within the input period of the synchronizing pulse signal.

The operation of the above configuration will be described below with reference to FIG.

That is, the synchronization signal generator 14 operates as shown in FIGS.
), the first and second synchronization signals CPI have a duty of 50% and are mutually opposite in phase.

Generating CF2. Each regulator part AI.

A2 are first and second synchronization pulse signals CPI, respectively;
The pulse width control range is limited by CP2. Here, as in the case shown in FIG. 4, each PWM circuit At
, A2 are set to tl, t2, respectively, the on-periods of the switching transistors Ql and Q2 become as shown in FIG. Synchronization is achieved by inputting CPI and CP2 with a phase shift of 180' from each other. In this case, the output current of each transistor Ql, Q2 is 11. I
2 is the same figure (e) due to the induced current of inductors LL and L2.
, (f), but since the output periods are different, the addition current 11+ of each regulator section 11.12
I2 becomes as shown in the same figure (g).

Therefore, in the switching regulator configured as described above, the switching timings do not overlap, so the ripple in the output voltage is reduced, the noise is also reduced when the transistor is turned on (or off), and the peak current of the input current is Since it does not overlap with the peak current of the regulator section, the effective input current can also be set low. Furthermore, since each PWM circuit is limited to 50% duty of the synchronized pulse signal, there is no need to add a dead time control circuit to each regulator section even if the boost chopper method or flyback chopper method is used, simplifying the circuit. This can contribute to improving credibility.

In the above embodiment, the case where there are two regulator sections has been explained. However, when there are n regulator sections, the synchronizing pulse signal generator 14 has n pulses at different positions and with non-overlapping pulse widths. It is also possible to generate several synchronous pulse signals, input each synchronous pulse signal to the PWM circuit of each regulator section, shift the control timing, and limit the pulse width control range. In addition, when using the same synchronization pulse in multiple units, PWM
A greater effect can be obtained by distributing the pulse width of the circuit.

Furthermore, it goes without saying that the switching transistor is not limited to a bipolar transistor, and may be any other switching element such as a field effect transistor.

[Effects of the Invention] As described above, according to the present invention, there is no generation of ripples or noise due to beats, and the effective input current is small.
A switching regulator with a simple circuit configuration can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the switching regulator according to the present invention, FIG. 2 is a timing waveform diagram for explaining the operation of the embodiment, and FIG. 3 is a circuit diagram showing the configuration of a conventional switching regulator. 4 are timing waveform diagrams for explaining the operation of the conventional circuit. 11.12...Regulator section, 13...Synchronizing signal generator, 14...2-phase synchronous pulse signal generator, Al,
A2...PWM circuit, CPl, CF2...Synchronization pulse signal. Applicant's agent: Takehiko Suzue, former figure 1, figure 2, figure 3

Claims (1)

[Claims] A switching element that switches and outputs a DC voltage,
A plurality of regulator sections each having a smoothing circuit that smoothes and outputs the output voltage of the switching element, and a pulse width control circuit that arbitrarily controls the switching pulse width for the switching element to adjust the output voltage of the smoothing circuit. In a switching regulator that inputs a DC voltage and arbitrarily controls each pulse width control circuit at regular intervals to stabilize the output voltage of each regulator section, multiple A synchronous pulse signal generation circuit that generates a synchronous pulse signal, and a plurality of synchronous pulse signals outputted from the synchronous pulse signal generation circuit are respectively supplied to each pulse width control circuit of the plurality of regulator sections to control the synchronous control timing. A switching regulator comprising pulse width control means for shifting the pulse width and limiting the pulse width control range to a synchronous pulse signal input period.