JP2006304419A - Multiplex power supply system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the generation of ripple components due to interference of switching frequencies when power is supplied to a load by connecting the outputs of a plurality of switching power supplies. <P>SOLUTION: In the multiplex power supply system for supplying a load with power by connecting the outputs of a plurality of switching power supplies 10-1 and 10-2 in parallel, the synchronous output terminals 16a and 16b of a specific switching power supply 10-1 are connected with the synchronous input terminals 18a and 18b of all specific switching power supplies 10-1 and 10-2 by a synchronous signal line 24 and the switching frequency of a switching regulator 54 is synchronized. An oscillation circuit outputs a sine wave oscillation signal having a predetermined switching frequency as a synchronizing signal. Photocouplers 32-1 and 32-2 receive synchronizing signals from the synchronous input terminals 18a and 18b while separating electrically and a clock generation circuits (34-1, 34-2) generate clock pulses from the synchronizing signals thus received. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a multiple power supply system that supplies power to a load by connecting a plurality of switching power supply devices in parallel or in series.

  Conventionally, as a multiple power supply system for supplying power to a load by connecting a plurality of switching power supply devices in parallel, for example, there is the one shown in FIG.

  In FIG. 5, when one switching power supply device cannot supply the current required by the load, the outputs of the switching power supply device 100 and the switching power supply device 102 are connected in parallel as shown in FIG. , 104b supplies power to the load. In this case, the switching power supply devices 100 and 102 may include a circuit for outputting current evenly. Further, the parallel connection of the power supply outputs may be connected by diode OR in addition to the connection as it is as shown in FIG.

Further, when the voltage required by the load cannot be supplied by one switching power supply device, as shown in FIG. 5B, the outputs of the switching power supply device 100 and the switching power supply device 102 are connected in series and output from the output terminals 104a and 104b. Supply power to the load.
JP-A-9-288518 JP 2005-27373 A

  However, in such a multiple power supply system that supplies power to a load by connecting the outputs of a plurality of conventional switching power supply devices in parallel or in series, a case where a plurality of power supply outputs are connected is shown in FIG. As described above, the output ripple voltage ΔV1 due to the switching frequency is generated in the power supply output after the connection, and the component of the difference between the switching frequencies in the two switching power supply devices 100 and 102 causes the interference between the power supply devices to generate the output ripple. There is a problem that appears as voltage ΔV2.

  When the output ripple voltage ΔV2 generated by the interference due to the difference component of the switching frequency is in the audible frequency band, the power supply output current vibrates at the frequency of the interference, so the choke provided in the output smoothing circuit of the switching power supply device There is a problem that the current flowing through the coil also vibrates in the audible frequency band and generates sound in the audible frequency band from the choke coil.

  Further, since the output ripple voltage ΔV2 due to interference has a low frequency, an LC filter that is several tens of times larger than the LC filter that removes the ripple voltage ΔV1 at the switching frequency is necessary to remove the ripple voltage by the LC filter. It is difficult to realize.

  Furthermore, vibrations in the audible frequency band due to interference may adversely affect the user equipment that supplies power. For example, when used as a power source for a mixer that synthesizes an acoustic signal, there is a problem that a frequency component due to interference in an audible frequency band is superimposed on the output of the mixer, and the S / N is greatly impaired.

An object of the present invention is to provide a multiple power supply system that does not generate a ripple component due to interference of switching frequency when outputs of a plurality of switching power supply devices are connected and supplied to a load.

In order to achieve this object, the present invention is configured as follows. The present invention provides a multiple power supply system for supplying power to a load by connecting a plurality of switching power supply devices in parallel or in series.
Each of the switching power supplies
An oscillation circuit that outputs a sinusoidal oscillation signal having a predetermined switching frequency as a synchronization signal;
A synchronization output terminal for outputting a synchronization signal from the oscillation circuit to the outside;
A synchronization input terminal for inputting a synchronization signal;
A photocoupler including a photodiode and a phototransistor for electrically separating and transmitting a synchronization signal input from the synchronization input terminal;
A clock generation circuit for generating a clock pulse from the synchronization signal transmitted by the photocoupler;
A switching power supply circuit that controls the output voltage to a constant voltage by a switching operation based on a clock pulse of the clock generation circuit;
With
The synchronous input terminal of all the switching power supply devices is connected to the synchronous output terminal of the specific switching power supply device by a synchronous signal line.

  Here, each of the synchronous output terminal and the synchronous input terminal is connected in series with a capacitor that separates in a DC manner.

  The multiple power supply system of the present invention includes two sets of photocouplers and clock generation circuits, and two sets of photocouplers are connected in parallel to each other with opposite polarities through a capacitor at a synchronous input terminal. Two systems of clock pulses having a reverse phase relationship are generated from the circuit. In this case, the switching power supply circuit is provided with an active filter on the primary side and a switching regulator on the secondary side, and the outputs of the two clock generation circuits are connected to the insulated switching units of the active filter and the switching regulator.

The clock generation circuit
The emitter of the first PNP transistor is connected to the emitter of a phototransistor whose collector is connected to a power supply line having a predetermined voltage higher than the logic power supply voltage, and the base of the first PNP transistor is connected to the logic power supply voltage line.
Connecting the emitter of the second PNP transistor to the collector of the first PNP transistor and connecting the collector of the second PNP transistor to the ground;
Connect a capacitor between the emitter and collector of the second PNP transistor,
Connect a discharge resistor in parallel with the capacitor,
Connect a charging resistor between the capacitor and ground,
Connect the emitter or base of the second PNP transistor to a pulse output circuit such as a logic IC that outputs a clock pulse;
The first PNP transistor is turned on in accordance with the ON operation of the phototransistor due to the light input, and the second PNP transistor is driven at a constant current by charging the charging current from the capacitor to the charging resistor, thereby interrupting the light input of the phototransistor. The operation of turning off the first PNP transistor and the second PNP transistor is repeated along with the off operation.

  The multiple power supply system according to the present invention further includes a pulse detection circuit that outputs a power supply operation signal to the switching power supply circuit when the generation of the clock pulse by the clock generation circuit is detected.

The multiple power supply system of the present invention has a pair of switching power supply devices by connecting one synchronization input terminal of the pair of switching power supply devices in phase with the synchronization signal line and reversely connecting the other synchronization input terminal to the synchronization signal line. The phase of the clock pulse to be supplied to is set in an anti-phase relationship to cancel the ripple voltage appearing in the output voltage to the load.

  According to the present invention, when supplying power to a load by connecting the outputs of a plurality of switching power supply devices in parallel or in series, a specific switching power supply device is provided by a synchronization signal from an oscillation circuit provided in the specific switching power supply device. And all other switching power supply devices have the same switching frequency, and even if multiple power supply outputs are connected, the ripple voltage generated by the interference of the switching frequency can be eliminated, and the ripple voltage due to the interference is in the audible frequency band. Generation of abnormal noise from the output choke and deterioration of S / N when used in equipment such as a mixer can be prevented.

  In addition, since a plurality of switching power supply devices are connected by an external synchronization signal line and used as a synchronization signal to be supplied, a sine wave synchronization signal is used, so that even if a synchronization signal having a frequency near 100 KHz is supplied to the synchronization signal line, Therefore, the synchronization signal line can be prevented from functioning as an antenna, and the radiation of the harmonic component can be sufficiently reduced.

  In addition, the synchronous output terminal and the synchronous input terminal are each connected to the synchronous signal line through a capacitor in an alternating manner, so that the photocoupler can be protected from destruction even if a direct current is applied due to a connection error with the power output line. it can.

  Photocouplers generally have a narrow frequency band of about 10 KHz, and transmission characteristics in the high frequency band such as 100 KHz necessary for a switching power supply are insufficient. In the present invention, the first PNP transistor is cascade-connected to the photocoupler. By doing so, the high frequency characteristics can be improved.

  Further, the variation in the pulse current due to the variation in the conversion efficiency of the photocoupler can be suppressed by increasing the impedance by driving the second PNP transistor at a constant current as the collector load of the first PNP transistor.

  In addition, by using a PNP transistor as a transistor that is cascade-connected to a phototransistor, a light receiving pulse having a voltage level with respect to the ground can be generated and matched to the input potential of a pulse output circuit such as a logic IC that generates a clock pulse. Can be easily done.

Furthermore, by using a PNP transistor for a transistor driven at a constant current, the voltage at its collector or base corresponds to the input potential of the logic IC that generates the clock pulse, and it can be simplified by a simple protective resistor or voltage dividing resistor. Can be input to a pulse output circuit such as a logic IC.

  FIG. 1 is a circuit block diagram showing an embodiment of a multiple power supply system according to the present invention. In this embodiment, the output of a plurality of switching power supply devices is connected in parallel to supply power to a load. Yes.

  In FIG. 1, the multiple power supply system of the present invention includes switching power supply apparatuses 10-1 and 10-2, for example. Of course, any two or more switching power supply devices can be used as required in addition to the two illustrated. The switching power supply devices 10-1 and 10-2 have input terminals 12a and 12b for inputting DC power, and the input terminals 12a and 12b are followed by 1 in this embodiment. An active filter 52 is provided on the secondary side, a switching regulator 54 is provided on the secondary side, and the output of the switching regulator 54 is connected to the output terminals 14a and 14b.

  The output power supply line 20 is connected to the output terminals 14a and 14b. The output power supply line 20 connects the output terminals 12a and 12b of the other switching power supply apparatus 10-2 in parallel, and the load side is the system output terminals 22a and 22b. Connected to.

  The active filter 52 is a well-known circuit, and performs switching so that the phase of the current waveform matches the phase of the voltage waveform that has been full-wave rectified by switching control to improve the power factor to 1, thereby reducing radiation noise. . The switching regulator 54 performs switching control so that the output voltage is kept constant.

  The switching power supply device 10-1 is provided with synchronous output terminals 16a and 16b and synchronous input terminals 18a and 18b. In this embodiment, the synchronization signal line 24 is drawn out from the synchronization output terminals 16a and 16b of the switching power supply apparatus 10-1, and the synchronization input terminals 18a and 18b of the switching power supply apparatus 10-1 itself are connected to the synchronization signal line 24. The synchronous input terminals 18a and 18b of the other switching power supply device 10-2 are connected.

  An oscillation circuit 25 is provided in the switching power supply device 10-1. The oscillation circuit 25 includes a clock oscillator 26, and oscillates a clock pulse having a frequency corresponding to a predetermined switching frequency, for example, a 100 kHz clock pulse. The oscillation clock of the clock oscillator 26 is input to the filter 28. The filter 28 uses a low-pass filter and converts the clock pulse from the clock oscillator 26 into a sinusoidal signal.

  The sinusoidal oscillation signal from the filter 28 is amplified by the amplifier 30 and then applied to the synchronous output terminal 16a via the resistor R1 and the capacitor C1. The capacitor C1 separates the oscillation circuit 25 from the synchronous output terminal 16a in a DC manner and is connected in an AC manner, and the oscillation circuit is protected from the application of direct current when the output power line 20 or the like is erroneously connected to the synchronous input terminal 18a. 25 destruction is prevented.

  The synchronous input terminals 18a and 18b are connected so that the photodiodes PD1 and PD2 of the photocouplers 32-1 and 32-2 have opposite polarities through a series circuit of a capacitor C2 and a resistor R2. . The capacitor C2 separates the photodiodes PD1 and PD2 of the photocouplers 32-1 and 32-2 from the synchronous input terminal 18a in a DC manner and is connected in an AC manner. The output power line 20 is erroneously connected to the synchronous input terminal 18a. This prevents damage caused by the application of direct current when connecting cables.

  A sine wave oscillation signal is applied to the synchronization input terminals 18a and 18b from the oscillation circuit 25 via the synchronization signal line 24, and a current flows to the photodiode PD1 of the photocoupler 32-1 in the positive half cycle period of the sine wave oscillation signal. Flows and emits light, and in the next negative half-cycle period, a current flows through the photodiode PD2 of the photocoupler 32-2 to emit light.

  A first clock generation circuit 34-1 and a second clock generation circuit 34-2 are provided corresponding to the photocouplers 32-1 and 32-2. The first and second clock generation circuits 34-1 and 34-2 have the same circuit configuration, and the circuit configuration is shown as a representative of the first clock generation circuit 34-1.

  The first clock generation circuit 34-1 is provided with a phototransistor PT1 on the light receiving side of the photocoupler 32-1, and its collector is connected to a power supply terminal 44 that supplies a power supply voltage V1 higher than the logic power supply voltage V2.

  A first PNP transistor 36-1 is cascade-connected to the phototransistor PT1. That is, the emitter of the phototransistor PT1 is connected to the emitter of the first PNP transistor 36-1, and the logic power supply terminal 45 that supplies the logic power supply voltage V2 is connected to the base thereof.

  The cascade connection of the first PNP transistor 36-1 to the phototransistor PT1 compensates for the fact that the high frequency characteristics of the photocoupler 32-1 are insufficient to transmit the switching frequency, and is capable of transmitting, for example, 100 kHz as the switching frequency. Improves high frequency characteristics.

  Following the first PNP transistor 36-1, a second PNP transistor 38-1 operating as a constant current source is cascade-connected. That is, the collector of the first PNP transistor 36-1 is connected to the emitter of the second PNP transistor 38-1, and the collector of the second PNP transistor 38-1 is connected to the ground.

  A capacitor C3 is connected between the collector and base of the second PNP transistor 38-1, and a charging resistor R4 of the capacitor C3 is connected between the base and collector. A discharging resistor R3 is connected in parallel with the capacitor C3.

The 2PNP transistor 38-1, the charging of the capacitor C3 by turning on of the 1PNP transistor 36-1 due to the on-operation by the light receiving phototransistor PT1, a constant current by the base-emitter voltage _{V BE} is substantially constant voltage The constant current load is formed by the second PNP transistor 38-1, thereby increasing the impedance of the load, suppressing variations in pulse current due to variations in the conversion efficiency in the photocoupler 32-1, and suppressing a substantially constant pulse. A current is supplied as a light receiving current.

  Subsequent to the second PNP transistor 38-1, a logic IC 40 that functions as a pulse output circuit that outputs a clock pulse is provided. For example, an amber is used as the logic IC 40. In this embodiment, the voltage at the point B serving as the base of the second PNP transistor 38-1 is input-connected to the input of the logic IC 40 via the protective resistor R5.

  As the voltage input to the logic IC 40, as will be clarified in a later embodiment, the voltage at the point A serving as the emitter of the second PNP transistor 38-1 may be input by resistance voltage division. The pulse voltage at point A or point B input to the logic IC 40 has a voltage level in the vicinity of the logic power supply voltage V2 supplied from the logic power supply terminal 45 at the timing when the phototransistor PT1 is turned off. As a result, the input potential of the received light pulse substantially matches the H level of the input potential of the logic IC 40, and the input circuit of the received light pulse to the logic IC 40 is simplified.

  From the logic IC 40, a clock pulse having a frequency that matches the frequency of the synchronization signal that is a sinusoidal oscillation signal input through the synchronization signal line 24 is output to the clock output terminal 46 and supplied to the active filter 52 to improve the power factor. Used for switching control.

  Further, the light reception pulse voltage at the point B serving as the base of the second PNP transistor 38-1 is input to the pulse detection circuit 42, the generation of the clock pulse by the pulse detection circuit 42 is detected, and the power supply operation signal is output from the power supply operation signal output terminal 48. It is output to the active filter 52. The power supply operation signal from the pulse detection circuit 42 is connected to a dedicated on / off operation terminal provided in the driver IC of the switching element provided in the active filter 52, and the active filter 52 is activated when the power supply operation signal is received. To do.

  The second clock generation circuit 34-2 generates a clock pulse signal from the synchronization signal transmitted using the photocoupler 32-2, and the photodiode PD2 of the photocoupler 32-2 Since the anti-phase connection is made with respect to the diode PD1, a clock pulse that becomes H level in the negative half cycle of the sinusoidal oscillation signal is supplied from the clock output terminal 46 to the switching regulator 54.

  Also, a power supply operation signal is supplied from the power supply operation signal output terminal 48 to the switching regulator 54 by detecting the generation of the clock pulse by the pulse detection circuit, and a dedicated driver IC for controlling on / off of the switching element provided in the switching regulator 54 is used. By supplying the on and off terminals, the switching regulator 54 is activated when the clock pulse generation is detected.

  Next, an embodiment of the operation of FIG. 1 will be described. When predetermined DC power is supplied to the input terminals 12a and 12b of the switching power supply devices 10-1 and 10-2, the oscillation circuit 25 of the switching power supply device 10-1 operates, and the clock pulse from the clock oscillator 26 is filtered. After being converted into a sinusoidal oscillation signal at 28, it is amplified by the amplifier 30, and output to the synchronization signal line 24 from the synchronization output terminals 16a and 16b via the resistor R1 and the capacitor C1.

  The sinusoidal oscillation signal output to the synchronization signal line 24 is input into the devices from the synchronization input terminals 18a and 18b of the switching power supply devices 10-1 and 10-2, and a clock pulse is generated.

  The generation of the clock pulse will be described with respect to the switching power supply device 10-1. In the positive half cycle of the sinusoidal synchronization signal output to the synchronization signal line 24, a current flows through the photodiode PD1 of the photocoupler 32-1 to emit light. Upon receiving this light, the phototransistor PT1 becomes conductive.

  When the phototransistor PT1 starts to conduct, the cascaded first PNP transistor 36-1 is turned on, and accordingly, the capacitor C3 connected between the emitter and base of the second cascaded PNP transistor 38-1 is connected to the charging resistor R4. The second PNP transistor 38-1 is biased to a substantially constant voltage between the base and the emitter. Therefore, the second PNP transistor 38-1 performs a constant current operation, and a substantially constant current flows as a light receiving current while the phototransistor PT1 is conductive.

Due to the constant current operation of the second PNP transistor 38-1, the voltage at the point B drops from the logic power supply voltage V2 until then to the emitter-collector voltage _{VEC (ON)} of the second PNP transistor 38-1, and the input to the logic IC 40. Is changed from H level to L level and, for example, an inverter is used as the logic IC 40, the clock pulse rising from the H level by inversion is output from the clock output terminal 46 to the active filter 52. At the same time, the pulse voltage at point B is detected by the pulse detection circuit 42, and the pulse detection circuit 42 outputs a power supply operation signal to the active filter 52 to start it.

When the light input from the photodiode PD1 to the phototransistor PT1 of the photocoupler 32-1 is cut off, the phototransistor PT1 is turned off, and the first PNP transistor 36-1 connected in cascade is also turned off. This charging of the capacitor C3 is cut off by the capacitor C3 is discharged through the discharging resistor R3, the 2PNP transistor 38-1 by the base-emitter voltage _{V BE} is eliminated also off, the B point for logic IC40 The voltage becomes H level, and the clock pulse from the logic IC 40 falls to L level.

  Thereafter, the output of the clock pulse that becomes the H level is repeated every positive half cycle of the sinusoidal oscillation signal supplied by the synchronization signal line 24.

  On the other hand, in the second clock generation circuit 34-2, the photodiode PD2 of the photocoupler 32-2 emits light during the negative half cycle period of the sinusoidal oscillation signal supplied from the synchronization signal line 24, and the phototransistor PT2 becomes conductive and a clock pulse is output to the switching regulator 54 in the same manner as in the first clock generation circuit 34-1, and at the same time, a power supply operation signal is output to the switching regulator 54 by pulse detection by the pulse detection circuit 42. 54 starts and starts a switching operation.

  Also in the next switching power supply device 10-2, as in the case of the switching power supply device 10-1, a sinusoidal oscillation signal is input from the synchronization signal line 24 to the synchronization input terminals 18a and 18b, thereby passing through the photocoupler. Clock pulses are generated by the first clock generation circuit and the second clock generation circuit, and switching is performed by supplying a clock pulse to the built-in active filter 52 and switching regulator 54 and supplying a power supply operation signal based on the pulse detection. The operation will start.

  FIG. 2 is an explanatory diagram of the ripple voltage of the system power supply output according to the embodiment of FIG. In the multiple power supply system of FIG. 1, each of the switching devices 10-1 and 10-2 uses a sinusoidal oscillation signal having a switching frequency from the oscillation circuit 25 provided in the switching power supply device 10-1 as a synchronization signal. Since the switching operation by the active filter and the switching regulator is performed, the switching frequencies of the switching power supply devices 10-1 and 10-2 are completely the same, and the interference is caused by the difference in the switching frequency between the devices. There is no ripple voltage, and only the ripple voltage ΔV1 associated with the switching control appears in the output voltage.

  For this reason, since there is no ripple voltage due to interference between the switching power supply devices 10-1 and 10-2, the generation of abnormal noise due to the vibration of the output choke coil of the switching regulator 54, or when a mixer or the like is connected as a system load, for example. S / N degradation caused by ripple voltage due to interference in the audible frequency band can be reliably prevented.

FIG. 3 is a time chart of pulse voltage waveforms at points A and B in the first clock generation circuit 34-1 in FIG. FIG. 3A shows the voltage at the point A, that is, the emitter of the second PNP transistor 38-1, and the constant current operation of the second PNP transistor 38-1 in the ON state of the first PNP transistor 36-1 by the optical input of the phototransistor PT1. At this time, the voltage at point A is the voltage V3. This voltage V3 is the collector-emitter voltage V _{CE2 (ON) when the} second PNP transistor 38-1 is on, and is about 0.2 volts.

The voltage at the point A becomes the voltage V4 when the light input to the phototransistor PT1 is cut off and the first PNP transistor 36-1 and the second PNP transistor 38-1 are turned off. This voltage V4 is V4 = V2 + _VBE1 - _{VCE1 (ON)}
= V2 + 0.7 [V] -0.2 [V]
= V2 + 0.5 [V]
It becomes.

FIG. 3B shows the voltage at point B. The voltage at point B is the voltage V5 when the phototransistor PT1 has an optical input, the first PNP transistor 36-1 is turned on, and the second PNP transistor 38-1 is operating at a constant current. This voltage V5 is V5 = _{VCE2 (ON)} + _VBE2
= 0.2 [V]-0.7 [V]
= -0.5 [V]
It becomes.

Further, when the light input to the phototransistor PT1 is cut off and the first PNP transistor 36-1 and the second PNP transistor 38-1 are turned off, the voltage V6 is obtained. This voltage V6 is V6 = V2 + _VBE1 - _{VCE1 (ON) -VBE2}
= V2 + 0.7 [V] -0.2 [V] -0.7 [V]
= V2-0.2 [V]
It becomes.

  Each of the voltage at point A in FIG. 3A and the pulse voltage at point B in FIG. 3B is a voltage that is determined between the voltage substantially matching the logic power supply voltage V2 in the logic IC 40 and the ground level. In the embodiment of FIG. 1, the voltage at point B in FIG. 3B is input to the logic IC 40, and this voltage at point B becomes a negative voltage when the phototransistor PT1 receives an optical input. Although it is V5, it is possible to input a received light pulse in accordance with the logic level of the logic IC 40 as an L level input condition by making an input connection to the logic IC 40 via the protective resistor R5.

  In addition, as for the voltage at point A in FIG. 3A, since the voltage level that becomes the H level exceeds the logic power supply voltage V2, for example, by inputting the voltage at point A to the logic IC 40 by resistance division, It can be easily adapted as a pulse input adapted to the logic level of the IC.

  FIG. 4 is a circuit block diagram showing another embodiment of the multiple power supply system according to the present invention. In this embodiment, the case where outputs of a plurality of switching power supply devices are connected in series is taken as an example. In the embodiment of FIG. 4, the active filter in the embodiment of FIG. 1 is not used, and only the switching regulator is used. Therefore, only one system of clock pulses is generated from the synchronization signal.

  In FIG. 4, the switching power supply devices 10-11 and 10-12 have the same circuit configuration and a circuit configuration representative of the switching power supply device 10-11.

  The switching power supply device 10-11 is provided with a switching regulator 54 following the input terminals 12a and 12b. The output of the switching regulator 54 is connected to the output terminals 14a and 14b. The devices 10-12 are connected in series, and a voltage obtained by adding the output voltages of the plurality of switching power supply devices 10-11, 10-12,... Is supplied from the system output terminals 22a, 22b to the load.

  The switching power supply device 10-11 has synchronous output terminals 16a and 16b, from which a synchronous signal line 24 is drawn to the outside. The synchronous signal line 24 includes the synchronous input terminals 18a and 18b of the switching power supply device 10-11 itself and Synchronous input terminals 18a and 18b of other switching power supply devices 10-12 are connected.

  Here, the connection polarity of the connection of the synchronization input terminals 18a and 18b of the switching power supply apparatus 10-11 to the synchronization signal line 24 and the connection of the synchronization input terminals 18a and 18b of the switching power supply apparatus 10-12 are reversed. Connected to. That is, the synchronization input terminal 18a of the switching power supply device 10-11 is connected to the synchronization signal line 24a from the synchronization output terminal 16a. In the switching power supply device 10-12, the synchronization input terminal 18a is connected to the synchronization signal line 24b. Connected to the side. Further, the synchronization input terminal 18b of the switching power supply 10-11 is connected to the synchronization signal line 24b, but in the switching power supply 10-12, the synchronization input terminal 18b is connected to the synchronization signal line 24a.

  The synchronous input terminals 18a and 18b are connected to the photodiode PD1 of the photocoupler 32 via the capacitor C2 and the resistor R2 in any of the switching power supply devices 10-11 and 10-12. Since the connection polarity with respect to the synchronization signal line 24 is reversed, in the switching power supply 10-11, the photodiode PD 1 emits light in the positive half cycle of the synchronization signal line 24. At -12, the photodiode PD1 emits light in the negative half cycle of the synchronization signal line 24. As a result, the generated clock pulses have a clock phase opposite in the switching power supply devices 10-11 and 10-12.

  A diode D1 is connected in reverse polarity in parallel with the photodiode PD1 of the photocoupler 32, and the diode D1 is turned on for the remaining half cycle with respect to the half-cycle signal for turning on the photodiode PD1, thereby the capacitor C2. Is charging / discharging.

  The oscillation circuit 25 provided in the switching power supply apparatus 10-11 is provided with the sine wave oscillator 56 in this embodiment, and therefore, it is not necessary to provide a filter as in the case of using the clock oscillator of FIG. The sine wave oscillation signal from the sine wave oscillator 56 is amplified by the amplifier 30 and then output to the synchronous output terminals 16a and 16b via the resistor R1 and the capacitor C1.

  Further, only one system is provided for the clock generation circuit 34 because it only needs to supply clock pulses to the switching regulator 54. The configuration of the clock generation circuit 34 has the same configuration and operation as the first clock generation circuit 32-1 of FIG. This also applies to the other switching power supply devices 10-12.

  Next, the operation of the embodiment of FIG. 4 will be described. When DC power is supplied to the input terminals 12 a and 12 b of the switching power supply devices 10-11 and 10-12, the respective oscillation circuits 25 operate, but the switching power supply device 10-11 connected to the synchronization signal line 24. Only the oscillation circuit 25 operates effectively.

  In the oscillation circuit 25, the sine wave oscillator 56 oscillates a sine wave signal, amplifies it by the amplifier 30, and then outputs the sine wave oscillation signal to the synchronization signal line 24 via the resistor R1 and the capacitor C1. The sine wave oscillation signal of the synchronization signal line 24 drives the photodiode PD1 of the photocoupler 32 to emit light from the synchronization input terminals 18a and 18b of the switching power supply devices 10-11 and 10-12.

  In this case, in the switching power supply devices 10-11 and 10-12, since the connection polarity of the synchronization input terminals 18a and 18b with respect to the synchronization signal line 24 is reversed, for example, the photodiode PD1 of the switching power supply device 10-11 is sine. When the half wave of the wave oscillation signal conducts and emits light, the photodiode PD1 of the switching power supply device 10-12 is added with a half cycle of the sine wave oscillation signal of reverse polarity, the diode D1 conducts, and the transmission by the photocoupler Not done.

  Therefore, in this case, only the transmission by the photocoupler 32 provided in the switching power supply apparatus 10-11 is performed, the clock pulse is output from the clock generation circuit 34 to the switching regulator 54, and the power supply operation signal based on the pulse detection is switched at the same time. Output to the regulator 54.

  In the next half cycle of the sine wave synchronization signal, transmission is performed by the photocoupler 32 of the switching power supply apparatus 10-12, and a clock pulse and a power supply operation signal based on the transmission are supplied to the switching regulator. The switching operation of the device 10-12 is performed.

  As a result, the ripple voltage appearing in the output voltage output to the output power supply line 20 connected in series from the output terminals 14a and 14b of the switching power supply devices 10-11 and 10-12 has a phase difference of 180 ° between the two. Therefore, it is canceled by the serial connection, and the ripple voltage at the system output terminals 22a and 22b can be greatly reduced.

  In the above embodiment, the sine wave oscillation signal from the oscillation circuit built in the switching power supply device is used as the synchronization signal, and the clock pulse is generated in each power supply device to perform the switching operation. An oscillation circuit built in the power supply device is not provided, but a clock oscillation circuit for precisely generating a reference clock pulse based on a crystal oscillator or the like is provided outside, and the clock pulse from the external clock oscillation circuit is transmitted through the synchronization signal line 24 to each By supplying to the synchronous input terminals 18a and 18b of the switching power supply device, a switching power supply device that oscillates at a highly accurate switching frequency can be easily configured.

  In the embodiment of FIG. 1, the switching power supply apparatus that requires two systems of clock pulses is connected in parallel to the load, but the same applies to the case of serial connection. In addition, in the switching power supply device that generates two clock pulses in FIG. 1, the connection to the synchronization input terminals 18a and 18b between the pair of switching power supply devices with respect to the synchronization signal line 24 has the opposite polarity as in the embodiment of FIG. By connecting in this manner, the ripple voltage appearing in the output voltage can be canceled and greatly reduced.

  Further, a system using a switching power supply device that requires one system of the clock pulse shown in FIG. 4 can of course have a system configuration in which output terminals are connected in parallel and supplied to a load.

Further, the present invention includes appropriate modifications that do not impair the object and advantages thereof, and is not limited by the numerical values shown in the above embodiments.

A circuit block diagram showing an embodiment of a multiple power supply system according to the present invention in which outputs of a plurality of switching power supply devices are connected in parallel Explanatory diagram of ripple component of output voltage by system of FIG. Time chart of pulse waveforms at points A and B in FIG. The circuit block diagram which showed embodiment of the multiple power supply system by this invention which connected the output of the several switching power supply apparatus in series Block diagram of a conventional multiple power supply system Illustration of ripple component of output voltage by conventional system

Explanation of symbols

10-1, 10-2, 10-11, 10-12: switching power supply devices 12a, 12b: input terminals 14a, 14b: output terminals 16a, 16b: synchronous output terminals 18a, 18b: synchronous input terminals 20: output power supply lines 22a, 22b: system output terminal 24: synchronization signal line 25: oscillation circuit 26: clock oscillator 28: filter 30: amplifiers 32, 32-1, 32-2: photocoupler 34: clock generation circuit 34-1: first clock Generation circuit 34-2: second clock generation circuit 36-1, 36-2: first PNP transistor 38-1, 38-2: second PNP transistor 40: logic IC
42: Pulse detection circuit 44: Power supply terminal 45: Logic power supply terminal 46: Clock output terminal 48: Power supply operation signal output terminal 50: Ground terminal 52: Active filter 54: Switching regulator 56: Sine wave oscillator

Claims (6)

In a multiple power supply system that supplies power to a load by connecting a plurality of switching power supplies in parallel or in series,
Each of the switching power supply devices
An oscillation circuit that outputs a sinusoidal oscillation signal having a predetermined switching frequency as a synchronization signal;
A synchronization output terminal for outputting a synchronization signal from the oscillation circuit to the outside;
A synchronization input terminal for inputting a synchronization signal;
A photocoupler including a photodiode and a phototransistor for electrically separating and transmitting a synchronization signal input from the synchronization input terminal;
A clock generation circuit for generating a clock pulse from the synchronization signal transmitted by the photocoupler;
A switching power supply circuit that controls the output voltage to a constant voltage by a switching operation based on a clock pulse of the clock generation circuit;
With
A multiple power supply system, wherein a synchronization input terminal of all switching power supply devices is connected to a synchronization output terminal of a specific switching power supply device by a synchronization signal line.
2. The multiple power supply system according to claim 1, wherein a capacitor for DC separation is connected in series to each of the synchronous output terminal and the synchronous input terminal.
The multiple power supply system according to claim 1,
Two sets of the photocoupler and the clock generation circuit are provided, and the photodiodes of the two sets of photocouplers are connected in parallel to each other in reverse polarity via a capacitor at the synchronization input terminal. Generate two clock pulses in phase relationship,
The switching power supply circuit is provided with an active filter on the primary side and a switching regulator on the secondary side, and the outputs of the two sets of clock generation circuits are connected to the insulated switching sections of the active filter and the switching regulator. A multiple power supply system characterized by that.
The multiple power supply system according to claim 1, wherein the clock generation circuit includes:
An emitter of a first PNP transistor is connected to an emitter of the phototransistor having a collector connected to a power supply line having a predetermined voltage higher than a logic power supply voltage, and a base of the first PNP transistor is connected to the logic power supply voltage line;
Connecting the emitter of the second PNP transistor to the collector of the first PNP transistor and connecting the collector of the second PNP transistor to the ground;
A capacitor is connected between the emitter and collector of the second PNP transistor;
Connect a discharge resistor in parallel with the capacitor,
Connect a charging resistor between the capacitor and ground,
Connecting the emitter or base of the second PNP transistor to a pulse output circuit for outputting a clock pulse;
As the phototransistor is turned on by light input, the first PNP transistor is turned on and a charging current is supplied from the capacitor to the charging resistor to charge the second PNP transistor, thereby driving the second PNP transistor at a constant current. The multiple power supply system is characterized by repeating the operation of turning off the first PNP transistor and the second PNP transistor in accordance with the off operation due to the interruption of the light input.
2. The multiple power supply system according to claim 1, further comprising a pulse detection circuit that detects generation of a clock pulse by the clock generation circuit and outputs a power supply operation signal to the switching power supply circuit to be activated. Multiple power supply system.
  2. The multiple power supply system according to claim 1, wherein one synchronization input terminal of a pair of switching power supply devices is connected in phase to the synchronization signal line, and the other synchronization input terminal is connected in reverse phase to the synchronization signal line. A multiple power supply system characterized in that the phase of a clock pulse supplied to a pair of switching power supply devices is set in a reverse phase relationship to cancel a ripple voltage superimposed on an output voltage to a load.

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