JP2009273196A - Electric power transmission control apparatus, electric power transmission device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric power transmission control apparatus which attains highly precise waveform detection. <P>SOLUTION: An electric power transmission control apparatus 20 provided in the electric power transmission device of a non-contact power transmission system for supplying power to a load of an electric power reception device by coupling a primary coil L1 and a secondary coil L2 electromagnetically and transmitting electric power from the electric power transmission device 10 to the electric power reception device 40 comprises: a waveform detection circuit 30 for detecting waveform change of a coil end signal CSG which is generated at the coil end node NA2 of the primary coil, and a control circuit 22 for detecting the state of load on the side of the electric power reception device based on the detection results from the waveform detection circuit. The waveform detection circuit has an operational amplifier OP1 which outputs an attenuation signal Sat obtained by attenuating the coil end signal, and detects waveform change of the coil end signal based on the waveform change of the attenuation signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power transmission control device, a power transmission device, an electronic device, and the like.

  In recent years, contactless power transmission (non-contact power transmission) that uses electromagnetic induction and enables power transmission even without a contact of a metal part has been in the spotlight. As an application example of this non-contact power transmission, charging of a mobile phone or a household device (for example, a handset of a phone) has been proposed.

There exists patent document 1 as a prior art of non-contact electric power transmission. In Patent Document 1, data transmission from a power receiving device (secondary side) to a power transmitting device (primary side) is realized by so-called load modulation. And a power transmission apparatus detects the change of the load state by the side of a power receiving (secondary side) accompanying insertion of a foreign material or data transmission by detecting the induced voltage of a primary coil by a comparator etc.
JP 2006-60909 A

  However, in the prior art of this patent document 1, the induced voltage signal input into a power transmission control apparatus was produced | generated by the voltage division by resistance. For this reason, when transmitting high power from the power transmission apparatus to the power reception apparatus, there is a problem that the waveform quality of the induced voltage signal deteriorates due to resistance used for voltage division, parasitic capacitance, and the like.

  According to some aspects of the present invention, it is possible to provide a power transmission control device capable of realizing highly accurate waveform detection, a power transmission device including the power transmission control device, an electronic device, and the like.

  The present invention relates to the non-contact power transmission system in which a primary coil and a secondary coil are electromagnetically coupled to transmit power from a power transmission device to a power reception device and supply power to a load of the power reception device. A power transmission control device provided in a power transmission device, based on a waveform detection circuit that detects a waveform change of a coil end signal generated at a coil end node of the primary coil, and a detection result in the waveform detection circuit, A control circuit that detects a load state on the power receiving device side, and the waveform detection circuit includes an operational amplifier that outputs an attenuation signal obtained by attenuating the coil end signal, and is based on a waveform change of the attenuation signal The present invention relates to a power transmission control device that detects a change in the waveform of the coil end signal.

  According to the present invention, since the waveform detection circuit is provided with the operational amplifier for attenuating the coil end signal, the coil end signal is attenuated. Therefore, based on the waveform change of the attenuation signal output from the operational amplifier, the coil end signal is attenuated. Changes in the waveform of the signal can be detected. Therefore, the waveform change can be detected by attenuating the amplitude of the waveform by the operational amplifier without performing voltage division or the like by the resistor, so that highly accurate waveform detection can be realized.

  In the present invention, the operational amplifier is provided between the coil end node and the input node of the operational amplifier, and between the output node and the input node of the operational amplifier. The coil end signal may be attenuated with an attenuation rate corresponding to a resistance ratio with the second resistor.

  In this way, by adjusting the resistance ratio between the first resistor and the second resistor, an attenuation signal suitable for detecting the load state on the power receiving side can be output.

  In the present invention, the power transmission device includes a waveform monitor circuit provided between the coil end node and the input node, and the first resistor and the second resistor are provided in the waveform monitor circuit. It may be done.

  In this way, since the first resistor and the second resistor are externally attached to the power transmission control device, the power transmission control device can be made compact and the attenuation signal can be easily adjusted.

  In the present invention, the power transmission device includes a waveform monitor circuit provided between the coil end node and the input node, and the first resistor is provided in the waveform monitor circuit, and The resistor may be provided in the waveform detection circuit.

  In this way, the attenuation signal suitable for detecting the load state on the power receiving side by adjusting the resistance ratio between the first resistor in the waveform monitor circuit and the second resistor in the waveform detection circuit. Can be output. Also, the first resistor can be used as a protective resistor for the output terminal of the operational amplifier.

  In the present invention, the operational amplifier may have an inverting input terminal connected to the coil end node and a non-inverting input terminal set to a reference voltage.

  In this way, since the attenuation signal of the coil end signal is output from the operational amplifier with the reference voltage as the center, detection of the load state on the power receiving side becomes stable.

  In the present invention, the waveform detection circuit may be configured such that the attenuation signal changes from the low potential power supply side and exceeds the comparison reference voltage, or the attenuation signal changes from the high potential power supply side and falls below the comparison reference voltage. When any one of the first timing is the first timing, a pulse width period that is a period between the edge timing of the driving clock that defines the driving frequency of the primary coil and the first timing is measured, The pulse width information is detected, and the control circuit may detect a load state on the power receiving side based on the pulse width information.

  In this way, since the load state on the power receiving side is detected based on the change in the pulse width information of the attenuation signal, stable load state detection becomes possible.

  In the present invention, a drive clock generation circuit that generates and outputs a drive clock that defines a drive frequency of the primary coil, and a power transmission that generates a driver control signal based on the drive clock and drives the primary coil A driver control circuit that outputs to the driver, and the waveform detection circuit outputs a pulse signal based on the attenuation signal of the coil end signal, and a pulse width period of the pulse signal. A pulse width detection circuit that detects and outputs pulse width information, and the waveform shaping circuit includes: an operational amplifier; a comparator that compares a voltage level of the attenuation signal with a comparison reference voltage; A pulse signal generation circuit that generates the pulse signal based on the output signal and the drive clock.

  In this way, since the load state on the power receiving side is detected based on the change in the pulse width information of the attenuation signal, the load state on the power receiving side can be detected stably.

  The present invention may further include a reference voltage generation circuit that supplies the reference voltage to the non-inverting input terminal of the operational amplifier and supplies the comparison reference voltage to the comparator.

  In this way, an attenuation signal centered on the reference voltage supplied from the reference voltage generation circuit is output from the operational amplifier, and the pulse signal can be generated by comparing the voltage level of the attenuation signal with the comparison reference voltage. become. Since the reference voltage and the comparison reference voltage are generated by one reference voltage generation circuit, even if the temperature, the power supply voltage, etc. change, the difference between the reference voltage and the comparison voltage is minimized. Can do. Thereby, the detection accuracy of the load state on the power receiving side can be improved.

  In the present invention, the pulse width detection circuit includes a counter that increments or decrements a count value in the pulse width period of the pulse signal and measures the length of the pulse width period based on the obtained count value. It may be included.

  In this way, the pulse width period can be accurately measured by digital processing using a counter.

  In the present invention, the control circuit may perform at least one of foreign object detection, data detection, and removal detection based on the pulse width information from the pulse width detection circuit.

  In this way, based on the pulse width information output from the pulse width detection circuit, foreign object detection, data detection, and removal detection determination can be realized from detection of a change in the load state on the power receiving side.

  According to another aspect of the present invention, there is provided a power transmission device for a non-contact power transmission system in which a primary coil is electromagnetically coupled to a secondary coil of a power reception device to transmit power to the power reception device. The present invention relates to a power transmission device including a device and a waveform monitor circuit provided between a coil end node of the primary coil and an input node of the power transmission control device.

  According to the present invention, since the signal input to the power transmission control device from the waveform monitor circuit that monitors the coil end signal is attenuated, the load state on the power receiving side is detected based on the waveform change of the attenuated signal. Based on the signal component, the accuracy of detection of the load state on the power receiving side is improved.

  In the present invention, the waveform monitor circuit includes a first resistor provided between a coil end node where a coil end signal of the primary coil is generated and an input node of the waveform detection circuit, and the input node. And a reference voltage node, a first diode having a forward direction from the input node to the reference voltage node, and provided between the input node and the reference voltage node, A second diode having a forward direction from a reference voltage node to the input node may be included.

  In this way, even when a signal with a large amplitude that cannot be followed by the operational amplifier is input, the first and second diodes allow the voltage at the input node to fall within a predetermined range from the reference voltage. Therefore, it is possible to protect the input node terminal of the power transmission control device.

  In the present invention, the waveform monitor circuit includes a first resistor provided between a coil end node where a coil end signal of the primary coil is generated and an input node of the waveform detection circuit, and the waveform detection. A Zener diode provided between the input node of the circuit and the reference voltage node and having a forward direction from the reference voltage node to the input node may be included.

  If it does in this way, it will become possible to protect the terminal of the input node of a power transmission control device with a Zener diode.

  In the present invention, the waveform monitor circuit may include a capacitor provided between the coil end node and the first resistor.

  In this way, the DC offset component of the coil end signal can be removed by capacitive coupling by the capacitor, and offset free for the coil end signal can be realized.

  Moreover, this invention relates to the electronic device containing the power transmission apparatus in any one of said.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Electronic Device FIG. 1A shows an example of an electronic device to which the contactless power transmission method of this embodiment is applied. A charger 500 (cradle), which is one of electronic devices, includes a power transmission device 10. In addition, the mobile phone 510 that is one of the electronic devices includes the power receiving device 40. In addition, the mobile phone 510 includes a display unit 512 such as an LCD, an operation unit 514 including buttons, a microphone 516 (sound input unit), a speaker 518 (sound output unit), and an antenna 520.

  Electric power is supplied to the charger 500 via the AC adapter 502, and this electric power is transmitted from the power transmitting device 10 to the power receiving device 40 by contactless power transmission. Thereby, the battery of the mobile phone 510 can be charged or the device in the mobile phone 510 can be operated.

  Note that the electronic device to which the present embodiment is applied is not limited to the mobile phone 510. For example, the present invention can be applied to various electronic devices such as wristwatches, cordless telephones, shavers, electric toothbrushes, wrist computers, handy terminals, portable information terminals, electric bicycles, and IC cards.

  As schematically shown in FIG. 1B, power transmission from the power transmission device 10 to the power reception device 40 is performed on the primary coil L1 (power transmission coil) provided on the power transmission device 10 side and on the power reception device 40 side. This is realized by electromagnetically coupling the secondary coil L2 (power receiving coil) formed to form a power transmission transformer. Thereby, non-contact power transmission becomes possible.

2. FIG. 2 shows a configuration example of the power transmission device 10, the power transmission control device 20, the power reception device 40, and the power reception control device 50 according to the present embodiment. A power transmission-side electronic device such as the charger 500 of FIG. 1A includes the power transmission device 10 of FIG. In addition, a power receiving-side electronic device such as the mobile phone 510 can include the power receiving device 40 and a load 90 (main load). 2, for example, the primary coil L1 and the secondary coil L2, which are planar coils, are electromagnetically coupled to transmit power from the power transmission device 10 to the power reception device 40, and the voltage output of the power reception device 40 is obtained. A non-contact power transmission (non-contact power transmission) system that supplies power (voltage VOUT) from the node NB7 to the load 90 is realized.

  The power transmission device 10 (power transmission module, primary module) can include a primary coil L1, a power transmission unit 12, a waveform monitor circuit 14, a display unit 16, and a power transmission control device 20. The power transmission device 10 and the power transmission control device 20 are not limited to the configuration in FIG. 2, and some of the components (for example, the display unit and the waveform monitor circuit) are omitted, other components are added, Various modifications such as changing the relationship are possible.

  The power transmission unit 12 generates an AC voltage having a predetermined frequency during power transmission, and generates an AC voltage having a different frequency according to data during data transfer, and supplies the AC voltage to the primary coil L1. Specifically, as illustrated in FIG. 3A, for example, when data “1” is transmitted to the power receiving device 40, an alternating voltage of frequency f1 is generated and data “0” is transmitted. In this case, an AC voltage having a frequency f2 is generated. The power transmission unit 12 includes at least a first power transmission driver that drives one end of the primary coil L1, a second power transmission driver that drives the other end of the primary coil L1, and a resonance circuit together with the primary coil L1. One capacitor can be included.

  Each of the first and second power transmission drivers included in the power transmission unit 12 is, for example, an inverter circuit (buffer circuit) configured by a power MOS transistor, and is controlled by the driver control circuit 26 of the power transmission control device 20. .

  The primary coil L1 (power transmission side coil) is electromagnetically coupled to the secondary coil L2 (power reception side coil) to form a power transmission transformer. For example, when power transmission is necessary, as shown in FIGS. 1A and 1B, a mobile phone 510 is placed on the charger 500, and the magnetic flux of the primary coil L1 passes through the secondary coil L2. Make it like this. On the other hand, when power transmission is unnecessary, the charger 500 and the mobile phone 510 are physically separated so that the magnetic flux of the primary coil L1 does not pass through the secondary coil L2.

  The waveform monitor circuit 14 relays the coil end signal CSG generated at the coil end node NA2 of the primary coil L1 to the waveform detection circuit 30. In the present embodiment, the waveform monitor circuit 14 has a function of adjusting the voltage level of the coil end signal CSG within an allowable range that can be detected by the waveform detection circuit 30. That is, the waveform monitor circuit 14 has a function as a protection circuit when the coil end signal CSG exceeds the maximum rated voltage of the IC of the power transmission control device 20 or becomes a negative voltage. Details of the waveform monitor circuit 14 will be described later.

  The display unit 16 displays various states of the contactless power transmission system (during power transmission, ID authentication, etc.) using colors, images, and the like, and is realized by, for example, an LED or an LCD.

  The power transmission control device 20 is a device that performs various controls of the power transmission device 10, and can be realized by an integrated circuit device (IC) or the like. The power transmission control device 20 can include a control circuit 22 (power transmission side), an oscillation circuit 24, a drive clock generation circuit 25, a driver control circuit 26, and a waveform detection circuit 30. In addition, some implementations, such as abbreviate | omitting some of these components and adding another component, are possible.

  The control circuit 22 (control unit) on the power transmission side controls the power transmission device 10 and the power transmission control device 20, and can be realized by, for example, a gate array or a microcomputer. Specifically, the control circuit 22 performs various sequence control and determination processes necessary for power transmission, load state detection (data detection, foreign object detection, removal detection, etc.), frequency modulation, and the like.

  The oscillation circuit 24 is composed of, for example, a crystal oscillation circuit, and generates a primary-side clock signal CLK. The drive clock generation circuit 25 generates a drive clock that defines the drive frequency. The driver control circuit 26 generates a control signal having a desired frequency based on the drive clock, the frequency setting signal from the control circuit 22, and the like, and outputs the control signal to the first and second power transmission drivers of the power transmission unit 12. Then, the first and second power transmission drivers are controlled.

  The waveform detection circuit 30 detects a waveform change of the attenuation signal Sat of the coil end signal CSG of the primary coil L1. For example, when the load state (load current) on the power receiving side (secondary side) changes, the waveform of the attenuation signal Sat changes. The waveform detection circuit 30 detects such a change in waveform and outputs a detection result (detection result information) to the control circuit 22.

  Specifically, the waveform detection circuit 30 shapes the attenuation signal Sat of the coil end signal CSG, for example, and generates a waveform shaping signal. For example, a square wave (rectangular wave) waveform shaping signal (pulse signal) that becomes active (for example, H level) when the attenuation signal Sat exceeds a given threshold voltage is generated. Then, the waveform detection circuit 30 detects pulse width information (pulse width period) of the waveform shaping signal based on the waveform shaping signal and the drive clock. Specifically, the pulse width information of the attenuation signal Sat is detected by receiving the waveform shaping signal and the drive clock from the drive clock generation circuit 25 and detecting the pulse width information of the waveform shaping signal.

  Based on the detection result of the waveform detection circuit 30, the control circuit 22 detects the load state (load fluctuation, load level) on the power receiving side (power receiving device 40 side). Specifically, based on the pulse width information detected by the waveform detection circuit 30 (pulse width detection circuit), the load state on the power receiving side is detected, for example, data (load) detection, foreign object (metal) detection, removal ( Detachment) is performed. That is, the pulse width period that is the pulse width information of the attenuation signal Sat changes according to the change in the load state on the power receiving side. The control circuit 22 detects a load fluctuation on the power receiving side based on the pulse width period (a count value obtained by measuring the pulse width period). Thereby, when the load modulation unit 46 of the power receiving device 40 transmits data by load modulation as shown in FIG. 3B, this transmission data can be detected.

  The power reception device 40 (power reception module, secondary module) can include a secondary coil L2, a power reception unit 42, a load modulation unit 46, a power supply control unit 48, and a power reception control device 50. Note that the power receiving device 40 and the power receiving control device 50 are not limited to the configuration in FIG. 2, and various components such as omitting some of the components, adding other components, and changing the connection relationship. Variations are possible.

  The power receiving unit 42 converts the AC induced voltage of the secondary coil L2 into a DC voltage. This conversion is performed by a rectifier circuit 43 included in the power receiving unit 42. The rectifier circuit 43 includes diodes DB1 to DB4. The diode DB1 is provided between the node NB1 at one end of the secondary coil L2 and the generation node NB3 of the DC voltage VDC, and DB2 is provided between the node NB3 and the node NB2 at the other end of the secondary coil L2. , DB3 is provided between the node NB2 and the VSS node NB4, and DB4 is provided between the nodes NB4 and NB1.

  The resistors RB1 and RB2 of the power receiving unit 42 are provided between the nodes NB1 and NB4. The signal CCMPI obtained by dividing the voltage between the nodes NB1 and NB4 by the resistors RB1 and RB2 is input to the frequency detection circuit 60 of the power reception control device 50.

  The capacitor CB1 and the resistors RB4 and RB5 of the power receiving unit 42 are provided between the node NB3 of the DC voltage VDC and the node NB4 of VSS. A signal ADIN obtained by dividing the voltage between the nodes NB3 and NB4 by the resistors RB4 and RB5 is input to the position detection circuit 56 of the power reception control device 50.

  The load modulation unit 46 performs load modulation processing. Specifically, when desired data is transmitted from the power receiving device 40 to the power transmitting device 10, the load at the load modulation unit 46 (secondary side) is variably changed in accordance with the transmission data, and FIG. ), The signal waveform of the induced voltage of the primary coil L1 is changed. For this purpose, the load modulation unit 46 includes a resistor RB3 and a transistor TB3 (N-type CMOS transistor) provided in series between the nodes NB3 and NB4. The transistor TB3 is ON / OFF controlled by a signal P3Q from the control circuit 52 of the power reception control device 50. When performing load modulation by controlling on / off of the transistor TB3, the transistor TB2 of the power feeding control unit 48 is turned off, and the load 90 is not electrically connected to the power receiving device 40.

  For example, as shown in FIG. 3B, when the secondary side is set to a low load (high impedance) in order to transmit data “0”, the signal P3Q becomes L level and the transistor TB3 is turned off. . As a result, the load of the load modulation unit 46 becomes almost infinite (no load). On the other hand, in order to transmit data “1”, when the secondary side is set to a high load (impedance is low), the signal P3Q becomes H level and the transistor TB3 is turned on. As a result, the load of the load modulation unit 46 becomes the resistance RB3 (high load).

  The power supply control unit 48 controls power supply to the load 90. The regulator 49 adjusts the voltage level of the DC voltage VDC obtained by the conversion in the rectifier circuit 43 to generate the power supply voltage VD5 (for example, 5V). For example, the power reception control device 50 is supplied with the power supply voltage VD5 and operates.

  The transistor TB2 (P-type CMOS transistor) is controlled by a signal P1Q from the control circuit 52 of the power reception control device 50. Specifically, the transistor TB2 is turned on when ID authentication is completed (established) and normal power transmission is performed, and turned off when load modulation is performed.

  The power reception control device 50 is a device that performs various controls of the power reception device 40 and can be realized by an integrated circuit device (IC) or the like. The power reception control device 50 can be operated by a power supply voltage VD5 generated from the induced voltage of the secondary coil L2. The power reception control device 50 can include a control circuit 52 (power reception side), a position detection circuit 56, an oscillation circuit 58, a frequency detection circuit 60, and a full charge detection circuit 62.

  The control circuit 52 (control unit) controls the power reception device 40 and the power reception control device 50, and can be realized by, for example, a gate array or a microcomputer. Specifically, the control circuit 52 performs various sequence control and determination processes necessary for ID authentication, position detection, frequency detection, load modulation, full charge detection, and the like.

  The position detection circuit 56 monitors the waveform of the signal ADIN corresponding to the waveform of the induced voltage of the secondary coil L2, and determines whether the positional relationship between the primary coil L1 and the secondary coil L2 is appropriate. Specifically, the signal ADIN is converted into a binary value by a comparator, or the level is determined by A / D conversion to determine whether the positional relationship is appropriate.

  The oscillation circuit 58 is constituted by a CR oscillation circuit, for example, and generates a secondary clock. The frequency detection circuit 60 detects the frequency (f1, f2) of the signal CCMPI, and as shown in FIG. 3A, whether the transmission data from the power transmission device 10 is “1” or “0”. Judging.

  The full charge detection circuit 62 (charge detection circuit) is a circuit that detects whether or not the battery 94 (secondary battery) of the load 90 is in a fully charged state (charged state).

  The load 90 can include a charge control device 92 that performs charge control of the battery 94 and the like. The charge control device 92 (charge control IC) can be realized by an integrated circuit device or the like. Note that, like a smart battery, the battery 94 itself may have the function of the charging control device 92.

  Next, an outline of the operation on the power transmission side and the power reception side will be described using the flowchart of FIG. When the power transmission side is powered on and powered on (step S1), the power transmission side performs temporary power transmission for position detection (step S2). By this power transmission, the power supply voltage on the power receiving side rises and the reset of the power reception control device 50 is released (step S11). Then, the power receiving side sets the signal P1Q to the H level (step S12). As a result, the transistor TB2 is turned off, and the electrical connection with the load 90 is interrupted.

  Next, the power receiving side uses the position detection circuit 56 to determine whether or not the positional relationship between the primary coil L1 and the secondary coil L2 is appropriate (step S13). If the positional relationship is appropriate, the power receiving side starts an ID authentication process and transmits an authentication frame to the power transmission side (step S14). Specifically, the authentication frame data is transmitted by the load modulation described with reference to FIG.

  When the power transmission side receives the authentication frame, the power transmission side performs determination processing such as whether or not the IDs match (step S3). When the ID authentication is permitted, a permission frame is transmitted to the power receiving side (step S4). Specifically, data is transmitted by the frequency modulation described with reference to FIG.

  The power receiving side receives the permission frame and, if the content is OK, transmits a start frame for starting contactless power transmission to the power transmitting side (steps S15 and S16). On the other hand, the power transmission side receives the start frame and starts normal power transmission when the content is OK (steps S5 and S6). Then, the power receiving side sets the signal P1Q to the L level (step S17). As a result, both transistors TB2 are turned on, so that power transmission to the load 90 becomes possible, and power supply to the load (output of VOUT) starts (step S18).

3. Power Transmission Control Device FIG. 5 shows a configuration example of the power transmission control device 20 of this embodiment. Note that the power transmission control device 20 of the present embodiment is not limited to the configuration of FIG. 5, and some of the components (for example, a latch circuit, a voltage detection circuit, a waveform shaping circuit) are omitted, or other components Various modifications, such as adding, are possible.

  In FIG. 5, when the inductance of the primary coil L1 and the capacitance value of the capacitor constituting the resonance circuit vary, the power supply voltage fluctuates, or the distance and positional relationship between the primary coil L1 and the secondary coil L2 fluctuate, The peak voltage (amplitude) of the input node Nin of the detection circuit 30 also varies. Therefore, there is a possibility that accurate detection of the load variation cannot be realized only by the method of detecting the peak voltage of the input node Nin. Therefore, in the present embodiment, the load is detected by detecting the pulse width information of the attenuation signal Sat of the coil end signal CSG generated at the coil end node NA2 of the primary coil L1 with the circuit configuration shown in FIG. Fluctuation is detected.

  The power transmission control device 20 controls the power transmission drivers (first and second power transmission drivers) of the power transmission unit 12 that drives the primary coil L1. Further, the power transmission control device 20 is connected to the coil end node NA2 of the primary coil L1 via the waveform monitor circuit 14, and the waveform change of the attenuation signal Sat of the coil end signal CSG generated at the coil end node NA2. Thus, the load state on the power receiving side (secondary side) is detected.

  As shown in FIG. 5, the power transmission control device 20 of this embodiment includes an oscillation circuit 24, a drive clock generation circuit 25, a driver control circuit 26, a waveform detection circuit 30, and a control circuit 22.

  The drive clock generation circuit 25 generates a drive clock DRCK that defines the drive frequency of the primary coil L1. Specifically, the reference clock signal CLK generated by the oscillation circuit 24 is divided to generate the drive clock DRCK. The primary coil L1 is supplied with an AC voltage having a driving frequency of the driving clock DRCK.

  The driver control circuit 26 generates a driver control signal based on the drive clock DRCK and outputs the driver control signal to the power transmission driver of the power transmission unit 12 that drives the primary coil L1. In this case, the signal input to the gate of the P-type transistor of the inverter circuit and the signal input to the gate of the N-type transistor are non-overlapping so that no through current flows through the inverter circuit constituting the power transmission driver. A driver control signal is generated so as to become a signal.

  The waveform monitor circuit 14 is provided between the coil end node NA2 where the coil end signal CSG of the primary coil L1 is generated and the input node Nin of the waveform detection circuit 30 and is generated at the coil end node NA2. The end signal CSG is relayed to the waveform detection circuit 30. The waveform monitor circuit 14 is provided with a first diode DA1 between the input node Nin and the reference voltage node Vref1 that has a forward direction from the input node Nin to the reference voltage node Vref1. A second diode DA2 having a forward direction from the reference voltage node Vref1 to the input node Nin is provided between the input node Nin and the reference voltage node Vref1.

  In this embodiment, as will be described later, since the input node Nin is set to the reference voltage Vref by an imaginary short, the first and second diodes DA1 and DA2 have functions of limit operation and half-wave rectification. The first operational amplifier OP1 functions as a protection circuit when a signal having a large amplitude that cannot be followed is input. In other words, the waveform monitor circuit 14 clamps the voltage at the input node Nin so that the first and second diodes DA1 and DA2 are within a predetermined range from the reference voltage Vref1, whereby the waveform detection circuit of the power transmission control device 20 is used. 30 input terminals are protected. In the present embodiment, a capacitor CA is provided on the input stage side of the waveform monitor circuit 14 in order to cancel the DC offset.

  The waveform detection circuit 30 detects a waveform change of the attenuation signal Sat of the coil end signal CSG generated at the coil end node NA2 of the primary coil L1. In the present embodiment, the waveform detection circuit 30 detects the pulse width period of the pulse signal WFQ based on the waveform shaping circuit 32 that outputs the pulse signal WFQ based on the attenuation signal Sat of the coil end signal CSG, and outputs the pulse width information PWQ. And a pulse width detection circuit 33 for outputting.

  The waveform shaping circuit 32 shapes the attenuation signal Sat of the coil end signal CSG of the primary coil L1, and outputs a waveform shaping signal WFQ. Specifically, for example, a square wave (rectangular wave) waveform shaping signal WFQ that becomes active (eg, H level) when the attenuation signal Sat of the coil end signal CSG exceeds a given threshold voltage is output. .

  In the present embodiment, the waveform shaping circuit 32 is provided with a first operational amplifier OP1 on the input stage side, and a second operational amplifier OP2, a comparator COM, and an AND circuit AND (pulse signal generation circuit) are provided on the subsequent stage. Is provided.

  The first operational amplifier OP1 is provided on the input stage side of the waveform shaping circuit 32, and its inverting input terminal is connected to the coil end node NA2 via the waveform monitoring circuit 14, and its non-inverting input terminal is the first inverting input terminal. The reference voltage Vref1 is set. The output node NA12 of the first operational amplifier OP1 is fed back to the input node Nin of the inverting input terminal of the first operational amplifier OP1. Therefore, the input node Nin is set to the first reference voltage Vref1 by the imaginary short function of the first operational amplifier OP1. As a result, the voltage level of the coil end signal CSG of the primary coil L1 is attenuated and output from the first operational amplifier OP1 as the attenuation signal Sat.

In the present embodiment, the second resistor RA2 is provided between the output node NA12 of the first operational amplifier OP1 and the input node Nin. A first resistor RA1 is provided between the coil end node NA2 and the input node Nin of the first operational amplifier OP1. In this embodiment, as shown in the following formula (1), the coil end signal CSG is attenuated with an attenuation rate set by the resistance ratio between the first resistor RA1 and the second resistor RA2. That is, by adjusting the resistance ratio between the first resistor RA1 and the second resistor RA2, an attenuation signal Sat suitable for detecting the load state on the power receiving side is output.
Sat = − (RA2 / RA1) CSG (1)

  In the present embodiment, the first resistor RA1 and the second resistor RA2 are provided in the waveform monitor circuit 14 provided between the coil end node NA2 and the input node Nin. That is, the first resistor RA1 and the second resistor RA2 are external to the power transmission control device 20. For this reason, the power transmission control device 20 can be made compact, and the attenuation signal Sat can be easily adjusted. Note that the first resistor RA1 is provided in the waveform monitor circuit 14 and the second resistor RA2 is provided in the waveform detection circuit 30, and the first resistor RA1 is a protective resistor for the output terminal of the first operational amplifier OP1. It may be possible to use both as

  The second operational amplifier OP2 is provided at the subsequent stage of the first operational amplifier OP1, and the attenuation signal Sat output from the first operational amplifier OP1 is input to the non-inverting input terminal of the second operational amplifier OP2. . The output node NA13 of the second operational amplifier OP2 is fed back to the inverting input terminal of the second operational amplifier OP2, and the attenuation signal Sat is further attenuated by the imaginary short function of the second operational amplifier OP2. Is output.

  The comparator COM is provided at the subsequent stage of the second operational amplifier OP2, compares the voltage level of the attenuation signal Sat attenuated by the second operational amplifier OP2 with the comparison reference voltage Vref2, and outputs the comparison result CPQ. . In the present embodiment, when the voltage level of the attenuation signal Sat is equal to or higher than the comparison reference voltage Vref2, an output signal CPQ that is an active voltage level (for example, H level) is output.

  An AND circuit AND (pulse signal generation circuit) calculates a logical product of the output signal CPQ of the comparator COM and the drive clock DRCK, and generates a pulse signal WFQ as a waveform shaping signal. That is, when the voltage level of the output signal CPQ of the comparator COM is an active voltage level (eg, H level) and the drive clock DRCK is an active voltage level (eg, H level), the active voltage level (eg, H level). ) Is output. In this way, the pulse signal WFQ based on the attenuation signal Sat of the coil end signal CSG is output.

  The pulse width detection circuit 33 has a function of detecting the pulse width information PWQ of the attenuation signal Sat of the coil end signal CSG of the primary coil L1. Specifically, the pulse signal WFQ (waveform shaping signal) is received from the waveform shaping circuit 32, and, for example, during the period in which the pulse signal WFQ is at an active voltage level (eg, H level), the oscillation circuit 24 (see FIG. 5). ) To detect the pulse width information PWQ based on the counter value obtained by the counting process using the reference clock signal CLK generated in step (1).

  Based on the pulse width information PWQ detected by the pulse width detection circuit 33, the control circuit 22 detects a load fluctuation (load level) on the secondary side (power receiving device 40 side). Specifically, the control circuit 22 detects data transmitted by the power receiving device 40 by load modulation based on the pulse width information detected by the pulse width detection circuit 33. Alternatively, detection of an overload state such as foreign object detection or removal detection (detachment detection) may be performed.

  6A and 6B show the measurement results of the coil end voltage waveform of the primary coil L1. 6A and 6B show voltage waveforms when the load current on the power receiving side is 150 mA and 300 mA, respectively. The pulse width period TPW in which the coil end voltage is equal to or higher than a given set voltage VR becomes shorter as the load current becomes larger (as the load becomes higher). Therefore, by measuring the pulse width period TPW, it is possible to determine the level of the load of the load modulation unit 46 of the power receiving device 40, and whether the transmission data from the power receiving side is “0” or “1”. I can judge. For example, as shown in FIG. 3B, it is assumed that “0” is defined when the load is low and “1” is defined when the load is high. In this case, if the pulse width period TPW is longer than a given reference pulse width period, the load is low, so it can be determined as “0”, and if it is short, it can be determined as “1” because the load is high. .

  FIG. 7 schematically shows the relationship between the drive clock DRCK (drive control signal) and the coil end voltage waveform. The drive clock DRCK becomes H level (active) at timing t21 and becomes L level (inactive) at timing t22. On the other hand, the coil end voltage rises sharply at timing t21 when the drive clock DRCK becomes H level, and then falls. As shown in FIG. 7, the lower the load on the power receiving side, the more slowly the coil end voltage falls. For this reason, the pulse width period in which the coil end voltage (induced voltage signal) is equal to or higher than a given set voltage becomes longer as the load on the power receiving side becomes lower. Therefore, by measuring this pulse width period, it is possible to determine whether the load on the power receiving side is low load, medium load, high load, or overload.

  As the set voltage VR for measuring the pulse width period (for example, a voltage of 0 V or higher, a voltage higher than the threshold voltage of the N-type transistor), a voltage that optimizes the load fluctuation detection accuracy is appropriately selected and set. That's fine.

  FIG. 8A shows an equivalent circuit on the primary side when there is no load, and FIG. 8B shows an equivalent circuit when there is a load. As shown in FIG. 8A, when there is no load, a series resonance circuit is formed by the capacitance C, the primary side leakage inductance L11, and the coupling inductance M. Therefore, as indicated by B1 in FIG. 8C, the resonance characteristic at no load is a sharp characteristic having a high Q value. On the other hand, in the case of a load, a secondary side leakage inductance Ll2 and a secondary side load resistance RL are added. Therefore, as shown in FIG. 8B, the resonance frequencies fr2 and fr3 in the case of load are larger than the resonance frequency fr1 in the case of no load. In addition, due to the influence of the resistance RL, the resonance characteristic under load is a gentle characteristic with a low Q value. Further, as the load becomes low (large RL) and high load (RL small), the resonance frequency increases and the resonance frequency approaches the coil drive frequency (DRCK frequency).

  When the resonance frequency approaches the drive frequency in this way, as shown in FIGS. 6A and 6B, a sine wave portion that is a resonance waveform gradually appears. That is, in the voltage waveform at the time of low load as shown in FIG. 6A, the square wave that is the drive waveform is more dominant than the sine wave that is the resonance waveform. On the other hand, in the voltage waveform at the time of high load as shown in FIG. 6B, the sine wave that is the resonance waveform is more dominant than the square wave that is the drive waveform. As a result, the pulse width period TPW in which the coil end voltage is equal to or higher than the set voltage VR becomes shorter as the load becomes higher. Therefore, by measuring the pulse width period TPW, it is possible to determine the fluctuation (high or low) of the load on the power receiving side with a simple configuration.

  For example, a method of judging the load fluctuation on the power receiving side based on the phase characteristics due to the load is also conceivable. Here, the phase characteristic due to the load indicates a voltage / current phase difference. However, this method has a problem that the circuit configuration is complicated and the cost is increased.

  On the other hand, the pulse width detection method of the present embodiment has an advantage that the circuit configuration can be simplified because it can be processed as digital data by using a simple waveform shaping circuit and a counting circuit (counter) using a voltage waveform. . Further, there is an advantage that it is easy to realize a combination with an amplitude detection method for detecting a load variation using a voltage waveform.

  FIG. 9 shows a detailed configuration example of the waveform detection circuit 30 of the power transmission control device 20 of the present embodiment. In particular, FIG. 9 shows a specific configuration example of the Halth width detection circuit 33.

  The power transmission control device 20 includes a waveform detection circuit 30 that detects a waveform change of the attenuation signal Sat of the coil end signal CSG of the primary coil L1. The waveform detection circuit 30 includes a waveform shaping circuit 32 and a pulse width detection circuit 33.

  The waveform shaping circuit 32 shapes the attenuation signal Sat of the coil end signal CSG of the primary coil L1, and outputs a waveform shaping signal WFQ. Specifically, for example, a square wave (rectangular wave) waveform shaping signal WFQ (pulse signal) that becomes active (eg, H level) when the attenuation signal Sat exceeds a given threshold voltage is output.

  As described above, in the present embodiment, the waveform shaping circuit 32 is provided with the first operational amplifier OP1, the second operational amplifier OP2, the comparator COM, and the AND circuit AND. Among these, the reference voltage Vref1 is supplied from the reference voltage generation circuit 19 to the non-inverting input terminal of the first operational amplifier OP1, and the comparison reference voltage Vref2 having a magnitude different from that of the reference voltage Vref1 is supplied to the comparator COM. Supplied from the voltage generation circuit 19.

  As described above, the attenuation signal Sat centered on the reference voltage Vref1 supplied from the reference voltage generation circuit 19 is output from the first operational amplifier OP1, and the voltage level of the attenuation signal Sat is compared with the comparison reference voltage Vref2. The pulse signal WFQ can be generated based on the obtained output data CPQ. That is, since the reference voltage Vref1 and the comparison reference voltage Vref2 are generated by one reference voltage generation circuit 19, the difference between the reference voltage Vref1 and the comparison reference voltage Vref2 varies even if the temperature, the power supply voltage, etc. change. Can be minimized. For this reason, the detection accuracy of the load state on the power receiving side by the power transmission control device 20 can be improved.

  The pulse width detection circuit 33 has a function of detecting the pulse width information PWQ of the attenuation signal Sat of the coil end signal CSG of the primary coil L1. Specifically, the pulse signal WFQ (waveform shaping signal) is received from the waveform shaping circuit 32, and, for example, during the period in which the pulse signal WFQ is at an active voltage level (eg, H level), the oscillation circuit 24 (see FIG. 5). ) To detect the pulse width information PWQ based on the counter value obtained by the counting process. In the present embodiment, the pulse width detection circuit 33 includes a counter 122, a counter value holding circuit 124, and an output circuit 126, as shown in FIG.

  The counter 122 increments (or decrements) the count value during the pulse width period, and measures the length of the pulse width period based on the obtained count value CNT. In this case, the counter 122 performs count processing of the count value CNT based on the reference clock signal CLK generated by, for example, the oscillation circuit 24 (see FIG. 5). That is, the pulse width period of the pulse signal WFQ can be accurately measured by digital processing using the counter 122.

  The count value holding circuit 124 functions as a latch circuit that holds a count value CNT that is a measurement result by the counter 122. Then, the data LTQ of the count value CNT held by the count value holding circuit 124 is output to the output circuit 126.

  The output circuit 126 (filter circuit, noise removal circuit) receives the data LTQ of the count value CNT held in the count value holding circuit 124 and outputs data PWQ serving as pulse width information. The output circuit 126 includes, for example, a comparison circuit 130 that compares the count value currently held in the count value holding circuit 124 with the count value held last time and outputs the larger count value. . By providing the comparison circuit 130 in this way, the output circuit 126 constantly holds and outputs the maximum count value. This makes it possible to suppress fluctuations in the pulse width period due to noise or the like, and to realize stable pulse width detection. Further, the combination with the amplitude detection method can be facilitated.

  Next, operation | movement of the waveform shaping circuit 32 of the power transmission control apparatus 20 of this embodiment is demonstrated, using drawing. FIGS. 10A and 10B show signal waveform examples for explaining the operation of the waveform shaping circuit of this embodiment. In FIG. 10A, CSG1 shows a waveform example of the coil end signal when there is a load, and CSG2 shows a waveform example of the coil end signal when there is no load. In FIG. 10B, Sat1 shows a waveform example of the attenuation signal of the coil end signal when there is a load, and Sat2 shows a waveform example of the attenuation signal of the coil end signal when there is no load.

  The coil end signal CSG of the primary coil L1 is used as the first operational amplifier as an attenuation signal Sat whose voltage level is attenuated by the imaginary short function of the first operational amplifier OP1 installed on the input stage side of the waveform shaping circuit 32. Output from OP1. That is, the voltage levels of the loaded coil end signal CSG1 and the unloaded coil end signal CSG2 shown in FIG. 10A are attenuated and reduced in waveform around the reference voltage Vref1, and shown in FIG. 10B. An attenuation signal Sat1 when there is a load and an attenuation signal Sat2 when there is no load.

  As in the prior art, in the voltage division by the resistance included in the rectifier circuit, the waveform of the attenuation signal Sat of the coil end signal CSG has been distorted, but the operational amplifier OP1 is used as in this embodiment. In the attenuation of the coil end signal CSG, as shown in FIG. 10B, an attenuation signal Sat centered on the reference voltage Vref1 is output from the first operational amplifier OP1. As described above, in this embodiment, even if the waveform of the coil end signal CSG is reduced, the attenuation signal Sat having good linearity that does not distort the waveform of the attenuation signal Sat can be obtained, so that the load state detection on the power receiving side is stabilized. become.

  The waveform of the coil end signal CSG is reduced by the imaginary short function of the first operational amplifier OP1, and then the comparator COM compares the voltage level of the attenuation signal Sat with the comparison reference voltage Vref2, and outputs the comparison result CPQ. To do. As described above, in this embodiment, when the voltage level of the attenuation signal Sat is equal to or higher than the comparison reference voltage Vref2, the output signal CPQ that becomes the active voltage level (H level) is output. As shown in FIG. 6, the attenuation signal Sat1 when there is a load is output as CPQ1, and the attenuation signal Sat2 when there is no load is output as CPQ2. If the pulse waveform of the comparison result CPQ is accurately reproduced, the target waveform is centered on the reference voltage Vref1. Therefore, if the comparison reference voltage Vref2 is set near the reference voltage Vref1, the sensitivity of pulse detection Will improve.

  Next, the comparison results CPQ1 and CPQ2 output from the comparator COM are supplied to the AND circuit AND, and the AND of the comparison results CPQ1 and CPQ2 and the drive clock DRCK is calculated in the AND circuit AND. As described above, in this embodiment, when the voltage level of the output signal CPQ of the comparator COM is the active voltage level (H level) and the drive clock DRCK is the active voltage level (H level), the active voltage level A pulse signal WFQ that becomes (H level) is output.

  Therefore, when the logical product of the comparison result CPQ1 and the drive clock DRCK when there is a load is calculated, as shown in FIG. 10B, the calculation of the H level A1 and B1 of CPQ1 and the H levels CKA and CKB of DRCK The result is a pulse signal WFQ1. On the other hand, when the logical product of the comparison result CPQ2 at no load and the drive clock DRCK is calculated, as shown in FIG. 10B, the calculation result of the H level A2, B2 of CPQ2 and the H level CKA, CKB of DRCK Becomes the pulse signal WFQ2.

  When the pulse signal WFQ output from the waveform shaping circuit 32 is input to the subsequent pulse width detection circuit 33, the counter 122 increments (or decrements) the count value during the pulse width period, and the obtained count value is obtained. The length of the pulse width period is measured based on CNT. When measuring the pulse width, for example, when counting the pulse width when there is a load, the state T2 in which WFQ1 is at the H level is directly counted, or the state T1 in which WFQ1 is at the L level is counted, By subtracting T1 from the pulse width T of DRCK, T2 is calculated. As described above, in this embodiment, the pulse width period of the pulse signal WFQ can be accurately measured by digital processing using the counter 122.

  The counter processing result CNT in the counter 122 is then held in the count value holding circuit 124, and then the data LTQ of the count value CNT is output to the output circuit 126. The output circuit 126 receives the data LTQ of the count value CNT held in the count value holding circuit 124, and outputs data PWQ serving as pulse width information to the control circuit 22.

  FIG. 12 is a flowchart for explaining primary foreign object detection and secondary foreign object detection by the power transmission device of this embodiment.

  First, the primary side (power transmission device side) is activated (step S21), and the activated primary side transmits power for activating the secondary side (position detection power) (step S22), and waiting for communication. The state is shifted (step S23). Then, the secondary side (power receiving device side) is activated (step S31), and an authentication frame (synchronization ID) is transmitted to the primary side by load modulation (step S32).

  When the primary side receives the authentication frame, it performs ID authentication (step S24). Then, the drive frequency (DRCK frequency) is set to the foreign object detection frequency F2, which is a frequency different from the normal power transmission frequency F1. Specifically, the foreign object detection frequency F2 which is a frequency between the normal power transmission frequency F1 and the coil resonance frequency F0 is set.

  Then, the primary side performs primary foreign object detection in a state where the drive frequency is set to the foreign object detection frequency F2 in this way (step S26). Specifically, the primary foreign object detection is performed by the waveform detection circuit 30 performing waveform detection.

  Next, the primary side sets the drive frequency to the normal power transmission frequency F1 and starts normal power transmission (step S27), whereby the secondary side receives power (step S33).

  After the normal power transmission starts in this way, the secondary side performs secondary foreign object detection (step S28). Specifically, secondary foreign object detection is performed by the second waveform detection circuit 32 performing waveform detection. In this case, it is desirable to perform secondary foreign object detection periodically after normal power transmission starts.

  Then, when the full charge of the load is detected, the secondary side notifies the end of normal power transmission (step S34), and thereby the primary side ends normal power transmission (step S29).

  In FIG. 12, primary foreign matter detection is performed, for example, in a no-load state before the start of normal power transmission. The primary foreign matter detection is performed by a method of detecting the load state on the power receiving side based on the waveform change of the attenuation signal Sat of the coil end signal CSG. Accordingly, even when there is a power supply voltage fluctuation or the like, stable foreign object detection is possible, and the pulse width count obtained in the primary foreign object detection can be set as a reference value. Based on the reference value in the no-load state, secondary foreign matter detection after normal power transmission can be performed, and “0” and “1” of data transmitted from the power receiving side can be detected. Load variation can be detected.

  As described above, in the present embodiment, the control circuit 22 can realize the determination of foreign object detection, data detection, and removal detection based on the pulse width information PWQ from the pulse width detection circuit 33.

  As described above, in the present embodiment, the waveform detection circuit 30 is provided with the first operational amplifier OP1 that attenuates the coil end signal CSG, so that the coil end signal CSG is attenuated. The waveform change of the coil end signal CSG can be detected based on the waveform change of the attenuation signal Sat. At this time, the attenuation signal Sat of the coil end signal CSG is output from the first operational amplifier OP1 around the reference voltage Vref1, and the load on the power receiving side is determined based on the change in the pulse width information of the attenuation signal Sat. Since the state is detected, the detection of the load state becomes stable.

4). Waveform monitor circuit 4.1. First Configuration Example FIG. 13 shows a first configuration example of the waveform monitor circuit 14 of the present embodiment. The waveform monitor circuit 14 is provided between the coil end node NA2 where the coil end signal CSG of the primary coil L1 is generated and the input node Nin of the waveform detection circuit 30 and is generated at the coil end node NA2. The end signal CSG is relayed to the waveform detection circuit 30.

  The waveform monitor circuit 14 is provided with a first diode DA1 between the input node Nin and the reference voltage node Vref1 that has a forward direction from the input node Nin to the reference voltage node Vref1. A second diode DA2 having a forward direction from the reference voltage node Vref1 to the input node Nin is provided between the input node Nin and the reference voltage node Vref1.

  In the present embodiment, as described above, the input node Nin is set to the reference voltage Vref by an imaginary short performed by the first arithmetic circuit OP1, so that the first and second diodes DA1 and DA2 are so-called. It does not have a limit operation by a rectifier circuit or a half-wave rectifier function. The waveform monitor circuit 14 of the present embodiment is configured so that the first and second diodes DA1 and DA1 when a signal having a large amplitude that cannot be followed by the inverting input terminal of the first operational amplifier OP1 of the waveform shaping circuit 32 is input. DA2 functions as a protection circuit that cuts signal components that exceed an allowable range that can be followed by the inverting input terminal of the operational amplifier OP1.

That is, the first diode DA1 clamps the voltage Vin at the input node Nin so as not to exceed the range of the magnitude of the forward voltage VF from the reference voltage Vref1, as shown in the following equation (2).
Vin ≤ Vref1 + VF (2)

On the other hand, the second diode DA2 clamps the voltage at the input node Nin so as to be equal to or larger than the value obtained by subtracting the forward voltage VF from the reference voltage Vref1, as shown in the following equation (3). .
Vin ≧ Vref1−VF (3)

  In this way, the waveform monitor circuit 14 of this embodiment clamps the voltage at the input node Nin so that the first and second diodes DA1 and DA2 are within a predetermined range from the reference voltage Vref1, thereby transmitting power. The inverting input terminal of the operational amplifier OP1 that serves as the input terminal of the waveform detection circuit 30 of the control device 20 is protected. The waveform monitor circuit 14 includes a first resistor RA1 that is a current limiting resistor provided between the coil end node NA2 of the primary coil L1 and the input node Nin of the waveform detection circuit 30. Thus, by providing the current limiting resistor RA1, a situation where an excessive current from the coil end node NA2 flows into the IC terminal of the power transmission control device 20 is prevented.

  Further, in the first configuration example, a capacitor CA is provided on the input stage side of the waveform monitor circuit 14. Specifically, the capacitor CA is provided between the coil end node NA2 and the first resistor RA1. The coil end signal CSG may not have a center voltage of 0 V but may have a DC offset. When the DC offset fluctuates, the pulse width of the pulse signal obtained by shaping the voltage signal Sin varies, and the load state detection accuracy decreases. Therefore, in order to cancel such a DC offset, a capacitor CA is provided on the input stage side of the waveform monitor circuit 14 in the first configuration example.

  As described above, by providing the capacitor CA, it is possible to prevent only the AC component of the coil end signal from being extracted, and even when the DC offset of the coil end signal fluctuates, the adverse effect of the load state detection accuracy can be prevented. . In other words, the DC coupling component of the coil end signal CSG can be removed by capacitive coupling by the capacitor CA, and the offset free for the coil end signal CSG can be realized.

  It is also possible to shift the voltage level of the coil end signal to a voltage level with high detection sensitivity that is easy to detect with a desired threshold voltage. Therefore, the detection accuracy such as the pulse width of the pulse signal obtained by shaping the attenuation signal Sat of the coil end signal CSG generated at the coil end node NA2 is improved, and the load state is detected with high sensitivity and high dynamic range. Etc. can be realized.

4.2. Second Configuration Example FIG. 14 shows a second configuration example of the waveform monitor circuit 14. In the second configuration example, a Zener diode DZ1 is provided instead of providing the diode DA1 of FIG. That is, a Zener diode is provided between the monitor node NA11 and the reference voltage node Vref1, and the forward direction is from the reference voltage node Vref1 to the input node Nin. For this reason, the Zener diode DZ1 can protect the terminal of the input node Nin of the power transmission control device 20. Similarly to the first configuration example, a capacitor CA is provided on the input stage side of the waveform monitor circuit 14 in order to cancel the DC offset.

4.3. Comparative Example FIG. 15 shows a comparative example of the waveform monitor circuit 14 of this embodiment. In FIG. 15, the waveform monitor circuit 141 includes a second rectifier circuit 181 in addition to the first rectifier circuit 171. The waveform detection circuit 30 includes first and second waveform detection circuits 31 and 34.

  The first waveform detection circuit 31 detects a waveform change of the first induced voltage signal PHIN1 of the primary coil L1. The second waveform detection circuit 34 detects a waveform change of the second induced voltage signal PHIN2 of the primary coil L1.

  The second rectifier circuit 181 outputs a second induced voltage signal PHIN2 for waveform monitoring to the second waveform detection circuit 32 via the second monitor node NA21. Specifically, the rectifier circuit 181 includes a second resistor RA21 that is a current limiting resistor provided between the coil end node NA2 and the monitor node NA21, and a monitor node NA21 and a GND (low potential power supply) node. A third resistor RA31 provided therebetween is included. Further, it includes a third diode DA31 provided between the monitor node NA21 and the GND node. Then, the voltage of the coil end signal CSG is divided by the resistors RA21 and RA31 and is input to the second waveform detection circuit 32 as the induced voltage signal PHIN2. Further, the diode DA31 performs half-wave rectification of the coil end signal CSG so that a negative voltage is not applied to the second waveform detection circuit 32.

  As described above, in the comparative example, circuits having different configurations, such as rectifier circuits 171 and 181, are used as circuits for generating the induced voltage signals PHIN 1 and PHIN 2 for the first and second waveform detection circuits 31 and 34. Therefore, as indicated by E1 in FIG. 16, the first waveform detection circuit 31 detects a pulse width period XTPW1 corresponding to a phase change at the rising portion of the induced voltage signal PHIN1 (coil end signal CSG). That is, as shown in E2 when the induced voltage signal PHIN1 changes from 0V, a pulse width period XTPW1 that is a period between the timing when the threshold voltage VT1 is exceeded and the edge timing of the drive clock DRCK is measured. Therefore, in this case, since it is only necessary to detect the vicinity of 0 V, the waveform reduction is unnecessary, and voltage division by the resistors RA21 and RA31 like the rectifier circuit 181 in FIG.

  Here, the signal PHIN1 may exceed the maximum rated voltage of the power transmission control device 20 unless the waveform is reduced by voltage division using a resistor in this way. In this respect, the rectifier circuit 171 is provided with a diode DA11, and the diode DA11 performs a limit operation for clamping the signal PHIN1 to the voltage VDD as shown by E3, so that the signal PHIN1 exceeds the maximum rated voltage. Can be prevented. Further, the rectifier circuit 171 is provided with a diode DA21, and the diode DA21 performs half-wave rectification as indicated by E4, so that a negative voltage is applied to the IC terminal of the power transmission control device 20. Can also be prevented.

  On the other hand, the second waveform detection circuit 32 detects a pulse width period XTPW2 corresponding to the phase change at the falling portion of the induced voltage signal PHIN2 (coil end signal CSG) as indicated by G1. That is, as shown in G2 when the induced voltage signal PHIN2 changes from the voltage on the VDD side, the pulse width period XTPW2 that is the period between the timing when the threshold voltage VT2 is lowered and the edge timing of the drive clock DRCK is measured. . Therefore, it is necessary to reduce the waveform of the coil end signal CSG that becomes a voltage exceeding VDD, and for this purpose, the rectifier circuit 181 performs voltage division using the resistors RA21 and RA31. Specifically, by dividing the coil end signal CSG and reducing the waveform, for example, the threshold voltage of an N-type transistor can be used as the threshold voltage VT2. The rectifier circuit 181 is provided with a diode DA31, and this diode DA31 performs half-wave rectification as indicated by G3, so that a negative voltage is applied to the IC terminal of the power transmission control device 20. Can also be prevented.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (GND, VDD, mobile phone / charger, etc.) described together with different terms (low-potential power supply, high-potential power supply, electronic device, etc.) in a broader sense or the same meaning at least once The different terms can be used anywhere in the specification or drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configuration and operation of the power transmission control device, the power transmission device, the power reception control device, the power reception device, and the pulse width detection method are not limited to those described in the present embodiment, and various modifications can be made.

1A and 1B are explanatory diagrams of contactless power transmission. 1 is a configuration example of a power transmission device, a power transmission control device, a power reception device, and a power reception control device of the present embodiment. 3A and 3B are explanatory diagrams of data transfer by frequency modulation and load modulation. The flowchart for demonstrating the outline | summary of operation | movement of the power transmission side and the power receiving side. The structural example of the power transmission control apparatus of this embodiment. 6A and 6B are signal waveform examples for explaining the operation of the waveform monitor circuit. The signal waveform example for demonstrating operation | movement of a waveform monitor circuit. FIG. 8A to FIG. 8C are equivalent circuits and resonance characteristic diagrams when there is no load and when there is a load. The detailed structural example of the power transmission control apparatus of this embodiment. 10A and 10B are signal waveform examples for explaining the operation of the waveform shaping circuit. Explanatory drawing of the relationship between pulse width information and the load condition of a receiving side. The flowchart for demonstrating a primary foreign material detection and a secondary foreign material detection. 1 is a first configuration example of a waveform monitor circuit of the present embodiment. 2 shows a second configuration example of a waveform monitor circuit according to the present embodiment. Comparison example of waveform monitor circuit. The signal waveform example for demonstrating operation | movement of the comparative example of a waveform monitor circuit.

Explanation of symbols

AND pulse signal generation circuit, CA capacitor, COM comparator,
DA1, DA2 diode, L1 primary coil, L2 secondary coil,
OP1 operational amplifier, RA1 first resistor, RA2 second resistor,
DESCRIPTION OF SYMBOLS 10 Power transmission apparatus, 12 Power transmission part, 14 Waveform monitor circuit, 16 Display part,
17, 18 rectifier circuit, 19 reference voltage generation circuit, 20 power transmission control device,
22 control circuit (power transmission side), 24 oscillation circuit, 25 drive clock generation circuit,
26 driver control circuit, 30 waveform detection circuit, 32 waveform shaping circuit,
33 pulse width detection circuit, 40 power receiving device, 42 power receiving unit, 43 rectifier circuit,
46 load modulation unit, 48 power supply control unit, 50 power reception control device,
52 control circuit (power receiving side), 56 position detection circuit, 58 oscillation circuit,
60 frequency detection circuit, 62 full charge detection circuit, 90 load, 92 charge control device,
94 battery, 122 counter, 124 count value holding circuit, 126 output circuit, 130 comparison circuit

Claims (15)

Provided in the power transmission device of the non-contact power transmission system that electromagnetically couples the primary coil and the secondary coil to transmit power from the power transmission device to the power reception device and supplies power to the load of the power reception device. A power transmission control device,
A waveform detection circuit for detecting a waveform change of a coil end signal generated at a coil end node of the primary coil;
A control circuit for detecting a load state on the power receiving device side based on a detection result in the waveform detection circuit,
The waveform detection circuit includes:
A power transmission control apparatus comprising: an operational amplifier that outputs an attenuation signal obtained by attenuating the coil end signal, and detecting a waveform change of the coil end signal based on a waveform change of the attenuation signal. In claim 1,
The operational amplifier is
According to a resistance ratio of a first resistor provided between the coil end node and the input node of the operational amplifier and a second resistor provided between the output node of the operational amplifier and the input node A power transmission control device, wherein the coil end signal is attenuated by an attenuation factor. In claim 2,
The power transmission device is:
A waveform monitor circuit provided between the coil end node and the input node;
The power transmission control device, wherein the first resistor and the second resistor are provided in the waveform monitor circuit. In claim 2,
The power transmission device is:
A waveform monitor circuit provided between the coil end node and the input node;
The first resistor is provided in the waveform monitor circuit,
The power transmission control device, wherein the second resistor is provided in the waveform detection circuit. In any one of Claims 1 thru | or 4,
The operational amplifier is
The inverting input terminal is connected to the coil end node, and the non-inverting input terminal is set to a reference voltage. In any one of Claims 1 thru | or 5,
The waveform detection circuit includes:
Either the timing when the attenuation signal changes from the low potential power supply side and exceeds the comparison reference voltage, or the timing when the attenuation signal changes from the high potential power supply side and falls below the comparison reference voltage is set as the first timing. A pulse width information is detected by measuring a pulse width period that is a period between an edge timing of a driving clock that defines a driving frequency of the primary coil and the first timing;
The control circuit includes:
A power transmission control device that detects a load state on a power receiving side based on the pulse width information. In any one of Claims 1 thru | or 5,
A drive clock generation circuit that generates and outputs a drive clock that defines the drive frequency of the primary coil;
A driver control circuit that generates a driver control signal based on the drive clock and outputs the driver control signal to a power transmission driver that drives the primary coil;
Further including
The waveform detection circuit includes:
A waveform shaping circuit that outputs a pulse signal based on the attenuation signal of the coil end signal;
A pulse width detection circuit that detects a pulse width period of the pulse signal and outputs pulse width information;
The waveform shaping circuit is
The operational amplifier;
A comparator for comparing the voltage level of the attenuation signal with a comparison reference voltage;
A pulse signal generation circuit that generates the pulse signal based on the output signal of the comparator and the drive clock;
A power transmission control device comprising: In claim 7,
The power transmission control device further comprising: a reference voltage generation circuit that supplies the reference voltage to a non-inverting input terminal of the operational amplifier and supplies the comparison reference voltage to the comparator. In claim 7 or 8,
The pulse width detection circuit
A power transmission control device comprising: a counter that increments or decrements a count value in the pulse width period of the pulse signal and measures the length of the pulse width period based on the obtained count value. In any one of Claims 7 thru | or 9,
The control circuit includes:
A power transmission control device that performs at least one of foreign object detection, data detection, and removal detection based on the pulse width information from the pulse width detection circuit. A power transmission device of a contactless power transmission system that electromagnetically couples a primary coil to a secondary coil of a power reception device and transmits power to the power reception device,
A power transmission control device according to any one of claims 1 to 10,
A waveform monitor circuit provided between a coil end node of the primary coil and an input node of the power transmission control device;
A power transmission device comprising: In claim 11,
The waveform monitor circuit includes:
A first resistor provided between a coil end node where a coil end signal of the primary coil is generated and an input node of the waveform detection circuit;
A first diode provided between the input node and a reference voltage node and having a forward direction from the input node to the reference voltage node;
A power transmission apparatus comprising: a second diode provided between the input node and the reference voltage node and having a forward direction from the reference voltage node to the input node. In claim 11,
The waveform monitor circuit includes:
A first resistor provided between a coil end node where a coil end signal of the primary coil is generated and an input node of the waveform detection circuit;
A power transmission device including a Zener diode provided between an input node and a reference voltage node of the waveform detection circuit and having a forward direction from the reference voltage node to the input node. In claim 12 or 13,
The waveform monitor circuit includes:
A power transmission device comprising a capacitor provided between the coil end node and the first resistor.   An electronic device comprising the power transmission device according to claim 11.

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