JP4525790B2 - Power transmission device, electronic device and waveform monitor circuit - Google Patents

Description

  The present invention relates to a power transmission device, an electronic device, and a waveform monitor circuit.

  In recent years, contactless power transmission (non-contact power transmission) that uses electromagnetic induction and enables power transmission even without a contact of a metal part has been in the spotlight. As an application example of this non-contact power transmission, charging of a mobile phone or a household device (for example, a handset of a phone) has been proposed.

There exists patent document 1 as a prior art of non-contact electric power transmission. In Patent Document 1, data transmission from a power receiving device (secondary side) to a power transmitting device (primary side) is realized by so-called load modulation. And a power transmission apparatus detects the change of the load state by the side of a power receiving (secondary side) accompanying insertion of a foreign material or data transmission by detecting the induced voltage of a primary coil by a comparator etc.
JP 2006-60909 A

  However, in the prior art of this patent document 1, the induced voltage signal input into a power transmission control apparatus was produced | generated by the voltage division by resistance. Therefore, the voltage division reduces the waveform, and there is a problem that the load state detection accuracy cannot be improved.

  The present invention has been made in view of the technical problems as described above, and an object thereof is to provide a power transmission device, an electronic device, and the like having a waveform monitor circuit suitable for a non-contact power transmission system. It is in.

  The present invention is a power transmission device of a non-contact power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power to a power receiving device and supplies power to a load of the power receiving device. Based on the coil end signal of the primary coil, a waveform monitor circuit that generates and outputs an induced voltage signal for waveform monitoring, and a power transmission driver that drives the primary coil, and a waveform monitoring circuit A power transmission control device that receives the induced voltage signal and detects a change in the waveform of the induced voltage signal to detect a load state on the power receiving side, and the waveform monitor circuit generates a coil end signal of the primary coil A first resistor which is a current limiting resistor provided between a coil end node and a first monitor node where a first induced voltage signal for waveform monitoring is generated, and the first induced voltage High power signal It performs a limiter operation that clamps the power supply voltage, related to the power transmitting device including a first rectifier circuit having a limiter function of performing half-wave rectification for the first induced voltage signal.

  According to the present invention, the waveform monitoring circuit generates an induced voltage signal for waveform monitoring based on the coil end signal of the primary coil, and outputs it to the power transmission control device. The current control resistor provided in the first rectifier circuit of the waveform monitor circuit can prevent a situation in which an excessive current from the coil end node flows into the power transmission control device. The first rectifier circuit included in the waveform monitor circuit clamps the induced voltage signal to the high-potential power supply voltage, thereby preventing a situation where a voltage higher than the maximum rated voltage is applied to the power transmission control device. The first rectifier circuit performs half-wave rectification, so that a situation where a negative voltage is applied to the power transmission control device can be prevented.

  In the present invention, the first rectifier circuit is provided between the first monitor node and the high-potential power node, and the direction from the first monitor node to the high-potential power node is a forward direction. And a second diode having a forward direction from the low potential power supply node to the first monitor node. The second diode is provided between the first monitor node and the low potential power supply node. A diode may be included.

  By providing such a first diode, the limit operation of the first rectifier circuit can be realized, and by providing such a second diode, half-wave rectification of the first rectifier circuit can be realized.

  In the present invention, the first rectifier circuit is provided between the first monitor node and a low-potential power node, and a direction from the low-potential power node to the first monitor node is a forward direction. A Zener diode may be included.

  In this way, the limit operation can be realized without providing the first diode.

  In the present invention, the first rectifier circuit is provided between the first monitor node and the high-potential power node, and the direction from the first monitor node to the high-potential power node is a forward direction. And a second diode having a forward direction from the low potential power supply node to the first monitor node. The second diode is provided between the first monitor node and the low potential power supply node. A diode, a low-potential-side resistance end node between the first resistor and the second diode, and a first capacitor provided between the coil end node may be included.

  In this way, the DC offset component of the coil end signal can be removed by capacitive coupling by the first capacitor, and offset free for the coil end signal can be realized.

  In the present invention, the power transmission control device includes a waveform detection circuit that detects a waveform change of the induced voltage signal of the primary coil, and the waveform detection circuit includes the first induced voltage signal of the primary coil. A first waveform detection circuit for detecting a waveform change; and a second waveform detection circuit for detecting a waveform change of a second induced voltage signal of the primary coil, wherein the waveform monitor circuit includes the first monitor The first rectifier circuit that outputs the first induced voltage signal for waveform monitoring to the first waveform detection circuit via the node, and the second monitor node via the second monitor node A second rectifier circuit that outputs the second induced voltage signal for waveform monitoring to the waveform detection circuit may be included.

  In this way, the first and second induced voltage signals suitable for the first and second waveform detection circuits can be generated by the first and second rectifier circuits.

According to the present invention, the second rectifier circuit includes a second resistor provided between the coil end node and the second monitor node, and between the second monitor node and the low potential power supply node. A third resistor provided between the second monitor node and the low-potential power supply node, and a direction from the low-potential power supply node to the second monitor node is a forward direction. 3 diodes may be included.

  In this way, the second induced voltage signal obtained by reducing the waveform of the coil end signal can be output to the power transmission control device.

  In the present invention, the power transmission control device generates a drive clock that generates and outputs a drive clock that defines a drive frequency of the primary coil, generates a driver control signal based on the drive clock, and A driver control circuit that outputs to a power transmission driver that drives the next coil; and a control circuit that detects a load state on the power receiving side based on a detection result of the waveform detection circuit; When the first induced voltage signal changes from the low potential power supply side and exceeds the first threshold voltage as the first timing, the first waveform detection circuit 1 A first pulse width detection circuit that detects a first pulse width information by measuring a first pulse width period that is a period between an edge timing and the first timing; Control circuit, based on the first pulse width information, may be detected load state of the power receiving side.

  According to the present invention, the first pulse width period, which is the period between the first edge timing (for example, falling edge or rising edge timing) of the drive clock and the first timing, is measured, and the first Is detected as pulse width information. Based on the detected first pulse width information, the load state on the power receiving side is detected. In this way, it is possible to stably detect the load fluctuation on the power receiving side without adopting a method in which the voltage and current are individually detected and determined based on the phase difference. Therefore, it is possible to properly detect the load fluctuation on the secondary side with a simple configuration. Further, in the present invention, the first timing is a timing at which the first induced voltage signal changes from the low potential power supply side and exceeds the first threshold voltage, so that it is resistant to disturbances such as the power supply voltage. Pulse width detection with little variation can be realized.

  In the present invention, the first waveform detection circuit includes a first waveform shaping circuit that shapes the first induced voltage signal and outputs a first waveform shaping signal, the first pulse The width detection circuit may measure the first pulse width period based on the first waveform shaping signal and the drive clock.

  In this way, it is possible to measure the first pulse width period by digital processing using the signal waveform-shaped by the first waveform shaping circuit and the drive clock.

  In the present invention, the first pulse width detection circuit increments or decrements a count value in the first pulse width period, and the length of the first pulse width period is based on the obtained count value. A first counter that counts may be included.

  In this way, the first pulse width period can be accurately measured by digital processing using the first counter.

  In the present invention, the control circuit may perform primary foreign object detection, which is foreign object detection before the start of normal power transmission, based on the first pulse width information.

  In this way, primary foreign object detection can be realized, for example, in a no-load state before the start of normal power transmission.

  Also, in the present invention, the second waveform detection circuit determines that a timing at which the second induced voltage signal of the primary coil changes from the high potential power supply side and falls below the second threshold voltage is a second timing. In this case, a second pulse for detecting second pulse width information by measuring a second pulse width period that is a period between the second edge timing of the drive clock and the second timing. A width detection circuit may be included, and the control circuit may perform secondary foreign object detection, which is foreign object detection after the start of normal power transmission, based on the second pulse width information.

  In this way, foreign objects can be detected with different standards before the start of normal power transmission and after the start of normal power transmission, and the accuracy and stability of foreign object detection can be improved.

  In the present invention, the second waveform detection circuit includes a second waveform shaping circuit that shapes the second induced voltage signal and outputs a second waveform shaping signal, the second pulse The width detection circuit may measure the second pulse width period based on the second waveform shaping signal and the drive clock.

  In this way, it is possible to measure the second pulse width period by digital processing using the signal waveform-shaped by the second waveform shaping circuit and the drive clock.

  In the present invention, the second pulse width detection circuit increments or decrements a count value in the second pulse width period, and the length of the second pulse width period is based on the obtained count value. A second counter may be included for measuring.

  In this way, the second pulse width period can be accurately measured digitally using the second counter.

  In the present invention, the first waveform detection circuit performs waveform shaping on the first induced voltage signal and outputs the first waveform shaping signal to the first pulse width detection circuit. A second waveform shaping circuit that shapes the second induced voltage signal different from the first induced voltage signal and converts the second waveform shaped signal to the second pulse width. You may output to a detection circuit.

  In this manner, the first method using the first waveform shaping circuit and the first pulse width detection circuit and the second method using the second waveform shaping circuit and the second pulse width detection circuit. The pulse width detection can be realized by using the first and second induced voltage signals having different signal states, and the accuracy and stability of the pulse width detection can be improved.

  In the present invention, the power transmission control device includes a waveform detection circuit that detects a waveform change of the induced voltage signal of the primary coil, and the waveform detection circuit includes the first induced voltage signal of the primary coil. A first waveform detection circuit for detecting a waveform change; and a second waveform detection circuit for detecting a waveform change of a second induced voltage signal of the primary coil, wherein the waveform monitor circuit includes the first monitor The first rectifier circuit that outputs the first induced voltage signal for waveform monitoring to the first waveform detection circuit via the node, and the second monitor node via the second monitor node A second rectifier circuit that outputs the second induced voltage signal for waveform monitoring to a waveform detection circuit; and the first rectifier circuit is provided between the first monitor node and a high-potential power supply node. And the first monitor node A first diode having a forward direction toward the high-potential power supply node as a forward direction; provided between the first monitor node and the low-potential power supply node; and from the low-potential power supply node to the first monitor node A first diode provided between the second diode whose forward direction is the direction toward, a low-potential-side resistance end node between the second resistor and the second diode, and the coil end node. The second rectifier circuit is provided between the second monitor node and the high potential power supply node, and has a direction from the second monitor node toward the high potential power supply node. A third diode that is forward-oriented, and provided between the second monitor node and the low-potential power node, and a forward direction from the low-potential power node to the second monitor node. Four An ion, a second resistor provided between the third diode and the second monitor node, and a third resistor provided between the second monitor node and the low-potential power supply node. And a high-potential side resistance end node between the third diode and the second resistor, and a second capacitor provided between the coil end node.

  As described above, if the first and second capacitors are provided, the DC offset of the coil end signal can be removed, and the offset free for the coil end signal can be realized.

  In the present invention, the power transmission control device generates a drive clock that generates and outputs a drive clock that defines a drive frequency of the primary coil, generates a driver control signal based on the drive clock, and A driver control circuit that outputs to a power transmission driver that drives the next coil; and a control circuit that detects a load state on the power receiving side based on a detection result of the waveform detection circuit; When the first induced voltage signal changes from the low potential power supply side and exceeds the first threshold voltage as the first timing, the first waveform detection circuit 1 Including a first pulse width detection circuit that measures a first pulse width period, which is a period between an edge timing and the first timing, and detects first pulse width information; It may be.

  In this way, it is possible to stably detect the load fluctuation on the power receiving side without adopting a method in which the voltage and current are individually detected and determined based on the phase difference. Therefore, it is possible to properly detect the load fluctuation on the secondary side with a simple configuration. Further, in the present invention, the first timing is a timing at which the first induced voltage signal changes from the low potential power supply side and exceeds the first threshold voltage, so that it is resistant to disturbances such as the power supply voltage. Pulse width detection with little variation can be realized.

  Also, in the present invention, the second waveform detection circuit determines that a timing at which the second induced voltage signal of the primary coil changes from the high potential power supply side and falls below the second threshold voltage is a second timing. In this case, a second pulse for detecting second pulse width information by measuring a second pulse width period that is a period between the second edge timing of the drive clock and the second timing. A width detection circuit may be included.

  By doing this, the waveform of the coil end signal is reduced, and the second pulse width information is obtained by comparing the voltage level of the second induced voltage signal after the waveform reduction with the second threshold voltage. Is possible.

  Moreover, this invention relates to the electronic device containing the power transmission apparatus in any one of said.

  The present invention also relates to a power transmission device of a contactless power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power to a power receiving device and supplies power to a load of the power receiving device. A waveform monitor circuit for providing a coil end signal for generating a coil end signal of the primary coil and a first monitor node for generating a first induced voltage signal for waveform monitoring A first resistor that is a current limiting resistor that performs a limiter operation that clamps the first induced voltage signal to a high-potential power supply voltage and performs a half-wave rectification on the first induced voltage signal, A first rectifier circuit with a limiter function that outputs one induced voltage signal to the power transmission control device of the power transmission device, the coil end node, and a second induced voltage signal for waveform monitoring is generated. 2 monitors A second resistor that is a current limiting resistor provided between the second monitor node and the low potential power supply node, the second monitor node, A third diode which is provided between the low potential power supply node and has a forward direction from the low potential power supply node to the second monitor node. The second induced voltage signal is The present invention relates to a waveform monitor circuit including a second rectifier circuit that outputs to a power transmission control device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Electronic Device FIG. 1A shows an example of an electronic device to which the contactless power transmission method of this embodiment is applied. A charger 500 (cradle) which is one of electronic devices has a power transmission device 10. A mobile phone 510 that is one of the electronic devices includes a power receiving device 40. The mobile phone 510 includes a display unit 512 such as an LCD, an operation unit 514 including buttons and the like, a microphone 516 (sound input unit), a speaker 518 (sound output unit), and an antenna 520.

  Electric power is supplied to the charger 500 via the AC adapter 502, and this electric power is transmitted from the power transmitting device 10 to the power receiving device 40 by contactless power transmission. Thereby, the battery of the mobile phone 510 can be charged or the device in the mobile phone 510 can be operated.

  Note that the electronic apparatus to which this embodiment is applied is not limited to the mobile phone 510. For example, the present invention can be applied to various electronic devices such as wristwatches, cordless telephones, shavers, electric toothbrushes, wrist computers, handy terminals, portable information terminals, electric bicycles, and IC cards.

  As schematically shown in FIG. 1B, power transmission from the power transmission device 10 to the power reception device 40 is performed on the primary coil L1 (power transmission coil) provided on the power transmission device 10 side and on the power reception device 40 side. This is realized by electromagnetically coupling the secondary coil L2 (power receiving coil) formed to form a power transmission transformer. Thereby, non-contact power transmission becomes possible.

2. FIG. 2 shows a configuration example of the power transmission device 10, the power transmission control device 20, the power reception device 40, and the power reception control device 50 according to the present embodiment. A power transmission-side electronic device such as the charger 500 of FIG. 1A includes the power transmission device 10 of FIG. In addition, a power receiving-side electronic device such as the mobile phone 510 can include the power receiving device 40 and a load 90 (main load). 2, for example, the primary coil L1 and the secondary coil L2, which are planar coils, are electromagnetically coupled to transmit power from the power transmitting apparatus 10 to the power receiving apparatus 40, and the voltage output node of the power receiving apparatus 40 A non-contact power transmission (non-contact power transmission) system that supplies power (voltage VOUT) from the NB 7 to the load 90 is realized.

  The power transmission device 10 (power transmission module, primary module) can include a primary coil L1, a power transmission unit 12, a waveform monitor circuit 14, a display unit 16, and a power transmission control device 20. The power transmission device 10 and the power transmission control device 20 are not limited to the configuration in FIG. 2, and some of the components (for example, the display unit and the waveform monitor circuit) are omitted, other components are added, Various modifications such as changing the above are possible.

  The power transmission unit 12 generates an AC voltage having a predetermined frequency during power transmission, and generates an AC voltage having a different frequency according to data during data transfer, and supplies the AC voltage to the primary coil L1. Specifically, as shown in FIG. 3A, for example, when data “1” is transmitted to the power receiving device 40, an AC voltage of frequency f1 is generated and data “0” is transmitted. Generates an alternating voltage of frequency f2. The power transmission unit 12 includes at least a first power transmission driver that drives one end of the primary coil L1, a second power transmission driver that drives the other end of the primary coil L1, and a resonance circuit together with the primary coil L1. One capacitor can be included.

  Each of the first and second power transmission drivers included in the power transmission unit 12 is an inverter circuit (buffer circuit) configured by, for example, a power MOS transistor, and is controlled by the driver control circuit 26 of the power transmission control device 20.

  The primary coil L1 (power transmission side coil) is electromagnetically coupled to the secondary coil L2 (power reception side coil) to form a power transmission transformer. For example, when power transmission is necessary, as shown in FIGS. 1A and 1B, a mobile phone 510 is placed on the charger 500 so that the magnetic flux of the primary coil L1 passes through the secondary coil L2. To make sure On the other hand, when power transmission is unnecessary, the charger 500 and the mobile phone 510 are physically separated so that the magnetic flux of the primary coil L1 does not pass through the secondary coil L2.

  The waveform monitor circuit 14 (rectifier circuit, waveform shaping circuit) generates an induced voltage signal PHIN for waveform monitoring based on the coil end signal CSG of the primary coil L1. For example, the coil end signal CSG which is an induced voltage signal of the primary coil L1 exceeds the maximum rated voltage of the IC of the power transmission control device 20, or becomes a negative voltage. The waveform monitor circuit 14 receives such a coil end signal CSG, generates an induced voltage signal PHIN for waveform monitoring, which is a signal that can be detected by the waveform detection circuit 30 of the power transmission control device 20, and generates the power transmission control device. For example, output to 20 waveform monitor terminals. Details of the waveform monitor circuit 14 will be described later.

  The display unit 16 displays various states of the contactless power transmission system (during power transmission, ID authentication, etc.) using colors, images, and the like, and is realized by, for example, an LED or an LCD.

  The power transmission control device 20 is a device that performs various controls of the power transmission device 10, and can be realized by an integrated circuit device (IC) or the like. The power transmission control device 20 can include a control circuit 22 (power transmission side), an oscillation circuit 24, a drive clock generation circuit 25, a driver control circuit 26, and a waveform detection circuit 30. In addition, some implementations, such as abbreviate | omitting some of these components and adding another component, are possible.

  The control circuit 22 (control unit) on the power transmission side controls the power transmission device 10 and the power transmission control device 20, and can be realized by, for example, a gate array or a microcomputer. Specifically, the control circuit 22 performs various sequence control and determination processes necessary for power transmission, load state detection (data detection, foreign object detection, removal detection, etc.), frequency modulation, and the like.

  The oscillation circuit 24 is constituted by a crystal oscillation circuit, for example, and generates a primary side clock. The drive clock generation circuit 25 generates a drive clock that defines the drive frequency. The driver control circuit 26 generates a control signal having a desired frequency based on the drive clock, the frequency setting signal from the control circuit 22, and the like, and outputs the control signal to the first and second power transmission drivers of the power transmission unit 12. Then, the first and second power transmission drivers are controlled.

  The waveform detection circuit 30 detects a change in the waveform of the induced voltage signal PHIN of the primary coil L1. For example, when the load state (load current) on the power receiving side (secondary side) changes, the waveform of the induced voltage signal PHIN changes. The waveform detection circuit 30 detects such a change in waveform and outputs a detection result (detection result information) to the control circuit 22.

  Specifically, the waveform detection circuit 30 shapes the induced voltage signal PHIN, for example, and generates a waveform shaped signal. For example, when the signal PHIN exceeds a given threshold voltage, a square wave (rectangular wave) waveform shaping signal (pulse signal) that becomes active (eg, H level) is generated. The waveform detection circuit 30 detects pulse width information (pulse width period) of the waveform shaping signal based on the waveform shaping signal and the drive clock. Specifically, the pulse width information of the induced voltage signal PHIN is detected by receiving the waveform shaping signal and the drive clock from the drive clock generation circuit 25 and detecting the pulse width information of the waveform shaping signal.

  Based on the detection result of the waveform detection circuit 30, the control circuit 22 detects the load state (load fluctuation, load level) on the power receiving side (power receiving device 40 side). Specifically, based on the pulse width information detected by the waveform detection circuit 30 (pulse width detection circuit), the load state on the power receiving side is detected, for example, data (load) detection, foreign object (metal) detection, removal ( Detachment) is performed. That is, the pulse width period, which is the pulse width information of the induced voltage signal, changes according to the change in the load state on the power receiving side. The control circuit 22 detects a load fluctuation on the power receiving side based on the pulse width period (a count value obtained by measuring the pulse width period). Thereby, when the load modulation unit 46 of the power receiving device 40 transmits data by load modulation as shown in FIG. 3B, this transmission data can be detected.

  The power reception device 40 (power reception module, secondary module) can include a secondary coil L2, a power reception unit 42, a load modulation unit 46, a power supply control unit 48, and a power reception control device 50. The power reception device 40 and the power reception control device 50 are not limited to the configuration shown in FIG. 2, and various modifications such as omitting some of the components, adding other components, and changing the connection relationship. Implementation is possible.

  The power receiving unit 42 converts the AC induced voltage of the secondary coil L2 into a DC voltage. This conversion is performed by a rectifier circuit 43 included in the power receiving unit 42. The rectifier circuit 43 includes diodes DB1 to DB4. The diode DB1 is provided between the node NB1 at one end of the secondary coil L2 and the generation node NB3 of the DC voltage VDC, and DB2 is provided between the node NB3 and the node NB2 at the other end of the secondary coil L2. , DB3 is provided between the node NB2 and the VSS node NB4, and DB4 is provided between the nodes NB4 and NB1.

  The resistors RB1 and RB2 of the power receiving unit 42 are provided between the nodes NB1 and NB4. The signal CCMPI obtained by dividing the voltage between the nodes NB1 and NB4 by the resistors RB1 and RB2 is input to the frequency detection circuit 60 of the power reception control device 50.

  The capacitor CB1 and the resistors RB4 and RB5 of the power receiving unit 42 are provided between the node NB3 of the DC voltage VDC and the node NB4 of VSS. A signal ADIN obtained by dividing the voltage between the nodes NB3 and NB4 by the resistors RB4 and RB5 is input to the position detection circuit 56 of the power reception control device 50.

  The load modulation unit 46 performs load modulation processing. Specifically, when desired data is transmitted from the power receiving device 40 to the power transmitting device 10, the load at the load modulation unit 46 (secondary side) is variably changed in accordance with the transmission data, and FIG. As shown, the signal waveform of the induced voltage of the primary coil L1 is changed. For this purpose, the load modulation unit 46 includes a resistor RB3 and a transistor TB3 (N-type CMOS transistor) provided in series between the nodes NB3 and NB4. The transistor TB3 is on / off controlled by a signal P3Q from the control circuit 52 of the power reception control device 50. When performing load modulation by controlling on / off of the transistor TB3, the transistor TB2 of the power supply control unit 48 is turned off, and the load 90 is not electrically connected to the power receiving device 40.

  For example, as shown in FIG. 3B, when the secondary side is set to a low load (high impedance) in order to transmit data “0”, the signal P3Q becomes L level and the transistor TB3 is turned off. . As a result, the load of the load modulation unit 46 becomes almost infinite (no load). On the other hand, in order to transmit data “1”, when the secondary side is set to a high load (impedance is low), the signal P3Q becomes H level and the transistor TB3 is turned on. As a result, the load of the load modulation unit 46 becomes the resistance RB3 (high load).

  The power supply control unit 48 controls power supply to the load 90. The regulator 49 adjusts the voltage level of the DC voltage VDC obtained by the conversion in the rectifier circuit 43 to generate the power supply voltage VD5 (for example, 5V). For example, the power reception control device 50 is supplied with the power supply voltage VD5 and operates.

  The transistor TB2 (P-type CMOS transistor) is controlled by a signal P1Q from the control circuit 52 of the power reception control device 50. Specifically, the transistor TB2 is turned on when ID authentication is completed (established) and normal power transmission is performed, and turned off when load modulation is performed.

  The power reception control device 50 is a device that performs various controls of the power reception device 40 and can be realized by an integrated circuit device (IC) or the like. The power reception control device 50 can be operated by a power supply voltage VD5 generated from the induced voltage of the secondary coil L2. The power reception control device 50 can include a control circuit 52 (power reception side), a position detection circuit 56, an oscillation circuit 58, a frequency detection circuit 60, and a full charge detection circuit 62.

  The control circuit 52 (control unit) controls the power reception device 40 and the power reception control device 50, and can be realized by, for example, a gate array or a microcomputer. Specifically, the control circuit 52 performs various sequence control and determination processes necessary for ID authentication, position detection, frequency detection, load modulation, full charge detection, and the like.

  The position detection circuit 56 monitors the waveform of the signal ADIN corresponding to the waveform of the induced voltage of the secondary coil L2, and determines whether the positional relationship between the primary coil L1 and the secondary coil L2 is appropriate. Specifically, the signal ADIN is converted into a binary value by a comparator or the level is determined by A / D conversion to determine whether or not the positional relationship is appropriate.

  The oscillation circuit 58 is constituted by a CR oscillation circuit, for example, and generates a secondary clock. The frequency detection circuit 60 detects the frequency (f1, f2) of the signal CCMPI and determines whether the transmission data from the power transmission device 10 is “1” or “0” as shown in FIG. To do.

  The full charge detection circuit 62 (charge detection circuit) is a circuit that detects whether or not the battery 94 (secondary battery) of the load 90 is in a fully charged state (charged state).

  The load 90 can include a charge control device 92 that performs charge control of the battery 94 and the like. The charge control device 92 (charge control IC) can be realized by an integrated circuit device or the like. Note that, like a smart battery, the battery 94 itself may have the function of the charging control device 92.

  Next, an outline of the operation on the power transmission side and the power reception side will be described using the flowchart of FIG. When the power transmission side is powered on and powered on (step S1), the power transmission side performs temporary power transmission for position detection (step S2). By this power transmission, the power supply voltage on the power receiving side rises and the reset of the power reception control device 50 is released (step S11). Then, the power receiving side sets the signal P1Q to H level (step S12). As a result, the transistor TB2 is turned off, and the electrical connection with the load 90 is interrupted.

  Next, the power receiving side uses the position detection circuit 56 to determine whether or not the positional relationship between the primary coil L1 and the secondary coil L2 is appropriate (step S13). If the positional relationship is appropriate, the power receiving side starts an ID authentication process and transmits an authentication frame to the power transmission side (step S14). Specifically, the authentication frame data is transmitted by the load modulation described with reference to FIG.

  When the power transmission side receives the authentication frame, the power transmission side performs determination processing such as whether or not the IDs match (step S3). When the ID authentication is permitted, a permission frame is transmitted to the power receiving side (step S4). Specifically, data is transmitted by the frequency modulation described with reference to FIG.

  The power receiving side receives the permission frame and, if the content is OK, transmits a start frame for starting contactless power transmission to the power transmitting side (steps S15 and S16). On the other hand, the power transmission side receives the start frame and starts normal power transmission when the content is OK (steps S5 and S6). Then, the power receiving side sets the signal P1Q to the L level (step S17). As a result, both transistors TB2 are turned on, so that power transmission to the load 90 becomes possible, and power supply to the load (output of VOUT) starts (step S18).

3. Waveform monitor circuit 3.1. First Configuration Example FIG. 5 shows a first configuration example of the waveform monitor circuit 14 of the present embodiment. In FIG. 5, the power transmission control device 20 controls the power transmission drivers (first and second power transmission drivers) of the power transmission unit 12 that drives the primary coil L1. Further, the power transmission control device 20 receives the induced voltage signal PHIN1 for waveform monitoring from the waveform monitor circuit 14 via the waveform monitor terminal. Then, the waveform detection circuit 30 included in the power transmission control device 20 detects a change in the waveform of the induced voltage signal PHIN1, thereby detecting the load state on the power receiving side (secondary side).

  The waveform monitor circuit 14 generates an induced voltage signal PHIN1 for waveform monitoring based on the coil end signal CSG of the primary coil L1, and outputs it to the power transmission control device 20. Specifically, the waveform monitor circuit 14 includes a first rectifier circuit 17 with a limiter function. This rectifier circuit 17 has a current provided between a coil end node NA2 where a coil end signal CSG of the primary coil L1 is generated and a first monitor node NA11 where an induced voltage signal PHIN1 for waveform monitoring is generated. A first resistor RA1 serving as a limiting resistor is included. The rectifier circuit 17 performs a limiter operation for clamping the induced voltage signal PHIN1 to the voltage of VDD (high potential power supply voltage), and performs half-wave rectification on the induced voltage signal PHIN1.

  By providing such a current limiting resistor RA1, it is possible to prevent an excessive current from the coil end node NA2 from flowing into the IC terminal of the power transmission control device 20. Further, the rectifier circuit 17 clamps the induced voltage signal PHIN1 to the voltage of VDD, so that a situation where a voltage equal to or higher than the maximum rated voltage is applied to the IC terminal of the power transmission control device 20 is prevented. Moreover, the situation where the negative voltage is applied to the IC terminal of the power transmission control device 20 is prevented by the rectifier circuit 17 performing half-wave rectification.

  Specifically, the rectifier circuit 17 is provided between the monitor node NA11 and the VDD (high potential power supply in a broad sense) node, and is a first diode whose forward direction is from the monitor node NA11 to the VDD node. Includes DA1. Further, it includes a second diode DA2 provided between the monitor node NA11 and the GND (low potential power supply in a broad sense) node and having a forward direction from the GND node to the monitor node NA11. A limit operation to VDD is realized by the diode DA1, and half-wave rectification is realized by the diode DA2.

3.2. Second Configuration Example FIG. 6 shows a second configuration example of the waveform monitor circuit 14. In the second configuration example, a Zener diode DZ1 is provided in the rectifier circuit 17 instead of providing the diode DA1 in FIG. That is, a Zener diode is provided between the monitor node NA11 and the GND (low potential power supply) node, and the forward direction is from the GND node to the monitor node NA11.

3.3. Third Configuration Example FIG. 7 shows a third configuration example of the waveform monitor circuit 14. In the third configuration example, similarly to the first configuration example, the waveform monitor circuit 14 includes a first rectifier circuit 17 with a limiter function, and the induced voltage signal PHIN1 is set to a voltage of VDD (high potential power supply voltage). A clamper limiter operation is performed and half-wave rectification is performed on the induced voltage signal PHIN1. That is, the rectifier circuit 17 clamps the induced voltage signal PHIN1 to the voltage of VDD, so that a situation where a voltage higher than the maximum rated voltage is applied to the IC terminal of the power transmission control device 20 is prevented. Further, since the rectifier circuit 17 performs half-wave rectification, a situation where a negative voltage is applied to the IC terminal of the power transmission control device 20 is prevented.

  Specifically, the rectifier circuit 17 includes a first diode DA1 and a second diode DA2. The first diode DA1 is provided between the monitor node NA11 and the VDD node (high potential power supply node in a broad sense), and the direction from the monitor node NA11 to the VDD node is the forward direction. On the other hand, the second diode DA2 is provided between the monitor node NA11 and the GND node (low potential power supply node in a broad sense), and the direction from the GND node to the monitor node NA11 is the forward direction. A limit operation to VDD is realized by the first diode DA1, and half-wave rectification is realized by the second diode DA2.

  Further, the rectifier circuit 17 is arranged between the coil end node NA2 and the first monitor node NA11 in order to prevent an excessive current from the coil end node NA2 from flowing into the IC terminal of the power transmission control device 20. A first resistor RA1 which is a current limiting resistor is provided. In the third configuration example, unlike the first configuration example, the first resistor RA1 is arranged between the first diode DA1 and the second diode DA2.

  The third configuration example is characterized in that the first capacitor CA1 is provided on the input stage side of the rectifier circuit 17. Specifically, the first capacitor CA1 is provided between the coil end node NA2 and the low potential side resistance end node NA12 between the first resistor RA1 and the second diode DA2.

  The coil end signal CSG may not have a center voltage of 0 V but may have a DC offset. When this DC offset varies, the pulse width of the pulse signal obtained by shaping the induced voltage signal PHIN1 varies, and the load state detection accuracy decreases. Therefore, in order to cancel such a DC offset, in the third configuration example, the first capacitor CA1 is provided on the input stage side of the rectifier circuit 17. By extracting only the AC component of the coil end signal by the capacitive coupling of the first capacitor CA1, even when the DC offset of the coil end signal fluctuates, the adverse effect affects the load state detection accuracy. Can be prevented. It is also possible to shift the voltage level of the coil end signal to a voltage level with high detection sensitivity that is easy to detect with a desired threshold voltage. Therefore, detection accuracy such as a pulse width of a pulse signal obtained by shaping the induced voltage signal PHIN1 output from the rectifier circuit 17 is improved, and detection of a load state or the like can be realized with high sensitivity and high dynamic range.

3.4. Fourth Configuration Example FIG. 8 shows a fourth configuration example of the waveform monitor circuit 14. In FIG. 8, the waveform monitor circuit 14 includes a second rectifier circuit 18 in addition to the first rectifier circuit 17. The waveform detection circuit 30 includes first and second waveform detection circuits 31 and 34. The first waveform detection circuit 31 detects a waveform change of the first induced voltage signal PHIN1 of the primary coil L1. The second waveform detection circuit 34 detects a waveform change of the second induced voltage signal PHIN2 of the primary coil L1.

  The second rectifier circuit 18 outputs the second induced voltage signal PHIN2 for waveform monitoring to the second waveform detection circuit 34 via the second monitor node NA21. Specifically, the rectifier circuit 18 includes a second resistor RA2 that is a current limiting resistor provided between the coil end node NA2 and the monitor node NA21, and a node between the monitor node NA21 and the GND (low potential power supply) node. Includes a third resistor RA3. Further, it includes a third diode DA3 provided between the monitor node NA21 and the GND node. Then, the voltage of the coil end signal CSG is divided by the resistors RA2 and RA3, and is input to the second waveform detection circuit 34 as the induced voltage signal PHIN2. Further, the diode DA3 performs half-wave rectification of the coil end signal CSG so that a negative voltage is not applied to the second waveform detection circuit 34.

  FIG. 9 shows a waveform example of a coil end signal CSG input to the rectifier circuit 17, an induced voltage signal PHIN1 output from the rectifier circuit 17 to the first waveform detection circuit 31, and a pulse signal PLS1 used for pulse width detection. Indicates.

  As indicated by E1 in FIG. 9, the first waveform detection circuit 31 detects a pulse width period XTPW1 corresponding to a phase change at the rising portion of the induced voltage signal PHIN1 (coil end signal CSG). That is, when the induced voltage signal PHIN1 changes from 0V and exceeds the threshold voltage VT1 as indicated by E2, the edge timing of the drive clock DRCK (the rising edge timing in FIG. 9 is the falling edge timing) The pulse width period XTPW1 that is a period between the two is also measured. Therefore, in this case, since it is only necessary to detect the vicinity of 0V, waveform reduction is unnecessary, and voltage division by the resistors RA2 and RA3 as in the rectifier circuit 18 of FIG. 8 is not necessary. For this reason, the waveform of the signal PHIN1 is not crushed, and there is no signal deterioration due to the resistance dividing node and the parasitic capacitance. Therefore, since the first waveform detection circuit 31 can perform waveform detection using the signal PHIN1 having a clean waveform, the detection accuracy can be improved.

  Here, the signal PHIN1 may exceed the maximum rated voltage of the power transmission control device 20 unless the waveform is reduced by voltage division using a resistor in this way. In this respect, the rectifier circuit 17 is provided with a diode DA1, and the diode DA1 performs a limit operation for clamping the signal PHIN1 to the voltage of VDD as indicated by E3, so that the signal PHIN1 exceeds the maximum rated voltage. Can be prevented. Further, the rectifier circuit 17 is provided with a diode DA2, and the diode DA2 performs half-wave rectification as indicated by E4, so that a negative voltage is applied to the IC terminal of the power transmission control device 20. Can be prevented.

  FIG. 10 shows a waveform example of a coil end signal CSG input to the rectifier circuit 18, an induced voltage signal PHIN2 output from the rectifier circuit 18 to the second waveform detection circuit 34, and a pulse signal PLS2 used for pulse width detection. Indicates.

  As indicated by G1 in FIG. 10, the second waveform detection circuit 34 detects a pulse width period XTPW2 corresponding to a phase change at the falling portion of the induced voltage signal PHIN2 (coil end signal CSG). That is, the induced voltage signal PHIN2 changes from the voltage on the VDD side, and as indicated by G2, the timing falls below the threshold voltage VT2 and the edge timing of the drive clock DRCK (in FIG. 10, it is the falling edge timing, A pulse width period XTPW2 that is a period between the rising edge timing and the rising edge timing may be measured. Therefore, it is necessary to reduce the waveform of the coil end signal CSG that becomes a voltage exceeding VDD, and for this purpose, the rectifier circuit 18 performs voltage division using the resistors RA2 and RA3. Specifically, by dividing the coil end signal CSG and reducing the waveform, for example, the threshold voltage of an N-type transistor can be used as the threshold voltage VT2. The rectifier circuit 18 is provided with a diode DA3, and this diode DA3 performs half-wave rectification as indicated by G3, so that a negative voltage is applied to the IC terminal of the power transmission control device 20. Can be prevented.

  For example, if the induced voltage signal PHIN1 input to the first waveform detection circuit 31 of FIG. 8 is generated by the rectifier circuit 18 instead of the rectifier circuit 17, the waveform is reduced by voltage division. For this reason, the waveform near the threshold voltage VT1 may be crushed, and the detection accuracy may be deteriorated.

  In this regard, in FIG. 8, such a situation can be prevented because the induced voltage signal PHIN1 is generated by the rectifier circuit 17 that does not perform voltage division.

  Further, as shown by E3 in FIG. 9, when the limit operation by the diode DA1 of the rectifier circuit 17 is performed, the current limiting resistor RA1 is not provided between the monitor node NA11 and the coil end node NA2 in FIG. 8B. The limit operation to the VDD voltage in the rectifier circuit 17 adversely affects the rectifier circuit 18. In other words, if the current limiting resistor RA1 is not present, the voltage at the coil end node NA2 is clamped to the voltage VDD by the limit operation by the rectifier circuit 17, which adversely affects the operation of the power transmission driver and the rectifier circuit 18.

  In this regard, in FIG. 8, since the current limiting resistor RA1 is provided between the coil end node NA2 and the monitor node NA11, when the limit operation to the voltage VDD shown in E3 of FIG. It is possible to prevent the limit operation from adversely affecting the rectifier circuit 18.

  As described above, in FIG. 8, circuits having different configurations such as the rectifier circuits 17 and 18 are used as circuits for generating the induced voltage signals PHIN1 and PHIN2 for the first and second waveform detection circuits 31 and 34. . By properly using the rectifier circuits 17 and 18 as described above, the dynamic range and sensitivity are complemented, and accurate waveform detection (pulse width detection) can be realized.

3.5. Fifth Configuration Example FIG. 11 shows a fifth configuration example of the waveform monitor circuit 14. In FIG. 11, the waveform monitor circuit 14 includes a second rectifier circuit 181 and a third rectifier circuit 191 in addition to the first rectifier circuit 17. The waveform detection circuit 30 includes first, second, and third waveform detection circuits 31, 34, and 37. The first waveform detection circuit 31 detects a waveform change of the first induced voltage signal PHIN1 of the primary coil L1. The second waveform detection circuit 34 detects a waveform change of the second induced voltage signal PHIN2 of the primary coil L1. The third waveform detection circuit 37 detects a waveform change of the third induced voltage signal PHIN3 of the primary coil L1.

  The first rectifier circuit 17 outputs the first induced voltage signal PHIN1 for waveform monitoring to the first waveform detection circuit 31 via the first monitor node NA11, and the configuration thereof is shown in FIG. This is the same as the rectifier circuit included in the third configuration example of the waveform monitor circuit 14. That is, the first rectifier circuit 17 includes a first diode DA1 provided between the monitor node NA11 and the VDD node, and a second diode DA2 provided between the monitor node NA11 and the GND node. Then, the limit operation to VDD is realized by the first diode DA1, and half-wave rectification is realized by the second diode DA2.

  Further, in order to prevent an excessive current from the coil end node NA2 from flowing into the IC terminal of the power transmission control device 20, a first current limiting resistor is provided between the coil end node NA2 and the first monitor node NA11. 1 resistor RA1 is provided, specifically, disposed between the first diode DA1 and the second diode DA2. Furthermore, on the input stage side of the first rectifier circuit 17, specifically, a coil end node NA2 and a low potential side resistance end node NA12 between the first resistor RA1 and the second diode DA2 A first capacitor CA1 is provided therebetween.

  The second rectifier circuit 181 outputs a second induced voltage signal PHIN2 for waveform monitoring to the second waveform detection circuit 34 via the second monitor node NA21. The second rectifier circuit 181 includes a third diode DA3B provided between the second monitor node NA21 and the GND node, and a fourth diode DA4B provided between the second monitor node NA21 and the VDD node. And including. In the second rectifier circuit 181, a limit operation to VDD is realized by the fourth diode DA4B, and half-wave rectification is realized by the third diode DA3B.

  Further, in order to prevent an excessive current from the coil end node NA2 from flowing into the IC terminal of the power transmission control device 20, a first current limiting resistor is provided between the coil end node NA2 and the second monitor node NA21. A second resistor RA2B is provided, and a third resistor RA3B is provided between the second monitor node NA21 and the GND node. Further, on the input stage side of the second rectifier circuit 181, specifically, between the coil end node NA2 and the high potential side resistance end node NA22 between the second resistor RA2B and the fourth diode DA4B. In addition, a second capacitor CA2 is provided.

  The third rectifier circuit 191 outputs a third induced voltage signal PHIN3 for waveform monitoring to the third waveform detection circuit 37 via the third monitor node NA31. Specifically, the rectifier circuit 191 includes a fourth resistor RA2C provided between the coil end node NA2 and the third monitor node NA31, and a fifth resistor provided between the monitor node NA31 and the GND node. Resistor RA3C. Further, it includes a fifth diode DA3C provided between the monitor node NA31 and the GND node. The voltage of the coil end signal CSG is divided by the resistors RA2C and RA3C, and is input to the third waveform detection circuit 37 as the induced voltage signal PHIN3. Further, the diode DA3C performs half-wave rectification of the coil end signal CSG so that a negative voltage is not applied to the third waveform detection circuit 37.

  FIG. 12 shows the coil end signal CSG input to the first and second rectifier circuits 17 and 181, the induced voltage signal PHIN 1 output from the first rectifier circuit 17 to the first waveform detection circuit 31, and the pulse width. Examples of waveforms of the pulse signal PLS1 used for detection, the induced voltage signal PHIN2 output from the second rectifier circuit 181 to the second waveform detection circuit 34, and the pulse signal PLS2 used for pulse width detection are shown.

  As shown in J1 of FIG. 12, the first waveform detection circuit 31 detects a pulse width period XTPW1 corresponding to the phase change at the rising portion of the induced voltage signal PHIN1 (coil end signal CSG). That is, as shown in J2 when the induced voltage signal PHIN1 changes from 0V, the timing exceeds the threshold voltage VT1 and the edge timing of the drive clock DRCK (the rising edge timing in FIG. 12 is the falling edge timing) The pulse width period XTPW1 that is a period between the timing and the timing may be measured. Therefore, in this case, since it is only necessary to detect the vicinity of 0 V, waveform reduction is unnecessary, and voltage division by the resistors RA2B and RA3B as in the rectifier circuit 181 in FIG. 11 is not necessary. For this reason, the waveform of the signal PHIN1 is not crushed, and there is no signal deterioration due to the resistance dividing node and the parasitic capacitance. Therefore, since the first waveform detection circuit 31 can perform waveform detection using the signal PHIN1 having a clean waveform, the detection accuracy can be improved.

  Here, the signal PHIN1 may exceed the maximum rated voltage of the power transmission control device 20 unless the waveform is reduced by voltage division using a resistor in this way. In this regard, the rectifier circuit 17 is provided with a diode DA1, and this diode DA1 performs a limit operation for clamping the signal PHIN1 to the voltage of VDD as indicated by J3, so that the signal PHIN1 exceeds the maximum rated voltage. Can be prevented. Further, the rectifier circuit 17 is provided with a diode DA2, and the diode DA2 performs half-wave rectification as indicated by J4, so that a negative voltage is applied to the IC terminal of the power transmission control device 20. Can also be prevented.

  On the other hand, the second waveform detection circuit 34 detects a pulse width period XTPW2 corresponding to a phase change at the falling portion of the induced voltage signal PHIN2 (coil end signal CSG), as indicated by K1. That is, as shown in K2 when the induced voltage signal PHIN2 changes from the voltage on the VDD side, the timing falls below the threshold voltage VT2 and the edge timing of the drive clock DRCK (the falling edge timing in FIG. 12 is A pulse width period XTPW2 that is a period between the rising edge timing and the rising edge timing may be measured. Therefore, it is necessary to reduce the waveform of the coil end signal CSG that becomes a voltage exceeding VDD, and for this purpose, the rectifier circuit 181 performs voltage division using the resistors RA2B and RA3B. Specifically, by dividing the coil end signal CSG and reducing the waveform, for example, the threshold voltage of an N-type transistor can be used as the threshold voltage VT2. Note that the rectifier circuit 181 is provided with a diode DA3B, and the diode DA3B performs half-wave rectification as indicated by K3, so that a negative voltage is applied to the IC terminal of the power transmission control device 20. Can also be prevented.

  For example, if the induced voltage signal PHIN1 input to the first waveform detection circuit 31 in FIG. 11 is generated by the rectifier circuit 181 instead of the rectifier circuit 17, the waveform is reduced by voltage division. For this reason, the waveform near the threshold voltage VT1 may be crushed, and the detection accuracy may be deteriorated.

  In this regard, in FIG. 11, since the induced voltage signal PHIN1 is generated by the rectifier circuit 17 that does not perform voltage division, such a situation can be prevented.

  As described above, in FIG. 11, circuits having different configurations such as the rectifier circuits 17 and 181 are used as the circuits for generating the induced voltage signals PHIN1 and PHIN2 for the first and second waveform detection circuits 31 and 34. Yes. By properly using the rectifier circuits 17 and 181 in this way, the dynamic range and sensitivity are complemented, and accurate waveform detection (pulse width detection) can be realized.

  Further, in the fifth configuration example, by providing the first and second capacitors CA1 and CA2 on the input stage side of the first and second rectifier circuits 17 and 181, by capacitive coupling of the capacitors CA1 and CA2, The DC offset of the coil end signal CSG can be canceled. Therefore, it is possible to prevent the fluctuation of the DC offset from adversely affecting the load state detection accuracy. This makes it possible to detect a load state with high sensitivity and high dynamic range.

4). First Configuration Example of Power Transmission Device FIG. 13 shows a first configuration example of the power transmission device 10. FIG. 13 corresponds to a first configuration example of the waveform monitor circuit 14 of FIG.

  In FIG. 13, when the inductance of the primary coil L1 or the capacitance value of the capacitor constituting the resonance circuit varies, the power supply voltage varies, or the distance and positional relationship between the primary coil L1 and the secondary coil L2 vary, the induced voltage The peak voltage (amplitude) of the signal PHIN1 also varies. Therefore, there is a possibility that accurate detection of the load fluctuation cannot be realized only by the method of detecting the peak voltage of the signal PHIN1. Therefore, in FIG. 13, the load fluctuation is detected by detecting the pulse width information of the induced voltage signal PHIN1.

  In FIG. 13, the drive clock generation circuit 25 generates a drive clock DRCK that defines the drive frequency of the primary coil L1. Specifically, the reference clock CLK generated by the oscillation circuit 24 is divided to generate the drive clock DRCK. The primary coil L1 is supplied with an AC voltage having a driving frequency of the driving clock DRCK.

  The driver control circuit 26 generates a driver control signal based on the drive clock DRCK and outputs the driver control signal to the power transmission drivers (first and second power transmission drivers) of the power transmission unit 12 that drives the primary coil L1. In this case, the signal input to the gate of the P-type transistor of the inverter circuit and the signal input to the gate of the N-type transistor are non-overlapping so that no through current flows through the inverter circuit constituting the power transmission driver. A driver control signal is generated so as to become a signal.

  The waveform detection circuit 30 includes a first waveform detection circuit 31 that detects a change in the waveform of the first induced voltage signal PHIN1 of the primary coil L1. The first waveform detection circuit 31 includes a first waveform shaping circuit 32 and a first pulse width detection circuit 33. The waveform shaping circuit 32 (pulse signal generation circuit) shapes the induced voltage signal PHIN1 of the primary coil L1 and outputs a waveform shaping signal WFQ1. Specifically, for example, a square wave (rectangular wave) waveform shaping signal WFQ1 (pulse signal) that becomes active (eg, H level) when the signal PHIN1 exceeds a given threshold voltage is output.

  The pulse width detection circuit 33 detects the pulse width information of the induced voltage signal PHIN1 of the primary coil L1. Specifically, the waveform shaping signal WFQ1 from the waveform shaping circuit 32 and the drive clock DRCK (driver control signal) from the drive clock generation circuit 25 are received, and the pulse width information of the waveform shaping signal WFQ1 is detected to induce the waveform shaping signal WFQ1. The pulse width information of the voltage signal PHIN1 is detected.

  For example, it is assumed that the timing when the induced voltage signal PHIN1 changes from the GND side (low potential power supply side) and exceeds the first threshold voltage VT1 is the first timing. In this case, the pulse width detection circuit 33 measures a first pulse width period, which is a period between the first edge timing (for example, the falling timing) of the drive clock DRCK and the first timing, The pulse width information is detected. For example, the first pulse width period in which the voltage signal PHIN1 induced by the voltage change of the drive clock DRCK is equal to or lower than a given threshold voltage VT1 is measured. Then, the magnitude of the pulse width of the waveform shaping signal WFQ1 (induced voltage signal) with respect to the pulse width of the drive clock DRCK is measured. In this case, the first pulse width period is measured using, for example, the reference clock CLK. Data PWQ1 as a result of measurement by the pulse width detection circuit 33 is latched by, for example, a latch circuit (not shown). Specifically, the pulse width detection circuit 33 measures the first pulse width period using a counter that increments (or decrements) the count value using the reference clock CLK, and the measurement result data PWQ1 is stored in the latch circuit. Latched.

  Based on the pulse width information detected by the pulse width detection circuit 33, the control circuit 22 detects the load state (load fluctuation, load level) on the power receiving side (secondary side). Specifically, the control circuit 22 performs foreign object detection (primary foreign object detection) based on the pulse width information detected by the pulse width detection circuit 33. Alternatively, the data transmitted by the power receiving device 40 by load modulation may be detected.

  14A to 14C show measurement results of signal waveforms of the drive clock DRCK, the coil end signal CSG, the induced voltage signal PHIN1, and the pulse signal PLS1. 14 (A), 14 (B), and 14 (C) respectively show a low load (for example, secondary side load current = 0 mA), a medium load (load current = 70 mA), and a high load (load current = 150 mA) is a signal waveform (voltage waveform). The pulse signal PLS1 used for pulse width detection becomes H level at the first timing TM1 when the induced voltage signal PHIN1 exceeds the first threshold voltage VT1, and L level at the rising edge timing TR of the drive clock DRCK. Is a signal. Note that as the threshold voltage VT1 for measuring the pulse width period (for example, the threshold voltage of the N-type transistor), a voltage that optimizes the load state detection accuracy may be appropriately selected and set.

  As shown in FIGS. 14A to 14C, the pulse width period XTPW1 of the pulse signal PLS1 becomes longer as the load on the power receiving side becomes higher (as the load current becomes larger). Therefore, by measuring the pulse width period XTPW1, it is possible to detect the load state (load level) on the power receiving side. For example, if a foreign object such as metal is inserted on the primary coil L1 (between L1 and L2), the primary power is supplied to the foreign object, and the load state on the power receiving side is an overload state. become. Even in such a case, this overload state can be detected by measuring the length of the pulse width period XTPW1, and so-called foreign matter detection (primary foreign matter detection) can be realized. In addition, by measuring the pulse width period XTPW1, it is possible to determine whether the load of the load modulation unit 46 of the power receiving device 40 is high or low and to detect whether the transmission data from the power receiving side is “0” or “1”. become.

  In FIGS. 14A to 14C, a period from the timing TM1 to the rising edge timing TR of the drive clock DRCK is defined as a pulse width period XTPW1. That is, in this case, the first waveform detection circuit 31 detects the pulse width period XTPW1 of the pulse signal PLS1 as the first pulse width information. However, as shown in FIG. 17 described later, the period from the falling edge timing TF to the timing TM1 of the drive clock DRCK is defined as a pulse width period TPW1, and the first waveform detection circuit 31 sets the pulse width period TPW1 to the first. It is desirable to detect it as pulse width information. In this way, it is possible to prevent a situation in which the noise signal is regarded as a pulse signal and the pulse width period is measured when the load on the power receiving side is low. In this case, the pulse width period TPW1 becomes shorter as the load on the power receiving side becomes higher. Therefore, when the pulse width period TPW1 (pulse width count number) becomes shorter than a given period (given count number), it can be determined that foreign matter has been inserted on the primary coil L1, and foreign matter detection is realized. it can.

  FIG. 15A shows an equivalent circuit on the primary side when there is no load, and FIG. 15B shows an equivalent circuit when there is a load. As shown in FIG. 15A, when there is no load, a series resonance circuit is formed by the capacitance C, the primary side leakage inductance Ll1 and the coupling inductance M. Accordingly, as indicated by B1 in FIG. 15C, the coil resonance characteristic at no load becomes a sharp characteristic having a high Q value. On the other hand, in the case of a load, a secondary side leakage inductance Ll2 and a secondary side load resistance RL are added. Therefore, as shown in FIG. 15C, the resonance frequencies fr2 and fr3 in the case of load are larger than the resonance frequency fr1 in the case of no load. Further, due to the influence of the resistance RL, the resonance characteristic under load is a gentle characteristic with a low Q value. Further, as the load becomes low (large RL) and high load (RL small), the resonance frequency increases and the resonance frequency approaches the coil drive frequency (DRCK frequency).

  As the resonance frequency approaches the drive frequency in this way, the portion of the sine wave that is the resonance waveform gradually appears. That is, in the voltage waveform at the time of low load as shown in FIG. 14A, the square wave that is the driving waveform is more dominant than the sine wave that is the resonance waveform. On the other hand, in the voltage waveform at the time of high load as shown in FIG. 14C, the sine wave that is the resonance waveform is more dominant than the square wave that is the drive waveform. As a result, as the load becomes higher, the pulse width period XTPW1 becomes longer (TPW1 becomes shorter). Therefore, by measuring the pulse width period XTPW1 (TPW1), it is possible to determine the load fluctuation (high or low) on the power receiving side with a simple configuration.

  For example, a method is conceivable in which load variation on the power receiving side due to insertion of a metal foreign object or the like is detected by detecting only a change in peak voltage of a coil end signal. However, according to this method, the peak voltage changes depending not only on the load fluctuation but also on the distance and the positional relationship between the primary coil L1 and the secondary coil L2. Therefore, there is a problem that variation in load variation detection becomes large.

  On the other hand, in the pulse width detection method of the present embodiment, the load fluctuation is detected by measuring, by digital processing, the pulse width period that changes depending on the load state on the power receiving side instead of the peak voltage. Therefore, there is an advantage that load variation detection with little variation can be realized.

  In addition, a method for determining the load fluctuation on the power receiving side based on the phase characteristics due to the load is also conceivable. Here, the phase characteristic due to the load indicates a voltage / current phase difference. However, this method has a problem that the circuit configuration is complicated and the cost is increased.

  On the other hand, the pulse width detection method of the present embodiment has an advantage that the circuit configuration can be simplified because a voltage waveform can be used and processed as digital data by a simple waveform shaping circuit and a counting circuit (counter). Further, there is an advantage that it is easy to realize a combination with an amplitude detection method for detecting a load fluctuation by detecting a peak voltage.

  Furthermore, in the pulse width detection method of this embodiment, as shown in FIGS. 14A to 14C, the timing TM1 when the induced voltage signal PHIN1 changes from 0 V (GND side) and exceeds the threshold voltage VT1. The pulse width period XTPW1 defined by is measured. Therefore, by setting the threshold voltage VT1 close to 0V, adverse effects due to power supply voltage fluctuations and coil distance / position relation fluctuations can be reduced, and load fluctuation detection with less variation can be realized.

  FIG. 16 shows a specific example of the first configuration example of the power transmission device 10 of the present embodiment.

  The waveform shaping circuit 32 includes a resistor RC1 and an N-type transistor TC1 connected in series between VDD (high potential power supply) and GND (low potential power supply), and an inverter circuit INVC1. The induced voltage signal PHIN1 from the waveform monitor circuit 14 is input to the gate of the transistor TC1. When the signal PHIN1 becomes higher than the threshold voltage of the transistor TC1, the TC1 is turned on and the voltage of the node NC1 becomes L level, so that the waveform shaping signal WFQ1 becomes H level. On the other hand, when the signal PHIN1 becomes lower than the threshold voltage, the waveform shaping signal WFQ1 becomes L level.

  The pulse width detection circuit 33 includes a first counter 122. The counter 122 increments (or decrements) the count value in the pulse width period, and measures the length of the pulse width period (first pulse width period) based on the obtained count value. In this case, the counter 122 performs a count value counting process based on the reference clock CLK, for example.

  More specifically, the pulse width detection circuit 33 includes a first enable signal generation circuit 120. The enable signal generation circuit 120 receives the first waveform shaping signal WFQ1 and the drive clock DRCK, and generates the first enable signal ENQ1 that becomes active in the first pulse width period. The counter 122 increments (or decrements) the count value when the enable signal ENQ1 is active (eg, H level).

  In the enable signal generation circuit 120, a drive clock DRCK (including a signal equivalent to DRCK) is input to its clock terminal (inverted clock terminal), and a voltage of VDD (high potential power supply) is input to its data terminal. It can be configured by a flip-flop circuit FFC1 in which a waveform shaping signal WFQ1 (including a signal equivalent to WFQ1) is input to a reset terminal (non-inverting reset terminal). According to the flip-flop circuit FFC1, when the drive clock DRCK becomes L level after the waveform shaping signal WFQ1 becomes L level, the output signal enable signal ENQ1 becomes H level (active). Thereafter, when the waveform shaping signal WFQ1 becomes H level, the flip-flop circuit FFC1 is reset, and the enable signal ENQ1 that is an output signal thereof becomes L level (inactive). Therefore, the counter 122 can measure the pulse width period by counting the period in which the enable signal ENQ1 is at the H level (active) with the reference clock CLK.

  The enable signal generation circuit 120 is configured by a flip-flop circuit in which the drive clock DRCK is input to the clock terminal, GND (low potential power supply) is connected to the data terminal, and the waveform shaping signal WFQ1 is input to the set terminal. May be. In this case, an inverted signal of the output signal of the flip-flop circuit may be input to the counter 122 as the enable signal ENQ1.

  The count value holding circuit 124 holds the count value CNT1 (pulse width information) from the counter 122. The held count value data LTQ 1 is output to the output circuit 126.

  The output circuit 126 (filter circuit, noise removal circuit) receives the count value data LTQ1 held in the count value holding circuit 124 and outputs data PWQ1 (first pulse width information). The output circuit 126 can include, for example, a comparison circuit 130 that compares the count value held this time in the count value holding circuit 124 with the count value held last time and outputs the larger count value. As a result, the maximum count value is held and output from the output circuit 126. This makes it possible to suppress fluctuations in the pulse width period due to noise or the like, and to realize stable pulse width detection. Further, the combination with the amplitude detection method can be facilitated.

  FIG. 17 shows an example of a signal waveform for explaining the operation of the circuit of FIG. When the waveform shaping signal WFQ1 becomes L level at the timing of D1 in FIG. 17, the reset of the flip-flop circuit FFC1 is released. Then, at the falling edge timing TF of the drive clock DRCK, the VDD voltage is taken into the flip-flop circuit FFC1, and the enable signal ENQ1 changes from L level to H level. As a result, the counter 122 starts the counting process, and measures the pulse width period TPW1 using the reference clock CLK.

  Next, when the waveform shaping signal WFQ1 becomes H level at the first timing TM1, the flip-flop circuit FFC1 is reset and the enable signal ENQ1 changes from H level to L level. Thereby, the count process of the counter 122 is completed. Then, the count value obtained by this counting process becomes a measurement result representing the pulse width period TPW1.

  As shown in FIG. 17, the sum of the pulse width periods TPW1 and XTPW1 is a half cycle period of the drive clock DRCK. The pulse width period XTPW1 in FIGS. 14A to 14C becomes longer as the load on the power receiving side becomes higher. Therefore, the pulse width period TPW1 of FIG. 17 becomes shorter as the power receiving side load increases. In the pulse width period XTPW1 in FIGS. 14A to 14C, there is a problem that it is difficult to distinguish between the noise signal and the pulse signal when the load on the power receiving side is low, but the pulse width period TPW1 in FIG. Then, such a problem can be prevented.

  In the first method of the pulse width detection method of this embodiment, as shown in D3 of FIG. 17, based on the timing TM1 when the coil end signal CSG changes from 0 V and exceeds the threshold voltage VTL on the low potential side, A pulse width period TPW1 is defined. That is, the pulse width period TPW1 is a period between the falling edge timing TF of the drive clock CLK and the timing TM1, and the pulse width period TPW1 is changed by changing the timing TM1 due to load fluctuation on the power receiving side. Since the threshold voltage VTL for determining the timing TM1 is a low voltage, there is little variation in the timing TM1 even when the power supply voltage or the like fluctuates. Even when the distance and the positional relationship between the coils L1 and L2 vary, there is little variation in the timing TM1. Therefore, according to the first method of the present embodiment, it is possible to realize a pulse width detection method in which the adverse effects of fluctuations in the power supply voltage and the like are small.

  In the rectifier circuit 17 of FIG. 16, unlike the rectifier circuit 18 for the second system of the present embodiment shown in FIG. 22 described later, the waveform shaping circuit is generated as the induced voltage signal PHIN1 without dividing the coil end signal CSG. 32. Accordingly, the threshold voltage VTL of FIG. 17 is substantially equal to the threshold voltage of the N-type transistor TC1 of the waveform shaping circuit 32 of FIG. 16, and the threshold voltages of FIGS. 14 (A) to 14 (C). It becomes almost equal to VT1.

  Note that the configuration of the waveform shaping circuit 32 is not limited to the configuration of FIG. 16, and may be configured by, for example, a comparator. Further, the configuration of the enable signal generation circuit 120 is not limited to the configuration of FIG. 16, and may be configured by a logic circuit such as a NOR circuit or a NAND circuit. Also, the configuration of the output circuit 126 is not limited to the configuration of FIG. 16, and may be configured by an averaging circuit that obtains an average value (moving average) of count values (for example, the current count value and the previous count value), for example. Good.

5). Second Configuration Example of Power Transmission Device FIG. 18 illustrates a second configuration example of the power transmission device 10. FIG. 18 corresponds to a fourth configuration example of the waveform monitor circuit 14 of FIG. Note that the power transmission device 10 may be configured so that the waveform monitor circuit 14 of the power transmission device illustrated in FIG. 18 corresponds to the fifth configuration example illustrated in FIG. 11.

  In FIG. 18, the waveform detection circuit 30 detects a waveform change of the second induced voltage signal PHIN2 of the primary coil L1 in addition to the first waveform detection circuit 31 described in FIGS. A waveform detection circuit 34 is included. Here, the first waveform detection circuit 31 performs the pulse width detection of the first method described with reference to FIGS. 14A to 14C and the like. On the other hand, the second waveform detection circuit 34 performs pulse width detection of the second method, which will be described later with reference to FIGS. 19 (A) to 19 (C).

  The second waveform detection circuit 34 includes a second waveform shaping circuit 35 and a second pulse width detection circuit 36. The waveform shaping circuit 35 shapes the induced voltage signal PHIN2 of the primary coil L1, and outputs a waveform shaping signal WFQ2. Specifically, for example, a square wave (rectangular wave) waveform shaping signal WFQ2 that is active (eg, H level) when the signal PHIN2 exceeds a given threshold voltage is output.

  The pulse width detection circuit 36 detects the pulse width information of the induced voltage signal PHIN2 of the primary coil L1. Specifically, the pulse of the induced voltage signal PHIN2 is received by receiving the waveform shaping signal WFQ2 from the waveform shaping circuit 35 and the drive clock DRCK from the drive clock generation circuit 25 and detecting the pulse width information of the waveform shaping signal WFQ2. Detect width information.

  For example, the timing when the induced voltage signal PHIN2 changes from the high potential power supply (VDD) side and falls below the second threshold voltage VT2 is set as the second timing. In this case, the pulse width detection circuit 36 measures a second pulse width period, which is a period between the second edge timing (for example, rising edge timing) of the drive clock DRCK and the second timing, The pulse width information is detected. For example, the second pulse width period in which the voltage signal PHIN2 induced by the voltage change of the drive clock DRCK is equal to or higher than a given threshold voltage VT2 is measured. Then, the magnitude of the pulse width of the waveform shaping signal WFQ2 (induced voltage signal) with respect to the pulse width of the drive clock DRCK is measured. In this case, the pulse width period is measured using, for example, the reference clock CLK. Then, data PWQ2 as a result of measurement by the pulse width detection circuit 36 is latched by, for example, a latch circuit (not shown). Specifically, the pulse width detection circuit 36 measures the pulse width period using a counter that increments (or decrements) the count value by the reference clock CLK, and the measurement result data PWQ2 is latched by the latch circuit. .

  Then, the control circuit 22 performs foreign matter detection (secondary foreign matter detection) based on the pulse width information detected by the pulse width detection circuit 36. Alternatively, the data transmitted by the power receiving device 40 by load modulation is detected.

  19A to 19C show measurement results of signal waveforms of the drive clock DRCK, the coil end signal CSG, the induced voltage signal PHIN2, and the pulse signal PLS2. FIG. 19A, FIG. 19B, and FIG. 19C are signal waveforms in the case of low load, medium load, and high load, respectively. The pulse signal PLS2 used for pulse width detection becomes H level at the second timing TM2 when the induced voltage signal PHIN2 falls below the second threshold voltage VT2, and becomes L at the falling edge timing TF of the drive clock DRCK. It is a signal that becomes a level. Note that as the threshold voltage VT2 (for example, the threshold voltage of an N-type transistor) for measuring the pulse width period, a voltage that optimizes the load state detection accuracy may be appropriately selected and set.

  As shown in FIGS. 19A to 19C, the pulse width period XTPW2 of the pulse signal PLS2 becomes longer as the load on the power receiving side becomes higher. Therefore, the load state on the power receiving side can be detected by measuring the pulse width period XTPW2. Specifically, it is possible to detect a foreign object (secondary foreign object detection) or whether transmission data (save frame) from the power receiving side is “0” or “1”.

  In FIGS. 19A to 19C, a period from the timing TM2 to the falling edge timing TF of the drive clock DRCK is defined as a pulse width period XTPW2. That is, in this case, the second waveform detection circuit 34 detects the pulse width period XTPW2 of the pulse signal PLS2 as the second pulse width information. However, as shown in FIG. 23 to be described later, the period from the rising edge timing TR of DRCK to the timing TM2 is defined as the pulse width period TPW2, and the second waveform detection circuit 34 sets the pulse width period TPW2 to the second pulse width. It is desirable to detect as information. In this way, it is possible to prevent a situation in which the noise signal is regarded as a pulse signal and the pulse width period is measured when the load on the power receiving side is low. In this case, the pulse width period TPW2 becomes shorter as the load on the power receiving side becomes higher.

  The second method (falling detection method) in FIGS. 19A to 19C has less load fluctuation than the first method (rising detection method) in FIGS. 14A to 14C. However, there is an advantage that the pulse width (count value) changes greatly and the sensitivity is high. On the other hand, the first method in FIGS. 14A to 14C is different from the second method in FIGS. 19A to 19C in that the power supply voltage fluctuation, the distance between the coils L1 and L2, and so on. There is an advantage that the variation in the detection of the pulse width is small with respect to the fluctuation of the positional relationship.

  For example, FIG. 20A is a diagram showing detection variation in pulse width with respect to power supply voltage fluctuation in the first method, and FIG. 20B shows detection variation in pulse width with respect to power supply voltage fluctuation in the second method. FIG.

  As shown in FIG. 20A, in the first method, the load current-pulse width characteristic curve does not vary so much even if the power supply voltage increases or decreases. On the other hand, as shown in FIG. 20B, in the second method, when the power supply voltage becomes higher or lower, the load current-pulse width characteristic curve also fluctuates, and the detection variation of the pulse width with respect to the power supply voltage fluctuation is large. .

  Therefore, in the second configuration example of FIG. 18, in the primary foreign object detection that is the foreign object detection before the start of normal power transmission, the first waveform detection circuit 31 performs the waveform detection by the first method, and the obtained first The pulse width information (PWQ1) is used. On the other hand, in secondary foreign object detection that is foreign object detection after the start of normal power transmission, the second waveform detection circuit 34 performs waveform detection by the second method, and uses the second pulse width information (PWQ2) obtained thereby. . Further, data transmitted from the power receiving side (data notifying full charge detection or the like) is also detected using, for example, second pulse width information.

  FIG. 21 shows a flowchart for explaining these primary foreign object detection and secondary foreign object detection.

  First, the primary side (power transmission device side) is activated (step S21), and the activated primary side transmits power for activating the secondary side (position detection power) (step S22), and is in a communication standby state. (Step S23). Then, the secondary side (power receiving apparatus side) is activated (step S31), and an authentication frame (synchronization ID) is transmitted to the primary side by the load modulation described with reference to FIG. 3B (step S32).

  When the primary side receives the authentication frame, it performs ID authentication (step S24). Then, the drive frequency (DRCK frequency) is set to the foreign object detection frequency F2, which is a frequency different from the normal power transmission frequency F1. Specifically, the foreign object detection frequency F2 which is a frequency between the normal power transmission frequency F1 and the coil resonance frequency F0 is set.

  Then, the primary side performs primary foreign object detection in a state where the drive frequency is set to the foreign object detection frequency F2 in this way (step S26). Specifically, primary foreign matter detection is performed by the first waveform detection circuit 31 performing waveform detection using the first method described with reference to FIGS. 14A to 14C.

  Next, the primary side sets the drive frequency to the normal power transmission frequency F1 and starts normal power transmission (step S27), whereby the secondary side receives power (step S33).

  After the normal power transmission starts in this way, the secondary side performs secondary foreign object detection (step S28). Specifically, secondary foreign matter detection is performed by the second waveform detection circuit 34 performing waveform detection by the second method described with reference to FIGS. 19A to 19C. In this case, it is desirable to perform secondary foreign object detection periodically after normal power transmission starts.

  When the secondary side detects the full charge of the load, it notifies the end of normal power transmission (step S34), and thereby the primary side ends normal power transmission (step S29).

  In FIG. 21, primary foreign matter detection is performed, for example, in a no-load state before the start of normal power transmission. The primary foreign matter detection is performed by the first method with little variation with respect to power supply voltage fluctuation or the like as shown in FIG. Accordingly, even when there is a power supply voltage fluctuation or the like, stable foreign object detection is possible, and the pulse width count obtained in the primary foreign object detection can be set as a reference value. Based on the reference value in the no-load state, secondary foreign matter detection after normal power transmission can be performed, and “0” and “1” of data transmitted from the power receiving side can be detected. Load variation can be detected.

  FIG. 22 shows a specific example of the second configuration example of the power transmission device 10 of the present embodiment. In FIG. 22, the waveform shaping circuit 35 of the second waveform detection circuit 34 has the same configuration as the waveform shaping circuit 32 of the first waveform detection circuit 31. In the enable signal generation circuit 140 of the second waveform detection circuit 34, the drive clock DRCK is input to the non-inverted clock terminal of the flip-flop circuit FFC2, and the waveform shaping signal WFQ2 is input to the inverted reset terminal. The other configurations of the counter 142, count value holding circuit 144, and output circuit 146 of the second waveform detection circuit 34 are the same as those of the counter 122, count value holding circuit 124, and output circuit 126 of the first waveform detection circuit 31. It is.

  FIG. 23 shows a signal waveform example for explaining the operation of the circuit of FIG. When the waveform shaping signal WFQ2 becomes H level at the timing D2 in FIG. 23, the reset of the flip-flop circuit FFC2 is released. Then, at the rising edge timing TR of the drive clock DRCK, the VDD voltage is taken into the flip-flop circuit FFC2, and the enable signal ENQ2 changes from L level to H level. As a result, the counter 142 starts the counting process, and measures the pulse width period TPW2 using the reference clock CLK.

  Next, when the waveform shaping signal WFQ2 becomes L level at the second timing TM2, the flip-flop circuit FFC2 is reset, and the enable signal ENQ2 changes from H level to L level. Thereby, the count process of the counter 142 is completed. And the count value obtained by this count process becomes a measurement result representing the pulse width period TPW2.

  As shown in FIG. 23, the sum of the pulse width periods TPW2 and XTPW2 is a half cycle period of the drive clock DRCK. The pulse width period XTPW2 in FIGS. 19A to 19C becomes longer as the load on the power receiving side becomes higher. Therefore, the pulse width period TPW2 in FIG. 23 becomes shorter as the power receiving side load increases. In the pulse width period XTPW2 in FIGS. 19A to 19C, there is a problem that it is difficult to distinguish between the noise signal and the pulse signal when the load on the power receiving side is low, but the pulse width period TPW2 in FIG. Then, such a problem can be prevented.

  As shown at D3 in FIG. 23, the timing TM1 is determined using the threshold voltage VTL on the low potential side in the first method, and the threshold voltage VTH on the high potential side in the second method as shown in D4. Is used to determine the timing TM2.

  In the first method for determining the timing TM1 using the threshold voltage VTL on the low potential side as indicated by D3 in FIG. 23, if the rectifier circuit 18 for the second method as shown in FIG. 22 is used, the resistor RA2 As a result of voltage division by RA3, the waveform may be crushed and the detection accuracy may be degraded.

  In this regard, in the rectifier circuit 17 for the first system shown in FIG. 22, the signal PHIN1 obtained by clamping and half-wave rectifying the coil end signal CSG without performing voltage division using a resistor, Can be input to the waveform monitor circuit 31. Therefore, the pulse width can be detected based on a clean waveform signal PHIN1 that is not subjected to voltage division using a resistor, so that the detection accuracy can be improved. Further, by providing the diodes DA1 and DA2, it is possible to prevent a situation in which the signal PHIN1 exceeds the maximum rated voltage or a negative voltage is input to the first waveform detection circuit 31.

  On the other hand, in the rectifier circuit 18 for the second method, the signal PHIN2 that is voltage-divided by the resistors RA2 and RA3 is input to the N-type transistor TC2 of the waveform shaping circuit 35. By performing voltage division in this way, a situation where the signal PHIN2 exceeds the maximum rated voltage can be prevented, and the threshold voltage VTH can be set to the high potential side as indicated by D4 in FIG. That is, signals PHIN1 and PHIN2 are input to the gates of N-type transistors TC1 and TC2 having the same threshold voltage, respectively. However, since the signal PHIN2 is a signal that is voltage-divided by the resistors RA2 and RA3, when viewed from the coil end signal CSG, the threshold voltage indicated by D4 is larger than the threshold voltage VTL indicated by D3. VTH becomes a high voltage. When the threshold voltage VTH is set to a high voltage as described above, the change in the pulse width with respect to the load change becomes large, and the load change detection with high sensitivity can be realized. Therefore, secondary foreign object detection after the start of normal power transmission and determination of “1” and “0” of data transmitted from the secondary side can be properly realized.

  In FIG. 22, the first and second rectifier circuits 17 and 18 for detecting the pulse width of the first method and the second method are provided. In addition, the first and second rectifier circuits 17 and 18 for detecting the pulse width are used. Three rectifier circuits may be provided. In addition to the first and second waveform detection circuits, a third waveform detection circuit to which the third induced voltage signal from the third rectifier circuit for peak detection is input may be provided. In this case, the third waveform detection circuit detects a change in the load on the power receiving side by detecting a change in the peak of the third induced voltage signal. Such a third waveform detection circuit can include, for example, an amplitude detection circuit that performs a peak hold operation, an A / D conversion circuit that performs A / D conversion of a signal peak-held by the amplitude detection circuit, and the like. By providing such a third rectifier circuit and a third waveform detection circuit for amplitude detection and combining peak detection and pulse width detection, more intelligent waveform detection can be realized.

  FIG. 24 shows a detailed configuration example of the third waveform detection circuit 37 included in the waveform detection circuit 30 of the fifth configuration example of FIG.

  As illustrated in FIG. 24, the third waveform detection circuit 37 includes an amplitude detection circuit 331, an A / D conversion circuit 332, and a latch circuit 333. The amplitude detection circuit 331 includes operational amplifiers OPA1 and OPA2, a holding capacitor CA3, and a reset N-type transistor TA1. In the operational amplifier OPA1, the signal PHIN3 is input to its non-inverting input terminal, and the output node NA5 of the operational amplifier OPA2 is connected to its inverting input terminal. The holding capacitor CA3 and the reset transistor TA1 are provided between a peak voltage holding node NA4, which is an output node of the operational amplifier OPA1, and the GND (low potential side power supply). The operational amplifier OPA2 has a holding node NA4 connected to its non-inverting input terminal and an output node NA5 of OPA2 connected to its inverting input terminal, thereby constituting a voltage follower-connected operational amplifier. Note that a voltage follower-connected operational amplifier may be further provided after the operational amplifier OPA2.

  The peak hold circuit (peak detection circuit) is configured by the operational amplifiers OPA1 and OPA2, the holding capacitor CA3, and the reset transistor TA1 in FIG. That is, the peak voltage of the detection signal PHIN3 from the third rectifier circuit 191 of the waveform monitor circuit 14 is held at the holding node NA4, and the held peak voltage signal is impedance-converted by the operational amplifier OPA2 connected to the voltage follower. Output to the node NA5.

  In the reset transistor TA1, the gate is turned on during the reset period, and the charge of the holding node NA4 is discharged to the GND side. That is, the operational amplifier OPA1 is a type of operational amplifier that only accumulates charges in the holding capacitor CA3 and cannot discharge charges to the GND side. For this reason, it can follow the rise of the peak voltage of the signal PHIN3, but cannot follow the fall of the peak voltage. In addition, since a leakage current is present in the charge storage P-type transistor provided at the output section of the operational amplifier OPA1, the voltage at the holding node NA4 is increased after a long time even when the P-type transistor is off. It will rise. For this reason, it is necessary to periodically reset the voltage of the holding node NA4. For the above reason, in FIG. 24, the reset transistor TA1 is provided in the holding node NA4.

  For example, in this embodiment, the power receiving side detects (extracts) a clock from the AC voltage on the power transmission side, and performs load modulation in synchronization with this clock. Accordingly, the load modulation on the power receiving side is performed in synchronization with the clock on the power transmission side, so that the power transmission side can uniquely know the timing of load modulation on the power receiving side. Therefore, the control circuit 22 specifies the load switching timing of the load modulation on the power receiving side, and performs reset control for discharging the charge of the holding node NA4 to the GND side in the reset period including the specified switching timing. In this way, an appropriate peak hold operation can be realized even when the operational amplifier OPA1 of a type that cannot follow the fall of the peak voltage is employed. Further, by periodically resetting the voltage of the holding node NA4 in the standby mode waiting for the peak voltage to exceed the provisional specified voltage SIGH0, it is possible to prevent the holding voltage from increasing due to the leakage current of the P-type transistor of the operational amplifier OPA1.

  FIG. 25 shows an example of a signal waveform for explaining the operation of the amplitude detection circuit 331. As shown in FIG. 25, the signal PHIN3 is a signal half-wave rectified by a third rectifier circuit 191 that is a half-wave rectifier circuit. The output signal OPQ of the operational amplifier OPA1 rises during the pulse generation period of the signal PHIN3, and is held and maintained in the holding capacitor CA3 during the non-pulse generation period. The output signal PHQ of the operational amplifier OPA2 smoothly follows the peak of the signal PHIN.

  The A / D conversion circuit 332 includes a sample and hold circuit 334, a comparator CPA 1, a successive approximation register 336, and a D / A conversion circuit 335. The sample hold circuit 334 samples and holds the signal PHQ. The comparator CPA1 compares the analog signal DAQ after D / A conversion from the D / A conversion circuit 335 and the sample hold signal SHQ from the sample hold circuit 334. The successive approximation register 336 (successive comparison control circuit) stores data of the output signal CQ1 of the comparator CPA1. The D / A conversion circuit 335 D / A converts, for example, 8-bit digital data SAQ from the successive approximation register 336, and outputs an analog signal DAQ.

  In this successive approximation A / D conversion circuit 332, the comparator CPA1 compares the signal DAQ after D / A conversion when only the MSB (most significant bit) is “1” and the input signal SHQ (PHQ). To do. If the voltage of the signal SHQ is larger, the MSB is kept at “1”, and if smaller, the MSB is set to “0”. The A / D conversion circuit 332 sequentially performs comparison processing for subsequent lower bits in the same manner. Then, the finally obtained digital data ADQ is output to the latch circuit 333. Note that the A / D conversion circuit 332 is not limited to the configuration shown in FIG. 24, and may be, for example, a successive approximation A / D conversion circuit having a different circuit configuration, a tracking comparison type, a parallel comparison type, or a double comparison type. An A / D conversion circuit such as an integral type may be used.

  By using the third waveform detection circuit 37 configured as shown in FIG. 24, for example, removal detection (detachment detection) for detecting that the mobile phone 510 of FIG. Can be realized. That is, when such removal is performed, as is apparent from FIG. 3B, the amplitude of the coil end signal CSG changes. In FIG. 24, the amplitude (peak voltage) of the coil end signal CSG is detected by the amplitude detection circuit 331, and the detected amplitude is converted into a digital value by the A / D conversion circuit 332. Then, the control circuit 22 compares the digital value corresponding to the obtained amplitude (peak voltage) with the digital value corresponding to the threshold voltage, so that the coil end signal as shown in FIG. A change in the amplitude of the CSG is detected to detect that the mobile phone 510 has been removed from the charger 500.

  On the other hand, the first waveform detection circuit 31 of FIG. 11 performs primary foreign object detection before the start of normal power transmission in step S26 of FIG. 21 by detecting the waveform of the first method (rising detection method).

  Also, the second waveform detection circuit 34 in FIG. 11 performs secondary foreign object detection after the start of normal power transmission in step S28 in FIG. 21 by displaying the waveform of the second method (falling detection method) or from the power receiving side. Detects data that is transmitted.

  Thus, in FIG. 11, the first waveform detection circuit 31 performs primary object detection, the second waveform detection circuit 34 performs secondary foreign object detection and data detection, and the third waveform detection circuit 37 removes and detects. I do. Thus, by using each waveform detection circuit properly, more intelligent waveform detection can be realized.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (GND, VDD, mobile phone / charger, etc.) described together with different terms (low-potential power supply, high-potential power supply, electronic device, etc.) in a broader sense or the same meaning at least once The different terms can be used anywhere in the specification or drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configuration and operation of the power transmission control device, the power transmission device, the power reception control device, the power reception device, and the pulse width detection method are not limited to those described in the present embodiment, and various modifications can be made.

1A and 1B are explanatory diagrams of contactless power transmission. 1 is a configuration example of a power transmission device, a power transmission control device, a power reception device, and a power reception control device of the present embodiment. 3A and 3B are explanatory diagrams of data transfer by frequency modulation and load modulation. The flowchart for demonstrating the outline | summary of operation | movement of the power transmission side and the power receiving side. 1 is a first configuration example of a waveform monitor circuit of the present embodiment. 2 shows a second configuration example of a waveform monitor circuit according to the present embodiment. The 3rd structural example of the waveform monitor circuit of this embodiment. The 4th structural example of the waveform monitor circuit of this embodiment. The signal waveform example for demonstrating operation | movement of a waveform monitor circuit. The signal waveform example for demonstrating operation | movement of a waveform monitor circuit. The 5th structural example of the waveform monitor circuit of this embodiment. The signal waveform example for demonstrating operation | movement of a waveform monitor circuit. The 1st structural example of the power transmission apparatus of this embodiment. 14A to 14C show signal waveform measurement results for explaining the pulse width detection of the first method. 15A to 15C are an equivalent circuit and a resonance characteristic diagram when there is no load and when there is a load. The specific example of the 1st structural example of a power transmission apparatus. The signal waveform example for demonstrating operation | movement of the 1st structural example of a power transmission apparatus. The 2nd structural example of the power transmission apparatus of this embodiment. 19A to 19C show signal waveform measurement results for explaining the pulse width detection of the second method. 20A and 20B are diagrams for explaining variation in pulse width detection due to power supply voltage fluctuation. The flowchart for demonstrating a primary foreign material detection and a secondary foreign material detection. The specific example of the 2nd structural example of a power transmission apparatus. The signal waveform example for demonstrating operation | movement of the 2nd structural example of a power transmission apparatus. 9 is a detailed configuration example of a third waveform detection circuit included in the waveform detection circuit. 9 is a signal waveform example for explaining the operation of the amplitude detection circuit of the third waveform detection circuit.

Explanation of symbols

L1 primary coil, L2 secondary coil,
DESCRIPTION OF SYMBOLS 10 Power transmission apparatus, 12 Power transmission part, 14 Waveform monitor circuit, 16 Display part,
17, 18, 19 Rectifier circuit, 20 power transmission control device, 22 control circuit (power transmission side),
24 oscillation circuit, 25 drive clock generation circuit, 26 driver control circuit,
30 waveform detection circuit, 31 first waveform detection circuit, 32 first waveform shaping circuit,
33 first pulse width detection circuit, 34 second waveform detection circuit,
35 second waveform shaping circuit, 36 second pulse width detection circuit,
37 third waveform detection circuit, 40 power receiving device, 42 power receiving unit,
43 rectifier circuit, 46 load modulation unit, 48 power supply control unit, 50 power reception control device,
52 control circuit (power receiving side), 56 position detection circuit, 58 oscillation circuit,
60 frequency detection circuit, 62 full charge detection circuit, 90 load, 92 charge control device,
94 battery,
120 enable signal generation circuit, 122 counter, 124 count value holding circuit,
126 output circuit, 130 comparison circuit 140 enable signal generation circuit, 142 counter, 144 count value holding circuit,
146 Output circuit, 150 comparison circuit

Claims (15)

A power transmission device of a non-contact power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power to a power receiving device and supplies power to a load of the power receiving device,
Based on the coil end signal of the primary coil, and a waveform monitor circuit for generating and outputting a EMF signal,
Controls the power transmitting driver that drives the primary coil, and a power transmission control device for detecting a load state before Symbol power receiving side by detecting a change in waveform of the induced voltage signal,
The waveform monitor circuit includes a rectifier circuit,
The rectifier circuit is
A coil-end node where the coils end signal is generated, a first resistor is a current limiting resistor provided between the motor Nitanodo that the induced voltage signal is generated,
A first diode provided between the monitor node and the high potential power supply node and having a forward direction from the monitor node to the high potential power supply node;
A second diode provided between the monitor node and the low potential power supply node and having a forward direction from the low potential power supply node to the monitor node;
A capacitor provided between a low-potential-side resistance end node between the first resistor and the second diode, and the coil end node;
A power transmission device comprising: A power transmission device of a non-contact power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power to a power receiving device and supplies power to a load of the power receiving device,
Based on the coil end signal of the primary coil, and a waveform monitor circuit for generating and outputting a EMF signal,
Controls the power transmitting driver that drives the primary coil, and a power transmission control device for detecting a load state before Symbol power receiving side by detecting a change in waveform of the induced voltage signal,
The waveform monitor circuit includes:
A first rectifier circuit that outputs a first induced voltage signal via a first monitor node;
Including a second rectifier circuit that outputs a second induced voltage signal via a second monitor node;
The power transmission control device includes:
A first waveform detection circuit having a first pulse width detection circuit for detecting first pulse width information from the first induced voltage signal output from the first rectifier circuit;
A second waveform detection circuit having a second pulse width detection circuit for detecting second pulse width information from the second induced voltage signal output from the second rectifier circuit;
A drive clock generation circuit that generates and outputs a drive clock that defines the drive frequency of the primary coil;
A driver control circuit that generates a driver control signal based on the drive clock and outputs the driver control signal to a power transmission driver that drives the primary coil;
A control circuit for detecting a load state on the power receiving side based on detection results in the first and second waveform detection circuits,
The control circuit includes:
Based on the first pulse width information, primary foreign object detection that is foreign object detection before the start of normal power transmission is performed,
A power transmission apparatus that performs secondary foreign object detection, which is foreign object detection after the start of normal power transmission, based on the second pulse width information . In claim 2 ,
The first rectifier circuit includes:
A first resistor which is a current limiting resistor provided between a coil end node where a coil end signal of the primary coil is generated and the first monitor node;
A first diode provided between the first monitor node and the high-potential power supply node and having a forward direction from the first monitor node to the high-potential power supply node;
A second diode provided between the first monitor node and the low-potential power supply node and having a forward direction from the low-potential power supply node toward the first monitor node; Power transmission device. In claim 2 ,
The first rectifier circuit includes:
A first resistor which is a current limiting resistor provided between a coil end node where a coil end signal of the primary coil is generated and the first monitor node;
A power transmission apparatus comprising a Zener diode provided between the first monitor node and a low potential power supply node and having a forward direction from the low potential power supply node to the first monitor node. . In claim 2 ,
The first rectifier circuit includes:
A first resistor which is a current limiting resistor provided between a coil end node where a coil end signal of the primary coil is generated and the first monitor node;
A first diode provided between the first monitor node and the high-potential power supply node and having a forward direction from the first monitor node to the high-potential power supply node;
A second diode provided between the first monitor node and the low potential power supply node and having a forward direction from the low potential power supply node to the first monitor node;
A capacitor provided between a low-potential-side resistance end node between the first resistor and the second diode, and the coil end node;
A power transmission device comprising: In any of claims 2 to 5 ,
The second rectifier circuit includes:
A second resistor provided between the coil end node and the second monitor node;
A third resistor provided between the second monitor node and the low potential power supply node;
And a third diode provided between the second monitor node and the low potential power supply node and having a forward direction from the low potential power supply node to the second monitor node. Power transmission equipment. In any one of Claims 2 thru | or 6 .
The first pulse width detection circuit includes:
When the first induced voltage signal changes from the low potential power supply side and exceeds the first threshold voltage as the first timing, the first edge timing of the drive clock and the first power transmitting apparatus characterized that you are is by a first pulse width period and measurement period, to detect the first pulse width information between timing. In claim 7,
The first waveform detection circuit includes:
Including a first waveform shaping circuit that shapes the first induced voltage signal and outputs a first waveform shaping signal;
The first pulse width detection circuit includes:
A power transmission apparatus that measures the first pulse width period based on the first waveform shaping signal and the drive clock. In claim 8,
The first pulse width detection circuit includes:
And a first counter that increments or decrements a count value in the first pulse width period and measures a length of the first pulse width period based on the obtained count value. apparatus. In any one of Claims 7 thru | or 9 ,
The second pulse width detection circuit includes:
When the second induced voltage signal changes from the high-potential power supply side and falls below the second threshold voltage as the second timing, the second edge timing of the drive clock and the second power transmitting apparatus characterized that you are is by the second pulse width period and measurement period, to detect the second pulse width information between timing. In claim 10 ,
The second waveform detection circuit includes:
A second waveform shaping circuit for shaping the second induced voltage signal and outputting a second waveform shaping signal;
The second pulse width detection circuit includes:
A power transmission device that measures the second pulse width period based on the second waveform shaping signal and the drive clock. In claim 11 ,
The second pulse width detection circuit includes:
And a second counter for incrementing or decrementing a count value in the second pulse width period and measuring a length of the second pulse width period based on the obtained count value. apparatus. An electronic apparatus comprising a power transmission device according to any one of claims 1 to 12. Waveform monitoring circuit for a power transmission device of a contactless power transmission system that electromagnetically couples a primary coil and a secondary coil to transmit power to a power receiving device and supplies power to a load of the power receiving device Because
The waveform monitor circuit includes a first rectifier circuit,
The first rectifier circuit includes:
A coil end node coil end signal of the primary coil is generated, a first resistor is a current limiting resistor that is provided between the first monitoring node first induced voltage signal is generated,
A first diode provided between the first monitor node and the high-potential power supply node and having a forward direction from the first monitor node to the high-potential power supply node;
A second diode provided between the first monitor node and the low potential power supply node and having a forward direction from the low potential power supply node to the first monitor node;
A capacitor provided between a low-potential-side resistance end node between the first resistor and the second diode, and the coil end node ;
A waveform monitor circuit comprising: In claim 14,
The waveform monitor circuit includes a second rectifier circuit,
The second rectifier circuit includes:
A second resistor which is a current limiting resistor provided between the coil end node and a second monitor node where a second induced voltage signal is generated;
A third resistor provided between the second monitor node and the low potential power supply node;
A third diode provided between the second monitor node and the low potential power supply node and having a forward direction from the low potential power supply node to the second monitor node ;
A waveform monitor circuit comprising:

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