CN114299737B - Synchronous timing signal generating device for internet connection signal lamp - Google Patents
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- CN114299737B CN114299737B CN202111469903.0A CN202111469903A CN114299737B CN 114299737 B CN114299737 B CN 114299737B CN 202111469903 A CN202111469903 A CN 202111469903A CN 114299737 B CN114299737 B CN 114299737B
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Abstract
The invention belongs to the field of intelligent transportation, and discloses a synchronous timing signal generating device for a network connection signal lamp, which comprises: the voltage transformation half-wave rectification circuit, the voltage generation circuit, the falling edge grabbing circuit and the waveform shaping circuit are sequentially connected. The invention can accurately judge the peak position and form a falling edge signal; if the peak position is passed during electrification, a falling edge signal can be generated in the voltage falling process of the positive half-wave of the alternating current, and the influence of small voltage amplitude is avoided; the counting and timing signals given by each device are ensured to be completely synchronous; and at the peak position. The circuit is not influenced by power-on fluctuation, the mains supply can be triggered only once in the descending process, and even if voltage fluctuation exists, the voltage fluctuation can be filtered.
Description
Technical Field
The invention belongs to the technical field of intelligent traffic, and particularly relates to a synchronous timing signal generating device for a network connection signal lamp, which is used for generating synchronous timing or counting pulse signals.
Background
The network traffic signal lamp is an intelligent traffic light with the functions of traffic signal lamps, road violation snapshot, road flow detection and the like; compared with the traditional traffic signal lamp, the lighting and extinguishing are different by controlling the on-off of 220V power supply, the network-connected traffic signal lamp needs to send a lighting scheme through a network, the association between the signal lamps is not limited by a crossing signal machine any more, and single-machine work can be carried out once the sending is completed, so that the GPS is generally used for timing to ensure the synchronization between all devices, but the GPS has the problems that the starting time is slow after the power is on, the timing failure rate is high, signal interference exists, the tunnel cannot be used and the like. The timing is partially carried out through a wireless 4G network or NB-IOT, and high later use cost exists; in addition, the intelligent network connection signal lamp generally cuts a control line, only a wired network or an optical fiber is reserved, and the wired network is easily affected by construction, later maintenance and the like, so that network connection is abnormal; if effective synchronous signals cannot be acquired, the lighting of signal lamps is asynchronous, transient green conflicts, flicker asynchronization and the like are easily caused, more importantly, the lighting scheme transmission among the networked signal lamps is used for ensuring stability, single-point transmission is adopted, after the data transmission is confirmed to be correct, the signal lamps simultaneously change the light colors and light and extinguish at appointed time according to received instructions, the small time difference can cause the lighting of the signal lamps with the same functions to be inconsistent at a certain instant, and further the condition that red lamps and green lamps are simultaneously lighted in the signal lamps (such as a main signal lamp on a rod piece and an auxiliary signal lamp in a green belt) indicating the same direction in pictures grabbed by the illegal snapshot camera is caused, so that the snapshot efficiency of the illegal snapshot system is low, and disputes are easily caused.
Therefore, the development of the internet traffic signal lamp urgently needs a device capable of carrying out accurate clock synchronization for assistance, the device does not depend on extra external timing, is stable and reliable, can adapt to asynchronous boosting in the power-on process of the intersection, and also has a device capable of accurately controlling and starting timing.
Disclosure of Invention
The device is integrated in the internet connection signal lamp, can be quickly started, can accurately count synchronously by identifying the change condition of the edge, is used for counting by identifying the waveform period and the change condition of the edge through the characteristic that the commercial power is fixed at 50 Hz, and sends counting pulses to the rear-stage signal lamp control equipment for timing.
In the process of just electrifying, although all the signal lamps are synchronously electrified at the master control position, the electrifying conditions in all directions are different due to different installation conditions of all the devices, the electricity consumption conditions are inconsistent, and the instant currents are different, so that certain difference exists among the electrifying conditions in all the directions.
According to the characteristics of the power-on process of the intersection, the voltage curve is used for counting according to the characteristics of the sine wave of the mains supply, each positive half-wave descending delay is used for timing, as long as the peak is reached and the descending occurs for the first time after the power-on, or the descending edge of the positive half-wave is sensed, even if the amplitude is small, the timing is started once, and the mains supply cycle positions where the initial timing is located are completely consistent after the synchronous power-on in all directions.
Specifically, the invention discloses a synchronous timing signal generating device for a network connection signal lamp, which comprises: the voltage transformation half-wave rectification circuit, the voltage generation circuit, the falling edge grabbing circuit and the waveform shaping circuit are sequentially connected.
Furthermore, the voltage transformation half-wave rectification circuit realizes voltage transformation and half-wave rectification on 220V mains supply and only keeps positive half-waves, wherein the alternating current input end of the mains supply is connected with 220V-L and 220V-N signals, the 220V-L signal is connected with one end of a first fuse F1, the other end of the first fuse F1 is connected with the input end of a first transformer T1, 220V-N is connected with the other pin of the input end of the first transformer T1, two pins of the output end of the T1 are connected with two ends of a TVS1, the positive electrode of a first diode D1 is connected with the output end of the T1 to form a V1-L network, and the negative electrode of a second diode D2 is connected with the other output end of the T1 to form a V1-N network; the negative electrode of the first diode D1 is connected with a VIF signal, the VIF signal is simultaneously connected with one end of the first capacitor C1 and led out of the circuit, and the positive electrode of the second diode D2 and the other end of the first capacitor C1 are connected with the GND.
Further, in the voltage generation circuit, one end of a second fuse F2 is connected to the V1-L network, the other end of the second fuse F2 is connected to the anode of a third diode D3 and the cathode of a fourth diode D4, the V1-N network is connected to the anode of a sixth diode D6 and the cathode of a seventh diode D7, the cathode of the third diode D3 is connected to the cathode of the sixth diode D6 and the anode of a fifth diode D5, the cathode of the fifth diode D5 is connected to the anode of a second capacitor C2 and one end of a first resistor R1, the other end of the first resistor R1 is connected to one end of a third capacitor C3 and the 3 pin of the first chip U1 to form a VCC1 network, the anode of the fourth diode D4, the anode of the seventh diode D7, the other end of the second capacitor C2, the other end of the third capacitor C3, the 1 pin of the first chip U1 is connected to form a GND, the 2 pin of the first chip U1 is connected to one end of the fourth capacitor C4, and the fourth capacitor C2 is connected to form a GND; the voltage generation circuit realizes the reshaping and rectification of the V1-L and V1-N alternating currents and generates VCC1, the voltage can be generated quickly after being electrified, the voltage is not lower than VIF, and VCC2 is generated through the first chip U1.
Furthermore, a VIF signal is used as an input signal of the falling edge capture circuit, the VIF signal is connected to a cathode of a twelfth diode D10, one end of a fourth resistor R4 and one end of a seventh resistor R7, an anode of the twelfth diode D10 is connected to GND, a pin 2 of a second chip U2 is connected to the other end of the fourth resistor R4, a V + end of the second chip U2 is connected to the network VCC1 and one end of a sixth capacitor C6, the other end of the sixth capacitor C6 is connected to GND, a V-end of the second chip U2 is connected to GND, a pin 1 is connected to one end of a second resistor R2 and a cathode of an eighth diode D8, a pin 3 is connected to an anode of the eighth diode D8, an anode of a ninth diode D9 and one end of a sixth resistor R6, and the other end of the second resistor R2 is connected to one end of a third resistor R3, a cathode of the ninth diode D9 and one end of a fifth resistor R5 to form a VHF network which is used as an output signal network of the falling edge capture circuit;
the other end of the third resistor R3 is connected with one end of a fifth capacitor C5, the other end of the fifth capacitor C5 is connected with GND, the other end of the seventh resistor R7 is connected with one end of a ninth resistor R9 and a pin 2 of a third chip U3, the other end of the ninth resistor R9 is connected with GND, a pin 1 of the third chip U3 is connected with the other end of a sixth resistor R6, a V + pin is connected with a VCC1 network and one end of the seventh capacitor C7, the other end of C7 is connected with GND, a V-pin of the third chip U3 is connected with GND, and a pin 3 is connected with one end of the sixth capacitor C6, one end of an eighth resistor C8 and a pin 1 of the first MOS transistor Q1; the other end of the C8, the other end of the R8 and the pin 3 of the Q1 are connected with GND, and the pin 2 of the Q1 is connected with the other end of a fifth resistor R5; the falling edge grabbing circuit is used for realizing peak value detection of the transformed and half-wave rectified mains supply signal VIF through the second chip U2 related circuit, so that the VHF signal is changed into 0V immediately after the VIF signal rises to the highest point, and a falling edge signal is generated at the position of the peak value of the input voltage; at the moment of powering on the signal lamp, the pin 3 of the second chip U2 may generate a high voltage at the moment of powering on.
Further, the input signal of the waveform shaping circuit is a VHF network signal, the output signal is VOFA, and the VOFA is used as a final clock signal and output to the control circuit of the signal lamp; one end of a twelfth resistor R12 of the waveform shaping circuit is connected with a VHF network, the other end of the twelfth resistor R12 is connected with a pin 2 of a fourth chip U4, a pin 1 of the fourth chip U4 is connected with a pin 3 of the U4 and one end of a tenth resistor R10, a pin V + of the fourth chip U4 is connected with the VCC1 network and one end of a ninth capacitor C9, the other end of the ninth capacitor C9 is connected with GND, a pin V-of the fourth chip U4 is connected with GND, and the other end of the tenth resistor R10 is connected with one end of an eleventh resistor R11, one end of a tenth capacitor C10, the negative electrode of an eleventh diode D11 and a pin 1 of a fifth chip U5; the other end of the eleventh resistor R11, the other end of the tenth capacitor C10, and the anode of the eleventh diode D11 are connected to GND, a V + pin of a fifth chip U5 is connected to the VCC2 network and one end of the eleventh capacitor C11, the other end of the eleventh capacitor C11 is connected to GND, a pin 2 of the fifth chip U5 is connected to one end of a thirteenth resistor R13, one end of a fifteenth resistor R15, and one end of a thirteenth capacitor C13, the other end of the thirteenth capacitor R13 is connected to the VCC2 network, the other ends of the fifteenth resistor R15 and the C13 are connected to GND, a V-pin of the fifth chip U5 is connected to GND, and a pin 3 of the fifth chip U5 is connected to one end of a twelfth capacitor C12, one end of a fourteenth resistor R14, the cathode of a twelfth diode D12, and the anode of a thirteenth diode D13; the other end of the twelfth capacitor C12, the other end of the fourteenth resistor R14 and the anode of the twelfth diode D12 are connected to GND, the cathode of the thirteenth diode D13 is connected to a VOFA network, and the VOFA network is used as an input signal of the waveform shaping circuit; the VHF signal is driven and enhanced by the fourth chip U4, the voltage of the signal is reduced through the voltage division of the tenth resistor R10 and the eleventh resistor R11, and meanwhile, a square wave is output through the voltage comparison of the fifth chip U5.
Compared with the prior art, the invention has the following beneficial effects:
the position of the wave crest can be accurately judged, and a falling edge signal is formed; if the peak position is passed during electrification, a falling edge signal can be generated in the voltage falling process of the positive half-wave of the alternating current, and the influence of small voltage amplitude is avoided; the two characteristics can ensure that the counting and timing signals given by each device are completely synchronous; and at the peak position. In addition, the circuit of the invention is not influenced by power-on fluctuation, the mains supply can be triggered only once in the descending process, and even if voltage fluctuation exists, the voltage fluctuation can be filtered by related circuits.
Drawings
FIG. 1 is a system framework of the present invention;
FIG. 2 is a rectification diagram of a voltage transformation half-wave of the present invention;
FIG. 3 is a voltage generation circuit diagram of the present invention;
FIG. 4 is a falling edge capture circuit diagram of the present invention;
fig. 5 is a waveform shaping circuit diagram of the present invention.
Detailed Description
The present invention is further described with reference to the drawings, but the present invention is not limited thereto in any way, and any modifications or alterations based on the teaching of the present invention shall fall within the scope of the present invention.
In order to make the technical solutions and advantages of the present invention clearer, the present invention is described below with reference to practical examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Examples
According to the invention, 220V mains supply is input from the outside, and after voltage signals are converted, required square wave signals are finally output through the VOFA network, wherein the signals are final synchronous timing signals.
As shown in fig. 1, the synchronous timing signal generating device for internet connection signal lamp disclosed by the invention comprises: the voltage transformation half-wave rectifying circuit, the voltage generating circuit, the falling edge grabbing circuit and the waveform shaping circuit are sequentially connected.
Specifically, the voltage transformation half-wave rectification circuit is shown in fig. 2, wherein 220V alternating current is externally input, 220V-L and 220V-N signals are mains supply alternating current input ends, 220V-L is connected with one end of a first fuse F1, the other end of the F1 is connected with the input end of a first transformer T1, 220V-N is connected with the other pin of the input end of the first transformer T1, two pins of the output end of the T1 are connected with two ends of a first TVS tube TVS1, the anode of a first diode D1 is connected with the input end of the T1, the network is named as V1-L, the cathode of a second diode D2 is connected with the other input end of the T1, and the network is named as V1-N; the negative electrode of the D1 is connected with a VIF signal, the VIF signal is simultaneously connected with one end of the first capacitor and led out of the circuit, and the positive electrode of the second diode and the other end of the first capacitor are connected with the GND. The partial circuit realizes transformation and half-wave rectification of 220V mains supply, and only keeps positive half-wave;
the voltage generating circuit is shown in fig. 3, wherein a V1-L network is connected to one end of a second fuse F2, the other end of the second fuse F2 is connected to the anode of a third diode D3 and the cathode of a fourth diode D4, a V1-N network is connected to the anode of a sixth diode D6 and the cathode of a seventh diode D7, the cathode of the third diode D3 is connected to the cathode of the sixth diode D6 and the anode of a fifth diode D5, the cathode of D5 is connected to a second capacitor C2 and one end of a first resistor R1, the other end of R1 is connected to one end of a third capacitor C3 and the 3-pin of a first chip U1, the network is named VCC1, the anode of the fourth diode D4, the anode of the seventh diode D7, the other end of the second capacitor C2, the other end of the third capacitor C3, the 1-pin of the first chip U1 is connected, the 2-pin of U1 is named one end of a fourth capacitor C4, the network VCC2, the other end of the fourth capacitor C4 is connected to the third capacitor C1, the V1-N network is connected to the GND 1, the V1-N network is connected to the V1, the V1-N network is connected to a power supply, the V1 is connected to the V1, the V-N network is used for generating a low-V-N rectifying voltage, and the ac power supply voltage, and the V-V2 is not lower than the dc voltage, and the dc voltage, the chip.
The falling edge grabbing circuit is shown in fig. 4, a network VIF signal is used as an input signal of the partial circuit, the VIF signal is connected with a cathode of a twelfth diode D10, one end of a fourth resistor R4 and one end of a seventh resistor R7, an anode of D10 is connected with GND, a pin 2 of a second chip U2 is connected with the other end of the fourth resistor R4, a V + end of U2 is connected with a VCC1 network and one end of a sixth capacitor C6, the other end of C6 is connected with GND, a V-end of the second chip U2 is connected with GND, a pin 1 is connected with one end of a second resistor R2 and a cathode of an eighth diode D8, a pin 3 is connected with an anode of the eighth diode D8, an anode of a ninth diode D9 and one end of the sixth resistor R6, the other end of the second diode R2 is connected with one end of a third resistor R3, a cathode of the ninth diode D9 and one end of a fifth resistor R5, and the network is named VHF and serves as an output signal network of the partial circuit; the other end of the third resistor R3 is connected with one end of a fifth capacitor C5, the other end of the C5 is connected with GND, the other end of the seventh resistor R7 is connected with one end of a ninth resistor R9 and a pin 2 of a third chip U3, the other end of the R9 is connected with GND, a pin 1 of the third chip U3 is connected with the other end of a sixth resistor R6, a V + pin is connected with a VCC1 network and one end of the seventh capacitor C7, the other end of the C7 is connected with GND, a V-pin of the third chip U3 is connected with GND, and a pin 3 is connected with one end of the sixth capacitor C6, one end of an eighth resistor C8 and a pin 1 of the first MOS transistor Q1; the other end of the C8, the other end of the R8 and the pin 3 of the Q1 are connected with GND, and the pin 2 of the Q1 is connected with the other end of the fifth resistor R5; the partial circuit realizes peak value detection of a transformed and half-wave rectified mains supply signal VIF through a related circuit of a second chip U2, so that the 3-pin output of the second chip U2 can rise along with the rising of an alternating-current half-wave signal VIF in the rising process, a fifth capacitor C5 is charged and boosted, when the voltage reaches a peak value, the voltage can not fall due to the existence of an eighth diode and a ninth diode at the 1-pin position of the second chip U2, the voltage at the 2-pin position is lower than that at the 1-pin position, and finally the 3 pins output 0V signals which serve as the 1-pin input of a third chip U3, the input of pin 2 of U3 is the voltage of VIF after the voltage division through the seventh resistor R7 and the ninth resistor R9, which is always lower than pin 1 of U3 in the rising process of VIF, but when the voltage of pin 1 of U3 is synchronously reduced to 0V because the voltage of pin 23 is reduced to 0V, the output voltage of pin 3 of the third chip U3 is changed from 0V to VCC1, the voltage signal drives the first MOS tube Q1 to realize the conduction of Q1, the VHF network is approximately connected with GND to realize the voltage relief of the VHF network, so that the VHF signal is changed to 0V immediately after the VIF signal rises to the highest point, and a circuit capable of generating a falling edge signal at the peak position of the input voltage is realized; similarly, at the moment of powering on the signal lamp, the mains supply may be in a positive half-wave voltage drop process, at this time, the VIF is in a continuous drop process, in the process, the pin 3 of the second chip U2 still can generate a high voltage at the moment of powering on, and the subsequent process and the VIF input voltage reach a peak voltage and start a drop process.
As shown in fig. 5, the VHF network signal is an input signal of the waveform shaping circuit, and an output signal of the VHF network signal is VOFA, which is output as a final clock signal to the control circuit of the signal lamp; the VHF network is connected with one end of a twelfth resistor R12, the other end of the R12 is connected with a pin 2 of a fourth chip U4, a pin 1 of the U4 is connected with a pin 3 of the U4 and one end of a tenth resistor R10, a V + pin of the U4 is connected with VCC1 and one end of a ninth capacitor C9, the other end of the C9 is connected with GND, a V-pin of the fourth chip U4 is connected with GND, the other end of the tenth resistor R10 is connected with one end of an eleventh resistor R11, one end of the tenth capacitor C10, the negative electrode of an eleventh diode D11 and a pin 1 of a fifth chip U5; the other end of the R11, the other end of the C10 and the anode of the D11 are connected with GND, a V + pin of a fifth chip U5 is connected with a VCC2 network and one end of an eleventh capacitor C11, the other end of the C11 is connected with GND, a pin 2 of the fifth chip U5 is connected with one end of a thirteenth resistor R13, one end of a fifteenth resistor R15 and one end of a thirteenth capacitor C13, the other end of the R13 is connected with VCC2, the other end of the R15 and the other end of the C13 are connected with GND, a V-pin of the fifth chip U5 is connected with GND, a pin 3 of the U5 is connected with one end of a twelfth capacitor C12, one end of a fourteenth resistor R14, the cathode of a twelfth diode D12 and the anode of the thirteenth diode D13, the other end of the C12, the other end of the R14 and the anode of the D12 are connected with VOFA, and the cathode of the thirteenth diode D13 is connected with VOFA, and the network is used as an input signal of the circuit; the VHF signal is driven and enhanced through a fourth chip U4, the voltage of the signal is reduced through voltage division of a tenth resistor and an eleventh resistor, meanwhile, the voltage of the signal is compared through a fifth chip U5 to output a square wave, the falling edge of the square wave is consistent with the falling edge of the VHF, and the rising edge of the square wave is adjusted through a thirteenth resistor and a fifteenth resistor.
The invention has the following beneficial effects:
the position of the wave crest can be accurately judged, and a falling edge signal is formed; if the peak position is passed during electrification, a falling edge signal can be generated in the voltage falling process of the positive half-wave of the alternating current, and the influence of small voltage amplitude is avoided; the two characteristics can ensure that the counting and timing signals given by each device are completely synchronous; and at the peak position. In addition, the circuit of the invention is not influenced by power-on fluctuation, the mains supply can be triggered only once in the descending process, and even if voltage fluctuation exists, the voltage fluctuation can be filtered by related circuits.
The word "preferred" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "preferred" is not necessarily to be construed as advantageous over other aspects or designs. Rather, use of the word "preferred" is intended to present concepts in a concrete fashion. The term "or" as used in this application is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise or clear from context, "X employs A or B" is intended to include either of the permutations as a matter of course. That is, if X employs A; b is used as X; or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing examples.
Also, although the disclosure has been shown and described with respect to one or an implementation, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present disclosure includes all such modifications and alterations, and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components (e.g., elements, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or other features of the other implementations as may be desired and advantageous for a given or particular application. Furthermore, to the extent that the terms "includes," has, "" contains, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising.
Each functional unit in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or a plurality of or more than one unit are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium. The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Each apparatus or system described above may execute the storage method in the corresponding method embodiment.
In summary, the above-mentioned embodiment is an implementation manner of the present invention, but the implementation manner of the present invention is not limited by the above-mentioned embodiment, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be regarded as equivalent replacements within the protection scope of the present invention.
Claims (4)
1. A synchronized timing signal generating apparatus for a networked signal lamp, comprising: the voltage transformation half-wave rectifying circuit, the voltage generating circuit, the falling edge grabbing circuit and the waveform shaping circuit are sequentially connected;
a VIF signal is used as an input signal of the falling edge capture circuit, the VIF signal is connected with a cathode of a twelfth diode D10, one end of a fourth resistor R4 and one end of a seventh resistor R7, an anode of the twelfth diode D10 is connected with GND, a pin 2 of a second chip U2 is connected with the other end of the fourth resistor R4, a V + end of the second chip U2 is connected with a network VCC1 and one end of a sixth capacitor C6, the other end of the sixth capacitor C6 is connected with GND, a V-end of the second chip U2 is connected with GND, a pin 1 is connected with one end of a second resistor R2 and a cathode of an eighth diode D8, a pin 3 is connected with an anode of the eighth diode D8, an anode of a ninth diode D9 and one end of a sixth resistor R6, and the other end of the second resistor R2 is connected with one end of a third resistor R3, a cathode of the ninth diode D9 and one end of a fifth resistor R5 to form a VHF network, and the output signal network of the falling edge capture circuit;
the other end of the third resistor R3 is connected with one end of a fifth capacitor C5, the other end of the fifth capacitor C5 is connected with GND, the other end of the seventh resistor R7 is connected with one end of a ninth resistor R9 and a pin 2 of a third chip U3, the other end of the ninth resistor R9 is connected with GND, a pin 1 of the third chip U3 is connected with the other end of a sixth resistor R6, a V + pin is connected with a VCC1 network and one end of the seventh capacitor C7, the other end of the C7 is connected with GND, a V-pin of the third chip U3 is connected with GND, and a pin 3 is connected with one end of the sixth capacitor C6, one end of an eighth resistor C8 and a pin 1 of the first MOS transistor Q1; the other end of the C8, the other end of the R8 and the pin 3 of the Q1 are connected with GND, and the pin 2 of the Q1 is connected with the other end of the fifth resistor R5; the falling edge grabbing circuit is used for realizing peak value detection of the transformed and half-wave rectified mains supply signal VIF through the second chip U2 related circuit, so that the VHF signal is changed into 0V immediately after the VIF signal rises to the highest point, and a falling edge signal is generated at the position of the peak value of the input voltage; at the moment of powering on the signal lamp, the pin 3 of the second chip U2 may generate a high voltage at the moment of powering on.
2. The synchronous timing signal generating device for the internet connection signal lamp as claimed in claim 1, wherein the transformation half-wave rectifying circuit realizes transformation and half-wave rectification of 220V commercial power, and only keeps positive half-wave, wherein a commercial power ac input terminal is connected with 220V-L and 220V-N signals, the 220V-L signal is connected with one end of a first fuse F1, the other end of the first fuse F1 is connected with an input terminal of a first transformer T1, the 220V-N signal is connected with the other pin of the input terminal of the first transformer T1, two pins of an output terminal of T1 are connected with two ends of a first TVS tube TVS1, a positive electrode of a first diode D1 is connected with an output terminal of T1 to form a V1-L network, and a negative electrode of a second diode D2 is connected with the other output terminal of T1 to form a V1-N network; the negative electrode of the first diode D1 is connected with a VIF signal, the VIF signal is simultaneously connected with one end of the first capacitor C1 and led out of the circuit, and the positive electrode of the second diode D2 and the other end of the first capacitor C1 are connected with the GND.
3. The synchronous timing signal generating device for the internet connection signal lamp according to claim 2, wherein one end of a second fuse F2 in the voltage generating circuit is connected to the V1-L network, the other end of the second fuse F2 is connected to an anode of a third diode D3 and a cathode of a fourth diode D4, the V1-N network is connected to an anode of a sixth diode D6 and a cathode of a seventh diode D7, a cathode of the third diode D3 is connected to a cathode of the sixth diode D6 and an anode of a fifth diode D5, a cathode of the fifth diode D5 is connected to a cathode of a second capacitor C2 and one end of a first resistor R1, the other end of the first resistor R1 is connected to one end of a third capacitor C3 and a pin 3 of a first chip U1 to form a VCC1 network, an anode of a fourth diode D4, an anode of the seventh diode D7, the other end of the second capacitor C2, the other end of the third capacitor C3, the pin 1 of the first chip U1, and one end of the fourth capacitor C2, and one pin of the fourth capacitor C4 are connected to a GND, and one end of the fourth capacitor C2 and one pin of the first chip U1 are connected to one end of the fourth capacitor C2; the voltage generation circuit realizes the shaping and rectification of the V1-L and V1-N alternating currents and generates VCC1, the voltage can be generated quickly after being electrified, the voltage is not lower than VIF, and VCC2 is generated through the first chip U1.
4. The apparatus according to claim 3, wherein the input signal of the waveform shaping circuit is a VHF network signal, the output signal is VOFA, and the output signal is used as a final clock signal to be output to the control circuit of the signal lamp; one end of a twelfth resistor R12 of the waveform shaping circuit is connected with a VHF network, the other end of the twelfth resistor R12 is connected with a pin 2 of a fourth chip U4, a pin 1 of the fourth chip U4 is connected with a pin 3 of the U4 and one end of a tenth resistor R10, a pin V + of the fourth chip U4 is connected with the VCC1 network and one end of a ninth capacitor C9, the other end of the ninth capacitor C9 is connected with GND, a pin V-of the fourth chip U4 is connected with GND, and the other end of the tenth resistor R10 is connected with one end of an eleventh resistor R11, one end of a tenth capacitor C10, the negative electrode of an eleventh diode D11 and a pin 1 of a fifth chip U5; the other end of the eleventh resistor R11, the other end of the tenth capacitor C10, and the anode of the eleventh diode D11 are connected to GND, a V + pin of a fifth chip U5 is connected to the VCC2 network and one end of the eleventh capacitor C11, the other end of the eleventh capacitor C11 is connected to GND, a pin 2 of the fifth chip U5 is connected to one end of a thirteenth resistor R13, one end of a fifteenth resistor R15, and one end of a thirteenth capacitor C13, the other end of the thirteenth capacitor R13 is connected to the VCC2 network, the other end of the fifteenth resistor R15 and the other end of the C13 are connected to GND, a V-pin of the fifth chip U5 is connected to GND, and a pin 3 of the fifth chip U5 is connected to one end of a twelfth capacitor C12, one end of a fourteenth resistor R14, the cathode of a twelfth diode D12, and the anode of a thirteenth diode D13; the other end of the twelfth capacitor C12, the other end of the fourteenth resistor R14, and the anode of the twelfth diode D12 are connected to GND, the cathode of the thirteenth diode D13 is connected to a VOFA network, and the VOFA network is used as an input signal of the waveform shaping circuit; the VHF signal is enhanced by the fourth chip U4, and is divided by the tenth resistor R10 and the eleventh resistor R11 to reduce the signal voltage, and the voltage comparison of the fifth chip U5 outputs a square wave.
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