JPS63244991A - Automatic phase control circuit - Google Patents

Abstract

PURPOSE:To shorten convergent time until a loop becomes stable state by correcting the number of frequency according to the quantity of a mistaken lock. CONSTITUTION:When the state of the mistaken lock occurs, output 'zero' is generated by a mistaken look detection circuit 18 and when the state of the mistaken lock does not occur, the output '1' is generated. As an APC loop is opened by an AND circuit 30 in the state of the mistaken lock, it is essentially cut. Then only a mistaken locked loop works. When the frequency error of a VCO 17 is held down in a controlled range by the APC loop, the output of the mistaken lock detection circuit 18 becomes '1'. As the result, a closed circuit is formed by the APC loop and the operation by the APC loop is obtained. Thus the phase of the output chrominance components from a band filter 21 is controlled to be the frequency (fs).

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an automatic phase control circuit used in a color signal processing section of a digital signal processing video tape recorder or the like.

(Prior art) Figure 4 shows the conventional automatic phase control (APC) of the color signal processing section.
) is a circuit. In a video tape recorder, the color signal is processed by a low frequency modulation circuit at a center frequency of 40 f, C, /''
H=horizontal frequency) and recorded on the magnetic tape. Therefore, during reproduction, it is necessary to return the low-frequency converted color signal to the original high-frequency color signal. In this case, the reproduced low-pass conversion color signal has a frequency fluctuation Δf corresponding to the jitter due to various factors such as rotational unevenness of the rotation system.

The reproduced low frequency converted color signal is supplied to one input terminal of the main converter 11 via the input terminal 10. The other input terminal of this main converter 11 is connected to the carrier (frequency: /, +407H+Δ
f2) is supplied. f8 is the oscillation frequency of the crystal oscillator 13, and normally the color subcarrier frequency is 3.58 MH
It is z.

The output of the main converter 12 is extracted via the bandpass filter 21, and is expressed as (f8+40fH+Δ/”g)−(40fH+Δf1)
=f, only the component of +(Δf8−Δf2) is extracted,
The signal is input to an automatic phase control (APC) detection circuit 14. A
The PC detection circuit 14 receives the output from the bandpass filter 21,
A phase comparison is made with the output from the crystal oscillator 13, and the resulting error signal is output. The error signal is input to an adder 16 via a low-pass filter 15.

Voltage controlled oscillator (VCO) 17 has a center frequency 407
``H oscillator, and the frequency is controlled by the output value from the adder 16. Now, the output frequency of the VCO 17 is (
40/H+Δf2), the frequency displacement Δ
Loop control is performed on f2 so that the output frequency of the bandpass filter 2 approaches fIl.

In other words, the output error signal of the APC detection circuit 14 is VC
It is constantly sent to the control end of O17 as control information and controls Δf2.

By the way, since the APC detection circuit 14 performs detection processing using the frequency of f3, when the signal frequency from the bandpass filter 21 is shifted by f8, the above-mentioned loop will mislock.

Therefore, in addition to the above-mentioned APC loop, a mislock detection loop is required to determine whether or not this loop is causing a mislock.

The mislock detection circuit 18 compares the frequency of the input with a signal obtained by dividing the output of the VCO 17 to 1/40 by the frequency divider 22, and generates a mislock signal when the error exceeds a certain level.

The mislock signal becomes a select signal for the selector 19, and the selector 19 outputs an offset signal according to the value of the mislock signal. The offset signal is passed through low-pass filter 2.
0 to the adder 16. by this,
The mislock information is fed back to VCO 7 to control the output frequency of VCo 17. When the output signal of the adder 16 is O, the VCO 77 outputs a signal matching the frequency of 40fH, and when the output signal of the adder 16 is a positive value, the VCO 77 outputs a signal matching the frequency higher than 408fH, and outputs a signal matching the frequency of 40fH when the output signal of the adder 16 is a positive value. When the value is 4
Outputs a frequency lower than 0fH.

Now, assume that the mislock detection circuit 18 generates a mislock signal and outputs a positive value as an offset signal. The output of the adder 16 is also assumed to be a positive value. In this case, VC
Since a positive value is added to the control end of OJ 7, the output frequency becomes higher than 4ofH. Then, the output frequency of the multiplier 12 also becomes high, and as a result, the output frequency of the bandpass filter 21 also becomes high. If this frequency change is very large, the error signal of the APC detection circuit 14 will change rapidly. The same applies to negative values. However, if there is such a sudden change in the error signal and the width of the change is large, the entire APC loop is likely to oscillate. To prevent this, the value of the offset signal output at the time of mislock is usually made very small.

(Problems to be Solved by the Invention) As described above, conventionally, in order to avoid sudden changes in the output error signal of the APC detection circuit 14, the value of the offset signal is set to a very small value. by this,
As a loop, it becomes difficult to oscillate, but because the offset amount is small, the convergence time of the mislock loop becomes long (approximately) Therefore, this invention can shorten the convergence time until a stable state is reached. The purpose is to provide an automatic phase control circuit.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a voltage controlled oscillator for obtaining a converted carrier when frequency converting a reproduced low frequency converted color signal to a high frequency color signal of the original frequency. oscillation of the voltage controlled oscillator so that the oscillation frequency of the voltage controlled oscillator and the frequency of the horizontal synchronization signal have a predetermined relationship; In the automatic phase control circuit, the automatic phase control circuit is equipped with a mislock-loose circuit that obtains frequency error information between the output and the horizontal synchronization signal and returns this as mislock information to the control terminal of the voltage controlled oscillator. A switching means is provided for detecting and, when operating, stopping control information in the APC loose from being applied to the control end of the voltage controlled oscillator.

(Function) With the above means, in the present invention, when the mislock loop detects a mislock, the APC loop will not oscillate even if the offset value given to the voltage controlled oscillator as frequency control information is increased. It is possible to speed up the convergence of miss-lock-loose.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and the same functional parts as the conventional circuits and circuits are given the same reference numerals as in the conventional circuit.

The difference from the conventional method is that the present invention is provided with means for disconnecting the APC loop from the mislock/loose when a mislock occurs.

That is, in the present invention, for example, an AND circuit 3o is provided between the low-pass filter 5 and the adder 5.

Then, the output of the low-pass filter 15 is input to one input terminal of the AND circuit 30, the output of the mislock detection circuit 18 is input to the other input terminal, and the output of the AND circuit 3θ is input to the adder 16.
is being entered. Therefore, instead of the previous explanation of the same parts as in the conventional art, the operation of the different parts will be explained.

Here, it is assumed that when there is a mislock state, "0" is generated from the mislock detection circuit I8, and when no mislock occurs, °1# is generated.

Assuming that the mislock state is present, the AND circuit 30 puts the APC rule in the open state, so that the APCA-1 is substantially separated and only the mislock loop operates. Therefore, even if the offset signal value of the Misron loop is increased, this will not affect the APC looseness and will not overwhelm the APC rule oscillation or the oscillation of the entire loop. When the frequency error of the voltage controlled oscillator (VCO) 17 within the control range due to APC looseness is suppressed by the automatic frequency control of the mislock loop, the output of the mislock detection circuit 18, the tb mislock signal, becomes '1#'. becomes.

Yo-C1 Now, form an APC rule cycle and AP
C operation is obtained, and the output color signal of the bandpass filter 21 is phase-controlled to have the frequency fB.

According to the above circuit, the frequency displacement of the mislock/loose does not affect the APC rule/phase displacement, so each time constant (in the case of a mislock/loose, the detection point of the mislock detection circuit, the offset amount, and the APC loose) In this case, it is possible to set the gain adjustment of this loop), and it is possible to create a circuit that can reliably converge at extremely high speed.

FIG. 2 shows the changes in the control signal for the output of the adder 16, that is, the VCOI 7, and the mislock loop! and APC loose operation section. In this circuit, since the amount of offset can be arbitrarily selected, loose convergence can be made faster. In particular, since the above circuit is a digital control circuit, this effect can be effectively utilized.

In the above embodiment, the offset amount is selected to be constant, but the present invention is not limited to this.

For example, there are cases where data is superimposed on the 20th H (H: water period) from the vertical synchronization signal and it is desired to establish a synchronized state in such a short period of time.

Therefore, Fig. 3 shows that when a mislock occurs, an offset amount commensurate with the magnitude of the mislock amount is applied to the VC.
This is an embodiment in which the control signal is given to OJ 7 as a control signal so that it can meet the synchronization establishment request time of the system. The same parts as in FIG.
is fed to one input of The output of the AND circuit 32 is then input to one terminal of the multiplier 33. A fixed value is given to the other terminal of this multiplier 33, and the output of this multiplier 33 is input to the adder 16 via the low-pass filter 20.

In the above circuit, the mislock detection circuit 18 detects "6" as the mislock amount when the frequency difference is approximately IH.
Assume that a value of 4# is output.

It is also assumed that the VCo 17 performs frequency correction for IH when an offset control signal with a value of 172'' is applied.Furthermore, the loop control circuit 3 determines the value from the detection circuit 18. , ifH deviation or more, that is, if a state of average=8 or more continues for a period of 4B or more, it is determined as a mislock state and "1#" is output.

Under the above settings, now the mislock i "64"
If the state continues for 4 hours or more, the loop control circuit 31
outputs 1". Therefore, the AND circuit 32 outputs @6
A digital value of 4# can be introduced into the multiplier 33. On the other hand, "1" is inverted and input to one side of the AND circuit 30 as a logic "O" through the APC rule and inverter 35, thus forming an open loop.

In the multiplier 33, the fixed value (=1.125) and ``64''
The offset signal 64×1.125=72 can be obtained. This offset signal is retained in a low pass filter 20 and applied via an adder 16 to the control terminal of the VCOl 7. Therefore, VCo
For frequency No. 17, correction for IH can be obtained.

Note that the method to output the amount of mislock is to use memory (
Various values may be stored in a ROM (ROM), and the mislock amount may be output from the ROM using the detection output as an address.

According to the above embodiment, since frequency correction is obtained according to the amount of mislock, the convergence time is extremely short, and the system requirements can be fully met.

[Effects of the Invention] As explained above, the present invention provides an automatic phase control circuit that can shorten the convergence time until the loop reaches a stable state without causing any trouble to others. can.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of the circuit shown in Fig. 1, Fig. 3 is a circuit diagram showing another embodiment of the invention, and Fig. 4 is a conventional circuit diagram. FIG. 2 is a diagram showing an automatic phase control circuit of FIG. 11.12... Multiplier, 13... Crystal oscillator, No.4
...APC detection circuit, 15...Low pass filter, 16
...Adder, 17...Voltage controlled oscillator (VCO),
1B...Mislock detection circuit, 19...Selector,
20...Low pass filter, 21...Band filter, 2
2... Frequency divider, 30.32... AND circuit, 33.
... Multiplier, 35... Innoguchita. Applicant's representative Patent attorney Takehiko Suzue "Figure 2

Claims (2)

[Claims] (1) When frequency converting the reproduced low frequency color signal into the original high frequency color signal, the voltage controlled oscillator for obtaining the conversion carrier is configured so that the high frequency color signal is phase-locked to a predetermined frequency. obtains frequency error information indicating whether or not the oscillation output of the voltage controlled oscillator and the reproduced horizontal synchronization signal have a predetermined frequency relationship, and uses this as mislock information to control the voltage control. In an automatic phase control circuit comprising a mislock loop circuit that feeds back to a frequency control terminal of an oscillator, when the mislock loop circuit detects mislock and is operating, phase control information of the automatic phase control loop circuit is An automatic phase control circuit comprising switching means for stopping feedback of the voltage controlled oscillator to the voltage controlled oscillator. (2) The mislock loop circuit includes means for varying the value of the mislock information in accordance with the amount by which the frequency relationship between the oscillation output of the voltage controlled oscillator and the reproduced horizontal synchronizing signal deviates from a predetermined relationship. An automatic phase control circuit according to claim 1, further comprising: an automatic phase control circuit according to claim 1.