JPS63244763A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a high-precision programming voltage by a method wherein a constant-voltage diode in a substrate is so structured that a depletion layer therein may extend, centripetally or diffusion-wise, in the lateral direction in the substrate and that a p-n junction portion prone to break down is contained in the substrate. CONSTITUTION:After the formation of an element-isolating region in a p<->-type Si substrate 1, a channel stopper layer 5 is formed, a prescribed distance back from the end of the element-isolating region. A thermal oxide film 6 is formed in the element-isolating region, a masking material 7 is formed provided with a ring-geometry opening, and the As ions are implanted for the formation of an n<+>-type layer 2. Next, a masking material 8 is formed provided with an opening at thc middle of the element, and then boron ions are implanted for the formation of a thick p-type layer 3. A CVD SiO2 film 9 is deposited, which is provided with contact holes for the construction of Al wirings 10, 11. The Al wiring 11 is formed into a ring, symmetrical to the pattern of the n<+>-type layer 2.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a non-volatile semiconductor memory device that is electrically rewritable, and particularly relates to a non-volatile semiconductor memory device that enables electrical rewriting, and in particular, programming that is higher than the power supply voltage for writing or erasing. This invention relates to improvements in the part of the constant voltage diode that obtains the voltage.

(Prior art) Non-volatile semiconductor memory device (E
2 FROM> memory cell has a MOS transistor structure with a floating gate and a control gate, and is devised to electrically perform not only charge injection into the floating gate but also charge discharge from the floating gate. There is. For example, the memory cell has a structure in which an extremely thin insulating film through which a tunnel current can flow is provided between the substrate in the rewrite area and the floating gate. Information erasure in an n-channel memory cell with such a structure is performed by applying a high positive voltage to the control gate, grounding the drain, and injecting electrons from the substrate into the floating gate through an extremely thin insulating film. be exposed. Information is written by grounding the control gate, applying a high positive voltage to the drain, and emitting electrons from the floating gate to the substrate through the extremely thin insulating film. The high voltage (programming voltage) used for electrical writing and erasing is generated using a booster circuit and a constant voltage circuit.

In the information rewriting operation in such an E"FROM, a high electric field is applied to the insulating film between the floating gate and the 1llJIIl gate, so the programming voltage mentioned above must be highly accurate in order to ensure the reliability of the memory cell. For example, if the programming voltage is higher than the set value, the gate insulating film will be easily destroyed as rewriting is repeated.Specifically, the thickness of the gate insulating film of the memory cell is about 400 mm.
Assuming that the programming voltage is 20V, the lifetime until the insulating film breaks down is reduced by half if the programming voltage increases by only 1V. Conversely, as the programming voltage decreases, the difference in threshold voltage between writing and erasing a memory cell decreases, reducing the memory cell's “0” 41
``This results in a narrower margin for judgment.

By the way, in order to make a high voltage of about 20V constant,
A diode that uses avalanche is required. Such a constant voltage diode normally exhibits a change over time in which the breakdown voltage increases due to charge accumulation at the interface between the substrate and the surface passivation film. This change over time becomes a major obstacle in obtaining the above-mentioned highly accurate programming voltage.

Conventionally, as a constant voltage diode structure with little change over time, the structure shown in the seventh factor has been proposed. p-type SK
An n+ type layer 52 is formed on the surface of the first plate 51, and this n"
A p-type layer 53 is formed in the center of the type layer 52 at a lower concentration and deeper.

54 is an element isolation insulating film, and 55 is a channel stopper layer. In this structure, the pn junction does not terminate at the substrate surface. In addition, the pn junction that obtains a constant voltage is located inside the substrate.
The tip of the type layer 52 is formed at a portion crossing the p-type layer 53. In this diode structure, breakdown occurs inside the substrate before breakdown occurs on the surface, so that the increase in breakdown voltage over time due to charge accumulation at the interface of the passivation film, as described above, is reduced.

However, the voltage regulator diode shown in FIG. 7 has the following problems. First, the breakdown voltage is determined by the pn voltage formed at the tip of the n+ type layer 52 when a reverse bias is applied.
The p-type layer 53 must be formed sufficiently deep inside the substrate because it depends on how the depletion layer extends into the low concentration p-type layer 53 that protrudes downward from the junction. For example, p-type 1f
The formation of 53 requires ion implantation at a high acceleration voltage. However, in this structure in which the p-type layer 53 is formed deeply to form a pn junction inside the substrate, the breakdown voltage is determined by the impurity concentration distribution in the depth direction, so it is difficult to set the breakdown voltage with high precision. difficult. Therefore, using this constant voltage diode, E2 FR
When generating programming voltage for OM, there are large variations depending on manufacturing conditions, and as mentioned above, E2PROM1
．． : It is difficult to obtain the required high precision programming voltage. Further, in order to obtain a breakdown voltage of about 20 V, for example, the acceleration voltage for ion implantation of the p-type layer 53 must be set to 200 keV or more, which makes the ion implantation device expensive.

(Problems to be Solved by the Invention) As described above, in E" PROM, extremely high precision high voltage is required as programming voltage for writing and erasing, but conventional constant voltage The problem was that diodes could not meet this requirement.

The present invention has been made in view of the above points, and an object of the present invention is to provide an E'' PROM equipped with a constant voltage diode that makes it possible to obtain extremely high precision programming voltage.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a constant voltage diode provided at the output end of a booster circuit for obtaining a programming voltage for an E2PROM, one of which is separated from the elements of a first conductivity type substrate. In the center of the area,
It is composed of a low impurity concentration layer of a first conductivity type and a high impurity concentration layer of a second conductivity type, the other being formed so as to partially overlap the peripheral portion thereof, and the low impurity concentration layer has an impurity concentration distribution. The peak is set at a position deeper than the substrate surface.

(Function) With such a constant voltage diode configuration, the ρn junction surface consisting of the first conductivity type low impurity concentration layer and the second conductivity type high impurity concentration layer is approximately perpendicular to the substrate. In other words, when a reverse bias is applied, the depletion layer extends laterally within the first conductivity type low impurity concentration layer. In other words, it is the impurity concentration distribution in the horizontal direction of the substrate that determines the reverse breakdown voltage characteristics of the diode, and it is possible to obtain a breakdown voltage with high accuracy compared to the conventional method based on the impurity concentration in the vertical direction of the substrate. There is also little variation in characteristics depending on conditions.

Moreover, since the depletion layer extends in the lateral direction of the substrate, the low impurity of the first conductivity type III! There is no need to form the layer so deeply, and there is no need to increase the ion implantation acceleration voltage so high when forming this constant impurity concentration layer. Moreover, since the 11th conduction type low impurity concentration layer has a peak of the wood purity distribution inside the substrate, the part that determines the breakdown voltage of the pn junction is inside the substrate a predetermined distance below the substrate surface position, and the breakdown There is little change over time in the form of an increase in down voltage. As described above, the programming voltage generated by the voltage regulator diode of the present invention has extremely high precision, and the Et FROM
This will improve reliability and performance.

(Example) The present invention will be explained in detail below.

FIG. 4 shows the overall configuration of an E'' PROM according to an embodiment of the present invention.A memory cell MC has a floating gate and a
It is composed of a memory transistor QM having an l gate and a switching transistor Qs connected in series with the memory transistor QM, which are arranged in a matrix. 21 is a row decoder, 22 is a column decoder, 23 is a memory cell source bias circuit, 24 is a sense amplifier, and 27 is a data decoder. 25 is a booster circuit, the output of which is set to a constant amplitude by a constant voltage diode 26 and is supplied to various parts as a programming voltage Vp.

The switching transistor Qs and the byte selection transistor Q along the O selected by the row decoder 21
When R is driven, the column decoder 22 selectively performs writing, vt extraction, etc. for one selected byte.

A brief description of the rewrite and read operations focusing on the memory cell MC surrounded by a broken line in FIG. 4 is as follows. During writing, the output of the row decoder 211 is the programming voltage Vp=20V.

The output of the column decoder 2221 is the same <Vp, the output of the column decoder 2211 is Vss, the selected output of the data line decoder 27 is also Vp, and the output of the cell bias circuit 23 is 70-ting. As a result, in the memory transistor QM of the selected memory cell MC, the drain becomes 20v1 and the control gate becomes 0■, and the electrons stored in the floating gate are released to the substrate. During erasing, the output of the column decoder 2211 becomes Vp1, the output of the column decoder 2221 and the row decoder 211, the output of the VP1 data line decoder 27 and the cell bias circuit become Vss. Electrons are injected into the floating gate of the selected memory transistor Qy.

Programming voltage Vp is not used for information reading. That is, the output of the row decoder 211 and the column
The output of the decoder 2221 is VCCN, and all other outputs are Vs.
By setting s, the memory transistor QM is turned on,
Off state is read.

FIG. 5 shows a specific structural example of the memory cell MC. The memory transistor QM has a source and a p-type 81 substrate 31,
An n4-type 1136°39 which becomes a drain is formed, a floating gate 33 is formed on the channel region via a gate insulating layer 32, and a gate insulating film 34 is further formed on this.
A gate 35 is formed through the gate. An n-type layer 4o connected to the source is previously formed on the surface of the substrate in the rewrite area, and an ultra-thin insulator 1141 for transferring charge between the substrate and the floating gate 33 is formed on this. The switching transistor QB uses the 09 type layer 36 which is common to the source of the memory transistor Qv as a source, and the n+ type layer 38 which becomes the drain is formed, and a two-layer structure is formed on the channel region between these with a gate insulating film interposed therebetween. A gate electrode 37 is formed and configured. The two-layer gate electrodes 37 are commonly connected through contact holes at other locations.

FIG. 1(a) and (b) are plan views showing the structure of the constant voltage diode 26 provided at the output end of the booster port!!25 for obtaining the programming voltage Vp, and its A-A-
FIG. A deep p-type Jii3 is formed in the center of the element-isolated region of the p-type 81M board 1, and this p-type layer 3
An n+ type 12, which becomes a cathode region, is formed surrounding the periphery so as to partially overlap the periphery of the . 4 is an element isolation insulating film, 5 is a channel stopper layer, and 6 is a thermal oxide film. As shown, the diode region is spaced a distance a1 from the end of the isolation region, and the tip of the channel stopper layer 5 is set back a distance l11a2 from the end of the isolation region.

The specific manufacturing process of this voltage regulator diode is shown in Figure 2 (
This will be explained using a) to (d). First, as shown in (a), an element isolation region of a p-type Si substrate 1 is formed. As described above, the channel stopper layer 5 is formed at a predetermined distance Ill from the end of the element isolation region. Thereafter, a thermal oxide film 6 of, for example, 300 layers is formed in the element formation region. Thereafter, as shown in FIG. 3B, a first mask material 7 having a ring-shaped opening is formed, and As is ion-implanted to form an n1 type layer 2. At this time, the ion implantation conditions are, for example, an acceleration voltage of 40 keV and a dose of 4.5 to 6.0×10"101".
shall be. Next, as shown in (C), a mask material 8 having an opening at the center of the element is formed again, and boron ions are implanted to form a deep p-type layer 3. A peripheral portion of the p-type layer 13 overlaps with a portion of the n+-type layer 2 . The ion implantation conditions for this p-type layer 3 are, for example, an acceleration voltage of 150 to 180 keV and a dose of 2.5 to 3.0×10 12 /α2. After these ion implantations, heat treatment is performed at 900 to 950° C. for 20 to 30 minutes in an 02 atmosphere with the oxide film 6 formed. And finally, as shown in (d), CVD5 I 0
Deposit 219, open a contact hole, and connect to 2 wiring 10.
11 is formed. The β pattern is formed in a ring shape similar to the pattern of the n1 type layer 2.

FIG. 3 shows the impurity 11 degree distribution in the depth direction of this constant voltage diode at the BB- position where the n-type layer 2 and the p-type layer 3 overlap each other in FIG. 1(b). The peak position of the impurity concentration of the p-type layer 3 is located deeper than the tip of the 04'' type layer 2.

In the constant voltage diode according to this embodiment, during reverse bias, the depletion layer extends laterally from the ring-shaped nI type layer 2 into the p type layer 3, and breakdown occurs at the pn junction inside the substrate. Therefore, the programming voltage Vp obtained by this constant voltage diode has a stable and highly accurate value with less dependence on the ion implantation accelerating voltage as well as less variation in IilI. This improves the reliability and performance of the E2 PROM. Further, since the constant voltage diode utilizes the spread of the depletion layer in the lateral direction, it is not necessary to form the p-type layer 3 deeply as in the conventional case, and there is no need to use a high acceleration voltage as in the conventional case.

In the constant voltage diode of the above embodiment, the p-type layer 3 having the same conductivity type as MMi is placed in the center of the element region, and the n+
Although the type 1iI2 is provided around this p-type WA3, their arrangement can be reversed. The cross-sectional structure in that case is shown in FIG. 6, corresponding to FIG. 1(b). The operational difference between this structure and the previous embodiment is that the depletion layer during reverse bias either extends toward the center of the device (centripetal) or extends outward from the center of the device (diffused). There is a difference between These are essentially the same in that the depletion layer extends in the horizontal direction of the substrate, and if the vertical impurity concentration distribution is set in the same way as in the previous example, the same effects as in the previous example can be obtained. It will be done.

The present invention is not limited to the above embodiments, and can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, a constant voltage diode for obtaining a high programming voltage has a structure in which the depletion layer extends centripetally or diffusely in the lateral direction of the substrate, and the breakdown By configuring the pn junction part that generates the E2 PRO
It is possible to improve the reliability and performance of M.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) show E2 PRO according to an embodiment of the present invention.
A diagram showing the structure of a constant voltage diode in M, Fig. 2 (
a) to (d) are diagrams showing the manufacturing process, Figure 3 is a diagram showing the impurity concentration distribution, and Figure 4 is the E2 FR.
Equivalent circuit diagrams showing the overall configuration of OM, Figures 5(a) to (C
) is a diagram showing the structure of the memory cell, FIG. 6 is a diagram showing the structure of a constant voltage diode of E2 FROM of another embodiment, and FIG. 7 is a diagram showing the structure of a conventional constant voltage diode. 1... p- type S1 substrate, 2... n+ type layer, 3...
p-type layer. 4... Element isolation insulating film, 5... Channel
Stopper layer, 6... Thermal oxide film, 7, 8... Mask material, MC... Memory cell, QM... Memory transistor, Qw... Switching transistor, QR, Qc
... selection transistor, 21 ... row decoder,
22... Column decoder, 23... Cell bias circuit, 24... Sense amplifier, 25... Boost circuit,
26... Constant voltage diode, 27... Data line decoder. Applicant's agent Patent attorney Takehiko Suzue No. 10 (a) s) + each 22++++ 2nd mouth (d) @2 Figure (a) No. 60

Claims (3)

[Claims] (1) A memory array in which electrically rewritable nonvolatile memory cells are arranged in a matrix on a first conductivity type semiconductor substrate, a control circuit for selectively reading, writing and erasing information in the memory cells, and selection. It integrates a booster circuit that generates a voltage higher than the power supply voltage for writing or erasing information into memory cells, and a constant voltage diode that sets the output voltage from this booster circuit to a constant value to obtain a programming voltage. In the formed nonvolatile semiconductor memory device, the constant voltage diodes are arranged in the device-isolated region of the first conductivity type semiconductor substrate, one of which partially overlaps the center of the region, and the other partially overlaps the periphery of the region. It is composed of a first conductivity type low impurity concentration layer and a second conductivity type high impurity concentration layer, and the peak of the impurity distribution of the low impurity concentration layer is set at a position deeper than the substrate surface. A nonvolatile semiconductor memory device characterized by: (2) The nonvolatile semiconductor memory device according to claim 1, wherein the impurity layer constituting the constant voltage diode is formed at a predetermined distance from an end of the element isolation region. (3) The channel stopper layer formed on the substrate surface of the element isolation region around the low voltage diode has a tip thereof set back from an edge of the element isolation region. semiconductor memory device.