JPS6324468A - Filter circuit - Google Patents

Abstract

PURPOSE:To delete the number of parts and to simplify a circuit constitution by performing all multiplication transformations through the same factor by one operation cell. CONSTITUTION:Input latches 1, 13 for holding picture data during one clock are respectively provided, output latches 2, 3, 7 are a first operation cells and these operation cells 2, 3, 7 are provided with multiplication look up table and an adder and a latch respectively. Further second cells 4, 6, 8, 10, 11, 12 provided with the adder and the latch are provided with line buffers 5, 9 applying the delay of (y-3) picture elements. The respective factors of the operation cells in a filter processing are generally symmetrical vertically and horizontally and for instance, when a filter processing size is a 3X3 size, it is understood that the three factors (a), (b), (c) among the nine factors are completely used. Thereby, in a window, in first and last lines, the operation through the factors (a), (b) may be performed and the operation through the factors (b), (c) may be performed in an intermediate line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a filter circuit that performs local area filter processing on a digital image.

[Conventional technology]

In image processing apparatuses, filter processing is effective and essential for averaging, noise removal, edge detection, and the like.

Filter processing generally involves setting a window of size nxn on an image of xxy pixels, as shown in Figure 9, and performing a sum-of-products operation based on predetermined coefficients between the pixel of interest and its surrounding pixels. be.

There are two types of calculation methods: software and hardware, but the former method requires a huge amount of calculation time when the image size is large.

In addition, as for the latter method, as described in Japanese Patent Application Laid-Open No. 60-72083, a number of calculation cells corresponding to the size of the local region, for example, nine calculation cells of 3×3 size, are provided.
There is a method that performs a sum-of-products operation. This is a method in which a multiplier that multiplies one pixel by one calculation coefficient (parameter) and an adder that adds the output of the multiplier and the output of the previous stage calculation cell are provided in one calculation cell. be.

[Problem that the invention seeks to solve]

However, as described above, in the system having arithmetic cells corresponding to the size, as the size increases, the number of necessary arithmetic cells increases in a geometric progression, resulting in an enormous circuit configuration. In addition, the multiplication part is stored in a lookup table (hereinafter LOT
Although it is possible to consider a method of replacing the table with a method (abbreviated as ), this method also requires a large number of tables with the same contents, resulting in a complicated configuration.

The purpose of the present invention is to improve the drawbacks of the upper part and to provide a filter circuit that has a simple configuration and is quick to perform filter processing without having to provide arithmetic cells corresponding to all nXn size local areas. This is what we provide.

[Means for solving problems]

In order to achieve the above object, the present invention provides a filter circuit that sets a window of a predetermined size for input image data and performs a predetermined operation, and includes a first calculation means that multiplies, adds, and holds the image data. are provided corresponding to mutually different coefficients of filter processing, and a second calculation means for adding and holding data obtained by the first calculation means is provided corresponding to coefficients that overlap with the above coefficients. It is characterized by

[Function] The present invention provides that each coefficient of a calculation cell in filter processing is
The aim is to simplify the circuit by focusing on the fact that it is generally symmetrical vertically and horizontally.

For example, if the filter processing size is 3×3 size,
As shown in FIG. 10, three coefficients a out of nine coefficients,
It turns out that b and c are sufficient. That is, in the window shown in FIG. 10, the coefficient a is
, b, and in the middle line the coefficients S, c
All you have to do is perform the calculation.

〔Example〕

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, features of the present invention will be specifically described based on examples with reference to the drawings.

FIG. 1 shows a simple example in which 3×3 size filter processing is performed. The coefficients in the filter are shown in FIG. 10 and are vertically and horizontally symmetrical. In this case, the only necessary coefficients are a, b, and c.

In Figure 1, 1.13 is an input latch that holds image data for one clock, an output latch, and 2.3.7
is the first calculation cell. These first calculation cells 2, 3 .
7 each include a multiplication look amplifier table, an adder, and a latch. 4.6°8, 10.11.12 is the second arithmetic cell equipped with an adder and a launch, 5.9 is (y −
3) Line buffer that provides pixel delay (9th
(see figure).

FIG. 2 shows a specific example of the first calculation cell 2.3.7. 14
is a LIT from FROM that multiplies and transforms the input image and outputs it.
It is. The contents of the LIT 14 differ depending on the arithmetic cell, and the first arithmetic cell 2 has data written such that the output is ia for the input l.

Also, the first arithmetic cells 3 and 7 each have an output of ib.

It is configured to be an IC. , 15 is a full adder which adds the output of the LIT 14 and the output of the previous stage cell. 16
is a D-type flip-flop (hereinafter abbreviated as D-F/F) that holds the addition output for one cycle of the pixel synchronization clock φD.

FIG. 3 shows the second calculation cell 4. 6. 8.10.11.1
2, 17 is LIIT 1 of the first calculation cell.
Full adder that adds the output of 4 and the output of the previous cell, 18
is a DF/F which is not shown in FIG. 2 and has the same function as the DF/F 16.

FIG. 4 shows a specific example of the line buffer 5.9.

This is called a double buffer method, and reading and writing can be performed simultaneously. 20°21 is S
RAM, 22 to 25 are pass buffers that switch the data bus route, and 26 is an SRAM D-20 that holds the read value from 21 for one cycle of the pixel synchronization clock φD.
It is F/F. If the SRAM 20 is currently writing, the SRAM 21 is currently reading. In this state, the SR
The same buffer address is supplied to AM 20.21, and write clocks φWR, 5RA7120 are supplied.
An output enable clock φOE is supplied to the SRAM 21. Further, the buffer switching signal is applied at a high level, and the path buffers 22 and 25 are enabled. Therefore, the input image data is written to the SRAM 20 via the path buffer 22, and at the same time
The read data from 1 is sent to D via the path buffer 25.
-Latched by F/F 26.

When the next line data is input, the line buffer control device sends the output enable clock 7 to the SRAM 20, φOE, SRA? + Write clock φ to 21
Eyes are supplied. Also, the bumper switching signal is given at low level, and the SRAM 20 is used for reading and
RAM 21 is switched to writing.

Thereafter, the above operation is repeated for each line.

Now, taking as an example the case where filter processing is performed on the pixel data shown in FIG. 5, explanation will be given with reference to timing charts of FIGS. 6 to 8.

In addition, in the figure, 14 = illa + i + zb + i + 3
aIz* = iz+b + 1zzc + 1zzb
Ist =iz+a+ 1izb +it*a■X y
= :x y−+ a +! z y b +l
x y++aIX41 y= 11141 y-+ b
+ L++ y c +tx or l y*1brx+t
y= Ix+ffi 7-1 a +fx*z y
b +ix+z y*1a.

First, in the input of the first line, pixel data Ll+ilt, . . . are output from the input collar edge 1 to point (A) in synchronization with the pixel clock φD, as shown in FIG. The point of the first calculation cell 2 (from the beginning, pixel data ll +
+11□, ... multiplied by a, 111a+Il! a+
... is output. Also, the input from the previous cell (O in this case) and the value at point (A) are added, and the value at point (A) is
Pixel data Ll+lI! .

Pixel data 11 is added to the point with a delay of 1 crotre from ...
1a+jl! a+... is output. Also, at point (1) of the first calculation cell 3, pixel data tlla+ of point (a)
At the same timing as lI□a, . . . , the values i1+b, Lzb+ . . . multiplied by b are output. Also the first
The point (o) of calculation cell 3 has the value of the previous cell, that is, the point (two) of first calculation cell 2! lIa+ll□a.

...and the value of point (1) obtained by multiplying the image data by b + 1zb
, 112b, ” is added to the value iza+Lzb+
f+za++1*b+... is the pixel data l of point (A)
lI+l+! It is output with a delay of 2 clocks from +....

The point (force) of the second calculation cell 4 has the previous cell, that is,
The value i++a+iBb+1Ba(□[+z)+i+ga+1 is the sum of the value iza+Ltb, . . . of the point (o) of the first calculation cell 3, and the value 113a, t+ma+, .. of the point (a).
lib+i+4abl+z)+... is output with a delay of 3 clocks from the pixel data Ll+11□3... of point (A). In other words, at this point Ll+11! +ll, a to l,
The value obtained by multiplying and adding b and a is output, and at the next clock, jl! a, b for +j+3+jlt.

The value obtained by multiplying and adding a is output.

Thereafter, the calculations are repeated in sequence in synchronization with the clock. This value is simultaneously written to the line buffer 5.

Next, the input on the second line will be explained with reference to the timing chart of FIG.

Pixel data j! is transferred to point (A) in synchronization with pixel clock φD.
++! ! ! +423+... is output. The value from the point (1) of the first arithmetic cell 3 and the value from the point (K) of the line buffer 5 are input to the second arithmetic cell 6.

In other words, the pixel data j of point (a)! l+121. +13.
” multiplied by b!21b+j2□l)+tff
i3b+... and the calculation value 112+113+... of the previous line read out from the line buffer 5 are input, and the output of the second calculation cell 6 (ri) is the pixel data of point (a)! ! ++! After a delay of 1 O from Z□+12ff+..., Lz+iz+b, r+s+jzzb+H.

At the next clock, the value of point (ri) and 12□+t23+・
The value obtained by multiplying ・ by C The value obtained by adding 122c+j2ffc+... 1+z+iz+b+1ziC, r+z+1zz
b+1ztc+” is the output of the first operation self (
(k) is output. Then, at the next clock, Lz+iz+b+1zzC is applied to the point (C) which is the output of the second arithmetic cell 8.
+Lxb('I+z+Izz), Itz+1zzb+1
zsC+1inb(=IB+Izz)+'' is output.

When entering the third line, a similar calculation is performed, as shown in FIG.
=I lz+Izz+l5z) + It ff+hs
+ 13za+13xb+is4aM+ 3+Ixs+
h*),... are output.

The above calculation calculates the center value that has been subjected to filter processing in a size of 3×3. Thereafter, by sequentially performing calculations in a pipeline manner, image data obtained by performing 3×3 size filter processing on input image data can be obtained.

Although the size is 3×3, the same circuit configuration can be made with a size of 5×5 or larger. Even if the size increases, the processing speed remains the same, and filter processing is performed in one clock.

〔Effect of the invention〕

As mentioned above, in the present invention, we focus on the fact that in general filter processing, the coefficients are vertically and horizontally symmetrical,
All multiplication conversions using the same coefficients are performed in one arithmetic cell. As a result, it is no longer necessary to provide multipliers or multiplication means such as LTLT in all the calculation cells corresponding to the number of filter sizes, and the number of parts can be reduced, and the circuit configuration can also be simplified.

In addition, it is possible to perform long-distance calculations in a pipelined manner, and the processing speed will not decrease even if the size increases.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the filter circuit according to the present invention, FIG. 2 is a specific example of the first arithmetic cell, FIG. 3 is a specific example of the second arithmetic cell, FIG. 4 is a specific example of the line buffer, and FIG. Figure 5 is an explanatory diagram of the original image data to be subjected to filter processing, and Figures 6 to 8
The figure is a timing chart showing the operation of the embodiment of FIG.
Figure 9 is an explanatory diagram showing the relationship between images and windows;
FIG. 0 is an explanatory diagram showing general coefficient contents of a 3×3 size filter. 1: Input lunch 2.3, 7: 1st calculation cell 4.6.8, 10, 11, 12: 2nd calculation cell 5.9
Niline buffer 13: Output launch 14: LIIT 15.17: Full adder 16.18, 26: D-type flipflop 20.2
1: SR total 22-25: Bus buffer patent applicant Fuji Xerox Co., Ltd. agent
Handmade profit (2 idiots) Fig. 1 Fig. 2 Fig. 2 Low −−−−−−−−−−−”1 ■ Fig. 3 Fig. 6 1st line input (force)
■1t Eng+s No. 7 Figure 2nd line input No. 8 Figure 3rd line input (7) 131! sz Its
ix+ fsa (i)
is+o l5za fnta
Itso〈Etet1D〈'9th 2γ-10th (l n=3

Claims (1)

[Claims] 1. In a filter circuit that sets a window of a predetermined size for image data and performs a predetermined calculation, the first calculation means that multiplies, adds, and holds the image data is used for filter processing. It is characterized in that it is provided corresponding to coefficients that are different from each other, and that a second calculation means for adding and holding data obtained by the first calculation means is provided corresponding to coefficients that overlap with the above-mentioned coefficients. filter circuit. 2. The first calculation means has two input sections, and has a multiplication means for multiplying the image data input to one input section by a coefficient of the window, and a multiplication output from the multiplication means and an input from the other input section. 2. The filter circuit according to claim 1, further comprising an adding means for calculating the sum with image data inputted to the filter circuit, and a holding means for holding the output of the adding means. 3. The second calculation means has two input sections, and calculates the sum of the multiplication value from the first calculation means input into one input section and the image data input into the other input section. Claim 1 is characterized in that it is comprised of an adding means that takes the value of
2. The filter circuit according to item 1 or 2.