JP2011030005A - Image processing device and image forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing device having a small circuit size of a filter circuit, and also to provide an image forming device. <P>SOLUTION: A filter circuit 1 generates filter-processed pixel data on the basis of the calculation product of the predetermined number of attention pixel data and the identical number of filter coefficients by shifting the predetermined number of attention pixel data of the pixel data arranged in one line by one pixel. The filter circuit 1 is equipped with: a multiplier 21 for multiplying the pixel data by one of the two filter coefficients having an identical value out of a plurality of filter coefficients having the value symmetrical centering around a center of a filter coefficient array; and delay circuits 24, 25 for delaying the value of multiplication result by the multiplier until the use of the calculation product of the other out of these two filter coefficients and the pixel data. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus and an image forming apparatus.

  In recent years, high-quality printing has been demanded in image forming apparatuses such as copiers and printers. For this reason, image sharpening, smoothing, edge detection, and the like are performed using various filter circuits such as a Gaussian filter and a Laplacian filter (see, for example, Patent Document 1).

Japanese Patent No. 3950871

  In the filter circuit as described above, the multiplication of the filter coefficient and the image data is often performed, so that the circuit scale of the filter circuit is increased and the cost is increased.

  SUMMARY An advantage of some aspects of the invention is that it provides an image processing apparatus and an image forming apparatus having a filter circuit with a small circuit scale.

  In order to solve the above problems, the present invention is configured as follows.

  The image processing apparatus according to the present invention has the same number of filters as a predetermined number of target pixel data while shifting a predetermined number of target pixel data in pixel data arranged in one line by a number of pixels smaller than the predetermined number. An image processing apparatus that generates pixel data after filter processing based on a product with a coefficient. The image processing apparatus according to the present invention includes a plurality of filter coefficients having the same absolute value among a plurality of filter coefficients in which the absolute values of the filter coefficients are symmetrical about the center of the filter coefficient array. And a delay circuit for delaying the value of the multiplication result by the multiplier until the product of the other of the two filter coefficients and the image data is used. .

  Thereby, since the number of multipliers is reduced, the circuit scale of the filter circuit can be reduced. In particular, since the circuit scale of the multiplier increases as the number of filter coefficients and the number of pixel data bits increases, this effect becomes more prominent as the number of filter coefficient and pixel data bits increases.

  In addition to the image processing apparatus described above, the image processing apparatus according to the present invention may be configured as follows. In this case, the filter coefficients of the plurality of filter coefficients are symmetrical about the center of the filter coefficient array. The image processing apparatus further includes an adder that adds the product of the filter coefficient delayed by the delay circuit and the image data to the multiplication result of the multiplier to generate pixel data after filtering.

  As a result, the circuit scale of the filter circuit that performs the smoothing process can be reduced.

  In addition to the image processing apparatus described above, the image processing apparatus according to the present invention may be configured as follows. In this case, in the plurality of filter coefficients, the absolute values of the filter coefficients are symmetric about the center of the filter coefficient array, and one of the two symmetric filters is positive and the other is negative. . The image processing apparatus adds an adder that generates pixel data after filtering by adding a value obtained by inverting the sign of the product of the filter coefficient delayed by the delay circuit and the image data to the multiplication result of the multiplier. Further prepare.

  As a result, the circuit scale of the filter circuit that performs edge detection processing can be reduced.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the image processing apparatus includes a plurality of line buffers connected in series to hold one line of pixel data, and a plurality of lines that output a product of the pixel data output from each of the plurality of line buffers and a filter coefficient. And a filter circuit. The number of line buffers is one less than the number of target pixel data, and the plurality of line filter circuits have the same multiplier and delay circuit as the above-described multiplier and the above-described delay circuit, respectively.

  As a result, when filtering is performed using pixel data for a plurality of lines, the number of multipliers is reduced, so that the circuit scale of the filter circuit can be further reduced.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the above filter coefficient is a filter coefficient of a Gaussian filter or a Laplacian filter.

  An image forming apparatus according to the present invention includes any of the image processing apparatuses described above, and forms an image based on pixel data after filtering generated by the image processing apparatus.

  According to the present invention, it is possible to obtain an image processing apparatus and an image forming apparatus in which the circuit scale of the filter circuit is small.

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing the configuration of the filter circuit 1 in FIG. FIG. 3 is a diagram illustrating an example of a product of a filter coefficient and pixel data by the image processing apparatus illustrated in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.

  FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention.

  In FIG. 1, the filter circuit 1 shifts three pixel-of-interest data in the pixel data arranged in each of the three lines one pixel at a time, and outputs the same number of filter coefficients as the three pixel-of-interest data. This is a circuit for generating pixel data after filtering based on the product. Note that the image data in FIG. 1 includes pixel data for each line.

  The filter circuit 1 according to the first embodiment performs a filtering process on a total of nine filter coefficients A11 to A33 in three rows and three columns using pixel data for three lines. The pixel data X (i, j) after the filter processing is expressed by the following equation.

  X (i, j) = A11 * d (i + 1, j-1) + A12 * d (i, j-1) + A13 * d (i-1, j-1) + A21 * d (i + 1, j) + A22 * d (I, j) + A23 * d (i-1, j) + A31 * d (i + 1, j + 1) + A32 * d (i, j + 1) + A33 * d (i-1, j + 1)

  As the filter coefficients A11 to A33, for example, filter coefficients of a Gaussian filter or a Laplace filter are used.

  In the case of the smoothing process, the values are symmetric about the center of the filter coefficient array of each row. That is, the values of the filter coefficients A11 and A13 are the same, the values of the filter coefficients A21 and A23 are the same, and the values of the filter coefficients A31 and A33 are the same.

  The line buffers 2-1 and 2-2 are storage circuits that are connected in series and hold one line of pixel data. In the first embodiment, since pixel data for three lines is used, two line buffers 2-1 and 2-2 are provided.

  FIG. 2 is a block diagram showing the configuration of the filter circuit 1 in FIG.

  As shown in FIG. 2, the filter circuit 1 has line filter circuits 11-1 to 11-3 for each line of pixel data, and further calculates the sum of output values of the line filter circuits 11-1 to 11-3. The adder 12 has

  The line filter circuit 11-1 is a circuit that outputs a product of pixel data supplied from the outside and filter coefficients A31, A32, and A33. The line filter circuit 11-2 is a circuit that outputs the product of the pixel data output from the line buffer 2-1 and the filter coefficients A21, A22, A23. The line filter circuit 11-3 is a circuit that outputs the product of the pixel data output from the line buffer 2-2 and the filter coefficients A31, A32, A33.

  In the line filter circuit 11-1, the multiplier 21 calculates the product of the pixel data and the filter coefficient A31. The delay circuit 22 delays the pixel data until the next pixel data is supplied. The multiplier 23 calculates the product of the previous pixel data supplied from the delay circuit 22 and the filter coefficient A32. The delay circuit 24 delays the product of the pixel data and the filter coefficient A31 until the next pixel data is supplied. The delay circuit 25 delays the product of the pixel data and the filter coefficient A31 from the time when the next pixel data is supplied to the time when the next pixel data is supplied. That is, the delay circuits 24 and 25 delay the product of the pixel data and the filter coefficient A31 by two pixels. The delay circuits 22, 24, and 25 are realized by D flip-flops, for example.

  As described above, the multiplier 21 has the same value among the two filter coefficients A31, A33 having the same value among the plurality of filter coefficients A31, A32, A33 whose values are symmetrical around the center of the filter coefficient array. 1 (filter coefficient A31) is multiplied by the pixel data, and the delay circuits 24 and 25 are the product of the other of the two filter coefficients A31 and A33 (filter coefficient A33) and the image data. This is a delay circuit that delays the value of the multiplication result by the multiplier 21 (the product of the pixel data and the filter coefficient A31) until it is used.

  The line filter circuits 11-2 and 11-3 have the same circuit configuration as the line filter circuit 11-1.

  Next, the operation of the above apparatus will be described.

  As image data, pixel data is supplied to the line filter circuit 11-1 and the line buffer 2-1 of the filter circuit 1 at a predetermined period (for example, every clock signal), and from the line buffer 2-1. The pixel data of the same column is supplied to the line filter circuit 11-2 and the line buffer 2-2 of the filter circuit 1, and the pixel data of the same column is supplied from the line buffer 2-2 to the line filter circuit 11 of the filter circuit 1. -3.

  In the line filter circuit 11-1, the product of the pixel data d (i + 1, j + 1) and the filter coefficient A 31 is output from the multiplier 21 at a certain time, and the pixel data d (i, j + 1) is output from the multiplier 23. The product of the filter coefficient A32 is output, and the product of the pixel data d (i-1, j + 1) and the filter coefficient A31 is output from the delay circuit 25.

  Since the value of the filter coefficient A31 and the value of the filter coefficient A33 are the same, the value of the product of the pixel data d (i−1, j + 1) and the filter coefficient A31 is the pixel data d (i−1). , J + 1) and the filter coefficient A33.

  At the same time, from the line filter circuit 11-2, the product of the pixel data d (i + 1, j) and the filter coefficient A21, the product of the pixel data d (i, j) and the filter coefficient A22, and the pixel The product of the data d (i-1, j) and the filter coefficient A21 is output.

  At the same time, the product of the pixel data d (i + 1, j-1) and the filter coefficient A11 and the product of the pixel data d (i, j-1) and the filter coefficient A12 are output from the line filter circuit 11-3. , And the product of the pixel data d (i−1, j−1) and the filter coefficient A11 is output.

  Then, the adder 12 calculates the sum of a total of nine products from the line filter circuits 11-1, 11-2, and 11-3 to obtain pixel data X (i, j) after the filter processing. Output.

  Here, the operation of the line filter circuit 11-1 will be described in more detail. FIG. 3 is a diagram illustrating an example of a product of a filter coefficient and pixel data by the image processing apparatus illustrated in FIG.

  FIG. 3A shows pixel data d1 to d8 supplied to the line filter circuit 11-1. Pixel data d1 to d8 are supplied to the line filter circuit 11-1 in the order of d1, d2,..., D8.

  FIG. 3B shows a product of the filter coefficient and the pixel data necessary for obtaining the pixel data X (i, j) after the filter processing, and FIG. 3C shows the next next filter processing. This shows the product of the filter coefficient and the pixel data necessary for obtaining the subsequent pixel data X (i + 2, j).

  At the time shown in FIG. 3B, the product of the pixel data d5 and the filter coefficient A31 is used. At the time shown in FIG. 3C, the product of the pixel data d5 and the filter coefficient A33 is used.

  For this reason, in the line filter circuit 11-1, the delay circuits 24 and 25 delay the product of the pixel data d5 and the filter coefficient A31 by two pixels, and calculate the pixel data X (i, j) after the filter processing. And it is used twice for the calculation of the pixel data X (i−2, j) after the filter processing. This eliminates the need for a multiplier that calculates the product of the pixel data d5 and the filter coefficient A33.

  As described above, according to the first embodiment, the filter circuit 1 shifts the three pixel-of-interest data in the pixel data arranged in one line by one pixel, and the same number as the three pixel-of-interest data. Pixel data after filtering is generated based on the product with the filter coefficient. The filter circuit 1 includes a plurality of filter coefficients Ai1, Ai2, and Ai3 whose values are symmetric about the center of the filter coefficient array {Ai1, Ai2, Ai3} (i = 1, 2, 3). Until the time when the multiplier 21 that multiplies the pixel data by one of the two filter coefficients Ai1 and Ai3 having the same value and the product of the other of the two filter coefficients and the image data is used. Delay circuits 24 and 25 for delaying the value of the multiplication result by the multiplier 21 are provided.

  Thereby, since the number of multipliers is reduced, the circuit scale of the filter circuit can be reduced. In particular, according to the first embodiment, the circuit scale of the filter circuit that performs the smoothing process can be reduced.

Embodiment 2. FIG.

  In the first embodiment, for smoothing processing, the filter coefficient values are symmetric about the center of the filter coefficient array of each row. In the second embodiment, for each edge detection processing, The absolute value of the filter coefficient is symmetric around the center of the filter coefficient array, and one of the two symmetric filter coefficients is positive and the other is negative. For example, in the case of 3 × 3 filter coefficients A11 to A33, Ai1 = −Ai3 (i = 1, 2, 3).

  In the second embodiment, in the line filter circuits 11-1, 11-2, and 11-3, a circuit that inverts the sign of the output value of the delay circuit 25 is added between the delay circuit 25 and the adder 12. .

  Since other configurations and operations of the image processing apparatus according to the second embodiment are the same as those of the first embodiment, description thereof is omitted.

  As described above, according to the second embodiment, as in the first embodiment, since the number of multipliers is reduced, the circuit scale of the filter circuit can be reduced. In particular, according to the second embodiment, the circuit scale of the filter circuit that performs the edge detection process can be reduced.

  Each embodiment described above is a preferred example of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. It is.

  For example, in each of the above embodiments, filter coefficients of 3 rows and 3 columns are used, but other numbers of filter coefficients (for example, filter coefficients of N rows and N columns, N> 3) may be used. . In that case, the number of line buffers and line filter circuits and the circuit configuration of the line filter circuit may be changed in accordance with the number of filter coefficients. For example, in the first embodiment, when the filter coefficient is 5 rows and 5 columns (that is, when 25 filter coefficients A11 to A55 are used), the number of line buffers is 4, and the line filter circuit The number is 5, the value of the filter coefficient Ai1 and the value of the filter coefficient Ai5 are the same, and the value of the filter coefficient Ai2 and the value of the filter coefficient Ai4 are the same (i = 1..., 5). The product of the pixel data and the filter coefficient Ai1 is delayed by 4 pixels and used as the product of the pixel data and the filter coefficient Ai5, and the product of the pixel data and the filter coefficient Ai2 is delayed by 2 pixels. And a multiplier that calculates the product of the pixel data and the value of the filter coefficient Ai5 by using the pixel data and the value of the filter coefficient Ai4, and the pixel data and the filter coefficient A. The product of the value of 4 may be omitted multiplier for computing.

  The image processing apparatus according to each of the above embodiments can be incorporated in an image forming apparatus such as a printer, a copier, or a multifunction peripheral. In that case, the image forming apparatus forms an image (printing or the like) using the pixel data after the filter processing generated by the image processing apparatus according to the above embodiment.

  The present invention can be applied to an image forming apparatus such as a printer, a copier, and a multifunction peripheral.

2-1, 2-2 Line buffer 11-1 to 11-3 Line filter circuit 12 Adder 21 Multiplier 24, 25 Delay circuit

Claims (6)

A filter based on the product of the predetermined number of target pixel data and the same number of filter coefficients while shifting a predetermined number of target pixel data in the pixel data arranged in one line by a smaller number of pixels than the predetermined number. In an image processing apparatus that generates pixel data after processing,
A multiplier that multiplies pixel data by one of two filter coefficients having the same absolute value among a plurality of filter coefficients whose absolute values are symmetrical about the center of the filter coefficient array; ,
A delay circuit for delaying the value of the multiplication result by the multiplier until the product of the other of the two filter coefficients and the image data is used;
An image processing apparatus comprising: An adder for adding the product of the filter coefficient delayed by the delay circuit and the image data to the multiplication result by the multiplier to generate pixel data after filtering;
The plurality of filter coefficients have symmetrical filter coefficient values around the center of the filter coefficient array;
The image processing apparatus according to claim 1. An adder that generates pixel data after filtering by adding a value obtained by inverting the sign of the product of the filter coefficient delayed by the delay circuit and the image data to the multiplication result by the multiplier;
The plurality of filter coefficients are such that the absolute values of the filter coefficients are symmetric with respect to the center of the filter coefficient array, and one of the two symmetric filters is positive and the other is negative.
The image processing apparatus according to claim 1. A plurality of line buffers connected in series to hold one line of pixel data;
A plurality of line filter circuits for outputting a product of pixel data output from each of the plurality of line buffers and the filter coefficient;
The number of the line buffers is one less than the number of the target pixel data,
The plurality of line filter circuits each include a multiplier and a delay circuit identical to the multiplier and the delay circuit;
The image processing apparatus according to claim 1, wherein:   The image processing apparatus according to claim 1, wherein the filter coefficient is a filter coefficient of a Gaussian filter or a Laplacian filter. An image processing apparatus according to any one of claims 1 to 5, comprising:
Forming an image based on the filtered pixel data generated by the image processing device;
An image forming apparatus.

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